DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on June 11, 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of 11,776,911 B2 has been reviewed and is NOT accepted.
The terminal disclaimer does not comply with 37 CFR 1.321 because: the title of the person signing on behalf of the applicant is missing.
It should be noted that applicant is not required to pay another disclaimer fee as set forth in 37 CFR 1.20(d) when submitting a replacement or supplemental terminal disclaimer.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 6, 8, 10-15 and 19-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of "the layer", as recited in claims 1 (lines 6-8), 2, 8 (lines 5-6), 12-14, 15 (lines 5 and 8), 19 and 22, is unclear as to which layer applicant refers: “a gate spacer layer” and/or “a layer comprising a carbon dopant”, as recited in claims 1 (lines 3-4), 8 (lines 2-3) and 15 (lines 3-4), respectively.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 6, 8, 10-15 and 19-28, as best understood, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14-19 of U.S. Patent No. 11,776,911 in view of Su et al. (2014/0015104).
U.S. Patent No. 11,776,911 discloses in claim 14 or 19:
As for claim 1, a method, comprising:
forming a gate structure on a substrate;
forming a gate spacer layer on a sidewall of the gate structure;
forming a layer comprising a carbon on the gate spacer layer;
performing an annealing process to diffuse the carbon from the layer into a portion of the substrate below the gate spacer layer;
after performing the annealing process, removing the layer (claim 14);
forming a recess in the substrate on one side of the gate spacer layer opposite to the dummy gate structure (claim 19); and
forming an epitaxy feature in the recess of the substrate (claim 19).
As for claim 8, a method, comprising:
forming a gate structure on a substrate;
forming a gate spacer layer on a sidewall of the gate structure;
forming a layer comprising a carbon on the gate spacer layer;
performing an annealing process after forming the layer;
after performing the annealing process, removing the layer;
removing a horizontal portion of the gate spacer layer to expose a surface of the substrate; and
forming an epitaxy structure in the substrate (claim 14).
As for claim 15, a method, comprising:
forming a gate structure over (a channel region of) a substrate;
forming a gate spacer layer on a sidewall of the gate structure;
forming a layer comprising a carbon over the gate spacer layer;
performing an annealing process to diffuse the carbon from the layer into the gate spacer layer and into the substrate, such that a first carbon-containing diffusion barrier is formed in the gate spacer layer and a second carbon-containing diffusion barrier is formed in the substrate;
after performing the annealing process, removing the layer; and
forming an epitaxy feature on the substrate (claim 14).
Claims 14 or 19 of U.S. Patent No. 11,776,911 do not disclose that the gate structure is a dummy gate structure, the carbon is a carbon dopant (claims 1, 8 and 15); forming a recess in the substrate on one side of the gate spacer layer opposite to the dummy gate structure; and forming the epitaxy feature in the recess of the substrate (claim 1); the layer is formed using a plasma doping (claim 14); forming the dummy gate structure over a channel region of the substrate (claim 15); the dummy gate structure comprises a gate dielectric layer and a dummy gate electrode (claims 21, 25 and 28); the annealing process comprises rapid thermal annealing, spike annealing, millisecond annealing, or laser annealing (claims 23 and 26).
Su et al. teach in Figs. 1, 2, 3A-3C and related text:
As for claims 1, 8 and 15, forming a dummy gat structure 26/28 on a substrate 10 ([0009]);
forming the layer 42 comprising a carbon dopant 40/44/48 on the gate spacer layer 32/20.
As for claim 1, forming a recess (not shown) in the substrate on one side of the gate spacer layer opposite to the dummy gate structure ([0012]); and
forming the epitaxy feature in the recess of the substrate ([0012]).
As for claim 14, the layer is formed using a plasma doping (Figs. 3A-3C; [0016]-[0021]).
As for claim 15, forming the dummy gate structure over a channel region of the substrate (Fig. 1; [0010]).
As for claims 21, 25 and 28, the dummy gate structure comprises a gate dielectric layer and a dummy gate electrode ([0010]).
As for claims 23 and 26, the annealing process comprises rapid thermal annealing, spike annealing, millisecond annealing, or laser annealing ([0019]; [0023]).
U.S. Patent No. 11,776,911 and Su et al. are analogous art because they are directed to a method for fabricating a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify U.S. Patent No. 11,776,911 with the specified feature(s) of Su et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form the gate structure being a dummy gate structure, the carbon being a carbon dopant; form a recess in the substrate on one side of the gate spacer layer opposite to the dummy gate structure, and form the epitaxy feature in the recess of the substrate; form the layer using a plasma doping; form the dummy gate structure over a channel region of the substrate; include the dummy gate structure comprising a gate dielectric layer and a dummy gate electrode; include the annealing process comprising rapid thermal annealing, spike annealing, millisecond annealing, or laser annealing, as taught by Su et al., in U.S. Patent No. 11,776,911, in order to in order to improve polysilicon depletion effect, provide very low resistance, no dopant penetration possible and better compatibility with high-k gate dielectric, eliminate gate depletion and boron penetration issues and lower gate sheet resistance; achieve better control of the location of the dopant region; increase the density of the device and improve the performance of the device.
As for claim 2, the combined device shows the layer is formed using a plasma-assisted process (911: claim 16).
As for claim 6, the combined device shows etching the gate spacer layer to expose a top surface of the substrate prior to forming the recess in the substrate (911: claim 14).
As for claim 10, the combined device shows the annealing process is performed such that first carbon-containing diffusion barriers are formed in the gate spacer layer and second carbon-containing diffusion barriers are formed in the substrate (911: claim 14).
As for claim 11, the combined device shows one of the second carbon-containing diffusion barriers is below an angular corner formed by an up-slant facet and a down-slant facet of the epitaxy structure (911: claim 15).
As for claim 12, the combined device shows the layer is formed using a plasma-assisted process (911: claim 16).
As for claims 13, 19 and 22, the combined device shows the layer (extends to) is above a top surface of the dummy gate structure (911: claim 17).
As for claim 20, the combined device shows removing a horizontal portion of the gate spacer layer to form a gate spacer prior to forming the epitaxy feature (911: claim 14).
As for claims 24 and 27, the combined device shows etching the substrate to form a recess, wherein the epitaxy structure is formed in the recess (911: claim 19).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 6, 8, 10-15, 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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