DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Feb. 23rd 2026 has been entered. Claims 1-2, 5, 7-18 and 20-24 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bao et al. (US 9997519) in view of Lee et al. (US 20200144255), Xu et al. (US 20160013289) and Cheng (US 20190304848).
Regarding claim 9, Bao teaches a device (Abstract) comprising:
a first set of nanostructures (fig. 6B, structure of nanosheet channels 214 on the right; col. 5, lin. 1) on a substrate (substrate 202; col. 4, lin. 29), the first set of nanostructures (214) comprising a first channel region (region of 214);
a second set of nanostructures (structure of nanosheet channels 215 on the left; col. 6, lin. 14) on the substrate (202), the second set of nanostructures (215) comprising a second channel region (region of 215);
a gate dielectric layer (high - k dielectric layer 218 in 201; col. 5, lin. 47-48) wrapping around each of the first and second sets of nanostructures (214, 215);
a first work function tuning layer (WF1 metal layer 222; col. 5, lin. 52-53) on the gate dielectric layer (218) of the first set of nanostructures (214), the first work function tuning layer (222) wrapping around each of the first set of nanostructures (214);
a second work function tuning layer (WF2 metal layer 226; col. 5, lin. 56) over the first set of nanostructures (214) and over the gate dielectric layer (218) of the second set of nanostructures (215), the second work function tuning layer having a different material composition than the first work function tuning layer (the materials used for WF1 metal layer 222 may be different than the material used for forming WF2 metal layer 226; col. 5, lin. 64-66); and
a fill layer (gate electrode 230; col. 8, lin. 20) on the second work function tuning layer (226).
Bao fails to teach the first work function tuning layer comprises an atomic percentage (at%) of aluminum in a range from 20% to 40%
However, Lee teaches the first work function tuning layer (Lee: work function pattern WF; para. 0039) comprises an atomic percentage (at%) of aluminum (Lee: aluminum; para. 0039) in a range from 0.1 at % to about 25 at % (Lee: 0.1 at % to about 25 at %; para. 0039), which overlaps the range from 20% to 40%.
Lee and Bao are considered to be analogous to the claimed invention because they are in the same field of gate structure semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the atomic percentage range from 0.1 at % to about 25 at % to 20% to 40%.
Doing so would realize a work function layer adjusted to suitable work function pattern (Lee: para. 0039). Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Bao in view of Lee fails to teach a protective layer on the first work function tuning layer, the protective layer wrapping around each of the first set of nanostructures, wherein the protective layer directly contacts the first work function tuning layer on the first set of nanostructures;
the second work function tuning layer over the protective layer of the first set of nanostructures.
However, Xu teaches a protective layer (Xu: fig. 3, barrier layer 301 and amorphous silicon layer 302; para. 0049) on the first work function tuning layer (Xu: work function layer in semiconductor substrate structure 309; para. 0052, similar to 222 of Bao), the protective layer (Xu: 301, 302 is on 222 of Bao, which wrapping around 214 of Bao) wrapping around each of the first set of nanostructures (Bao: 214), wherein the protective layer (Xu: 301, 302) directly contacts the first work function tuning layer (Xu: 309) on the first set of nanostructures (Bao: 214);
the second work function tuning layer (Bao: 226) over the protective layer (Xu: 301, 302 is on 222 of Bao and 226 on 222) of the first set of nanostructures (Bao: 214).
Xu, Lee and Bao are considered to be analogous to the claimed invention because they are in the same field of gate structure semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the protective layer as taught by Xu.
Doing so would realize barrier layers that penetration or diffusion of unwanted particles may be substantially blocked, and interface defects may be minimized or substantially prevented (Xu: para. 0065)
Bao in view of Lee and Xu fails to explicitly teach the first work function tuning layer on and directly contacting the gate dielectric layer;
wherein the second work function tuning layer directly contacts the gate dielectric layer on the second set of nanostructures.
However, Cheng teaches the first work function tuning layer (Cheng: fig. 8A, first work function metal 112 with metal and TiN; para. 0046, similar to 222, 220 of Bao) on and directly contacting the gate dielectric layer (Cheng: high-k material 110; para. 0042, similar to 218 of Bao);
wherein the second work function tuning layer (Cheng: second work function metal 802 with metal and TiN; para. 0046, similar to 226, 224 of Bao) directly contacts the gate dielectric layer (Cheng: 110) on the second set of nanostructures (Cheng: nanosheets 108 on the right; para. 0048, similar to 215 of Bao).
Cheng, Xu, Lee and Bao are considered to be analogous to the claimed invention because they are in the same field of gate structure semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first work function tuning layer and the second work function tuning layer directly contacting the gate dielectric layer as taught by Cheng.
Doing so would realize work function metal physically contacting the gate dielectric layer to reduce manufacturing cost by not forming a separate barrier layer.
Regarding claim 14, Bao in view of Lee, Xu and Cheng further teaches the device of claim 9, wherein the second work function tuning layer (Bao: fig. 6B, 226) separates and fills an area (Bao: area between 218 on the left) between respective portions of the gate dielectric layer (Bao: 218) on adjacent nanostructures (Bao: 215) of the second set of nanostructures (Bao: 215).
Regarding claim 15, Bao in view of Lee, Xu and Cheng further teaches the device of claim 9, wherein the fill layer (Bao: fig. 6B, 230) does not extend between adjacent nanostructures (Bao: 215) of the second set of nanostructures (Bao: 215).
Regarding claim 16, Bao in view of Lee, Xu and Cheng further teaches the device of claim 9, wherein the fill layer (Bao: fig. 6B, 230) does not extend between adjacent nanostructures (Bao: 214) of the first set of nanostructures (Bao: 214).
Claims 17-18, 20 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Bao in view of Cheng and Xu.
Regarding claim 17, Bao teaches a device (Abstract) comprising:
a first set of nanostructures (fig. 6B, structure of nanosheet channels 214 on the right; col. 5, lin. 1) on a substrate (substrate 202; col. 4, lin. 29);
a second set of nanostructures (structure of nanosheet channels 215 on the left; col. 6, lin. 14) on the substrate (202);
a gate dielectric layer (high - k dielectric layer 218 in 201; col. 5, lin. 47-48) wrapping around each of the first and second sets of nanostructures (214, 215);
a first work function tuning layer (WF1 metal layer 222; col. 5, lin. 52-53) on the gate dielectric layer (218) of the first set of nanostructures (214), the first work function tuning layer (222) wrapping around each of the first set of nanostructures (214), the first work function tuning layer (222) comprising an n-type work function metal (222, WF1 metal has higher Vt for nFET; col. 4, lin. 4-5);
a glue layer (top capping layer 212, which may be formed of TiN, including material equivalent to the glue layer in the instant specification; col. 5, lin. 16, 18) on the first work function tuning layer (222);
a second work function tuning layer (WF2 metal layer 226; col. 5, lin. 56) on the glue layer (212) of the first set of nanostructures (214) and on the gate dielectric layer (218) of the second set of nanostructures (215); and
a fill layer (gate electrode 230; col. 8, lin. 20) on the second work function tuning layer (226), wherein the fill layer (230) does not extend between adjacent nanostructures (215) of the second set of nanostructures (215), and wherein the fill layer (230) does not extend between adjacent nanostructures (214) of the first set of nanostructures (214).
Bao fails to explicitly teach the first work function tuning layer on and directly contacting the gate dielectric layer.
However, Cheng teaches the first work function tuning layer (Cheng: fig. 8A, first work function metal 112 with metal and TiN; para. 0046, similar to 222, 220 of Bao) on and directly contacting the gate dielectric layer (Cheng: high-k material 110; para. 0042, similar to 218 of Bao).
Cheng and Bao are considered to be analogous to the claimed invention because they are in the same field of gate structure semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first work function tuning layer on and directly contacting the gate dielectric layer as taught by Cheng into Bao.
Doing so would realize work function metal physically contacting the gate dielectric layer to reduce manufacturing cost by not forming a separate barrier layer.
In addition, Bao in view of Cheng fails to teach an amorphous silicon layer between the first work function tuning layer and the glue layer on the first set of nanostructures, the amorphous silicon layer wrapping around each of the
first set of nanostructures, the amorphous silicon layer extending from directly contacting the first work function tuning layer to the glue layer.
However, Xu teaches an amorphous silicon layer (Xu: fig. 3, amorphous silicon layer 302; para. 0049) between the first work function tuning layer (Xu: work function layer in semiconductor substrate structure 309; para. 0052, similar to 222 of Bao) and the glue layer (Xu: barrier layer 303 may with TiN; para. 0049, 0053, similar to 212 of Bao) on the first set of nanostructures (Bao: 214, Xu: 302 is on 222 of Bao, which is on 214), the amorphous silicon layer (Xu: 302 is on 222 of Bao, which wrapping around 214 of Bao) wrapping around each of the first set of nanostructures (Bao: 214), the amorphous silicon layer (Xu: 302) extending from the first work function tuning layer (Xu: 309) to the glue layer (Xu: 303).
Xu, Cheng and Bao are considered to be analogous to the claimed invention because they are in the same field of gate structure semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the amorphous silicon layer as taught by Xu.
Doing so would realize barrier layers that penetration or diffusion of unwanted particles may be substantially blocked, and interface defects may be minimized or substantially prevented (Xu: para. 0065).
Regarding claim 18, Bao in view of Cheng and Xu further teaches the device of claim 17, wherein the first work function tuning layer (Bao: fig. 6B, 222) comprises an n-type work function metal (Bao: 222, WF1 metal has higher Vt for nFET; col. 4, lin. 4-5), the second work function tuning layer (Bao: 226) comprises a p-type work function metal (Bao: 226, WF2 metal has higher Vt for PFET; col. 4, lin. 8-11), and the p-type work function metal is different from the n-type work function metal (Bao: the materials used for WF1 metal layer 222 may be different than the material used for forming WF2 metal layer 226; col. 5, lin. 64-66).
Regarding claim 20, Bao in view of Cheng and Xu further teaches the device of claim 17, wherein the glue layer (Bao: fig. 6B, 212) comprises titanium nitride, titanium aluminum carbide, tantalum aluminum carbide, silicon-doped tantalum aluminide (Bao: 212 may be formed of TiN; col. 5, lin. 18).
Regarding claim 23, Bao in view of Cheng and Xu further teaches the device of claim 17, wherein a thickness ratio of the glue layer (Xu: fig. 3, thickness pf 303) to the amorphous silicon layer (thickness of 302) is at least 5:1 (more than 5 times from the fig.).
Bao in view of Cheng and Xu as applied to claim 17 fails to explicitly teach the amorphous silicon layer has a thickness in a range from 0.1 nm to 10 nm.
However, Xu teaches the amorphous silicon layer (Xu: fig. 3, 302) has a thickness less than 0.4~0.6 nm (Xu: thickness 20~30 A for 303 and more than 5 times thicker than 302), which overlaps in a range from 0.1 nm to 10 nm.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the amorphous silicon layer has a thickness from 0.4~0.6 nm to a range from 0.1 nm to 10 nm.
Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges).
Allowable Subject Matter
Claims 1-2,5,7-8,21-22 and 24 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 would be allowable for disclosing “a protective layer between the first work function tuning layer and the glue layer on the first set of nanostructures, the protective layer wrapping around each of the first set of nanostructures, wherein the protective layer directly contacts both the first work function tuning layer and the glue layer, and the second set of nanostructures is free of the protective layer, wherein the protective layer is an amorphous silicon layer.”
Claims 2,5,7-8,21-22 and 24 would be also allowable because they are dependent on claim 1.
Claims 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 would be allowable for disclosing “the protective layer is an amorphous silicon layer”.
Claims 11-13 would be also allowable because they are dependent on claim 10.
Response to Arguments
Applicant’s arguments with respect to claims 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed on Feb. 23rd 2026 of claim 9 have been fully considered but they are not persuasive.
With respect to pages 8-9 of applicant’s response of claim 9 is rejected under 35 U.S.C.103.
Applicant submits "the cited references fail to teach or suggest a protective layer directly contacting a first work function tuning layer on a first set of nanostructures and a second work function tuning layer directly contacting the gate dielectric layer on the second set of nanostructures".
The examiner respectfully disagrees.
As shown in fig. 3 of Xu, Xu teaches adding a protective layer (301, 302, which includes two layers) directly contacting a first work function tuning layer (309) on a first set of nanostructures (214 of Bao, wherein 309 of Xu similar to 222 of Bao on 214 of Bao). In addition, as shown in fig. 8A of Cheng, Cheng teaches a second work function tuning layer (802, which includes both metal and TiN together as work function tuning layer, similar to 222 and 220 of Bao) directly contacting the gate dielectric layer (110) on the second set of nanostructures (108). As result, given a broadest reasonable interpretation, Bao in view of Lee, Xu and Cheng teaches all limitations of claims 9. Details of rejections are discussed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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