Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election without traverse of Group I, Species #2, as shown in FIG. 11, in the reply filed on November 03, 2025 is acknowledged. Applicant identified claims 1-3, 5 and 12-13 are readable on the Elected Group I and Species #2.
Non-Elected Invention and Species, Claims 4, 6-11 and 14-21 have been withdrawn from consideration. Claims 1-21 are pending.
Action on merits of Elected Invention and Species, claims 1-3, 5 and 12-13 follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 09, 2023, October 03, 2024 and June 30, 2025 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
FIELD EFFECT TRANSISTOR HAVING A PLURALITY OF P-TYPE DEEP LAYERS AND PLURALITY OF N-TYPE DEEP LAYERS LATERALLY AND ALTERNATIVELY FORMED UNDER P-TYPE BODY LAYER EXTENDING IN A SECOND DIRECTION PERPENDICULAR TO THE DIRECTION OF THE TRENCH
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 5 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “wherein a depth from the bottom surface of the trench to a lower surface of the p-type trench lower layer is identical to a depth from the upper surface of the semiconductor substrate to a lower surface of the p-type body layer” (claim 5) (emphasis added) in the application as filed.
Applicant must cancel the un-support new matters in response to the Office Action.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3, 5 and 12-13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 12-13, recites: “a p-type trench lower layer located below the n-type source layer and extending in a longitudinal direction of the trench …”;
Lines 21-22, recites: “the plurality of p-type deep layers are spaced at intervals in a second direction perpendicular to the first direction”.
What is the difference between “a longitudinal direction of the trench” and “second direction”?
The limitations create a confusion and/or contradictory.
Therefore, claim 1 and all dependent claims are indefinite.
Claim 5 recites: the field effect transistor of claim 1, wherein a depth from the bottom surface of the trench to a lower surface of the p-type trench lower layer is identical to a depth from the upper surface of the semiconductor substrate to a lower surface of the p-type body layer”.
However, as shown in FIG. 11, the depth of the “p-type trench lower layer” 35 is much deeper than the depth of the p-type body layer 34.
Claim 5 contravenes the disclosure. Therefore, claim 5 is indefinite.
Claim 13 recites: the field effect transistor of claim 1, wherein each of the plurality of p-type deep layers has a p-type impurity concentration being larger in a depth range corresponding to the n-type deep lower layer than a depth range corresponding to the n-type deep upper layer.
The limitation is incomprehensible.
The claim is generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over NOBORIO et al. (US. Pub. No. 2012/0319136) in view of KOBAYASHI et al. (US. Pub. No. 2019/0165162) both of record.
With respect to claim 1, As best understood by the Examiner, NOBORIO teaches a field effect transistor substantially as claimed including:
a semiconductor substrate (1) having a trench (6) at an upper surface of the semiconductor substrate;
a gate insulating film (8) covering an inner surface of the trench (6); and
a gate electrode (9) located inside the trench (6), the gate electrode (9) being insulated from the semiconductor substrate through the gate insulating film (8), wherein
the semiconductor substrate includes:
an n-type source layer (4) being in contact with the gate insulating film (8) at a side surface of the trench;
a p-type body layer (3) being in contact with the gate insulating film (8) at the side surface of the trench below the n-type source layer (4);
a trench lower layer located below the n-type source layer (4) and extending in a longitudinal direction of the trench (6) in a top view of the semiconductor substrate;
a plurality of p-type deep layers (10); and
a plurality of n-type deep layers,
each of the plurality of p-type deep layers (10) protrudes and extends downward from the p-type body layer (3) to a location below a bottom surface of the trench (6),
each of the plurality of p-type deep layers (10) extends in a first direction (x) intersecting the trench (6) in the top view of the semiconductor substrate,
the plurality of p-type deep layers (10) are spaced at intervals in a second direction (y) perpendicular to the first direction (x) in the top view of the semiconductor substrate, and are in contact with the trench lower layer located below the trench,
each of the plurality of n-type deep layers is located in a corresponding one of the intervals, and is in contact with the gate insulating film (8) at the side surface of the trench (6) located below the p-type body layer (3),
each of the n-type deep layers includes:
an n-type deep lower layer; and
an n-type deep upper layer (2a) located above the n-type deep lower layer, the n-type deep upper layer (2a) having an n-type impurity concentration (N) being higher than the n-type deep lower layer (N-), and
the n-type deep upper layer (2a) is located above the bottom surface of the trench (6). (See FIGs. 20-21).
Thus, NOBORIO is shown to teach all the features of the claim with the exception of explicitly disclosing a p-type trench lower layer extending in a longitudinal direction of the trench.
However, KOBAYASHI teaches a field effect transistor including:
a semiconductor substrate (1) having a trench (18) at an upper surface of the semiconductor substrate;
a gate insulating film (9) covering an inner surface of the trench (18); and
a gate electrode (10) located inside the trench (18), the gate electrode (10) being insulated from the semiconductor substrate through the gate insulating film (9), wherein
the semiconductor substrate includes:
an n-type source layer (7) being in contact with the gate insulating film (9) at a side surface of the trench;
a p-type body layer (6) being in contact with the gate insulating film (9) at the side surface of the trench below the n-type source layer (4);
a p-type trench lower layer (15) located below the n-type source layer (7) and extending in a longitudinal direction of the trench (18) in a top view of the semiconductor substrate. (See FIG. 18).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to the transistor of NOBORIO having the p-type trench lower layer located below the n-type source layer and extending in a longitudinal direction of the trench as taught by KOBAYASHI to provide protection for the gate insulating film.
With respect to claim 2, the n-type source layer (4) of NOBORIO extends in a direction parallel to the longitudinal direction of the trench (6) in the top view of the semiconductor substrate.
With respect to claim 3, the semiconductor substrate of NOBORIO further includes a contact layer (5) located above the p-type body layer (3) and having a p-type impurity concentration (N+) being higher than (p) the p-type body layer (3), and the contact layer (5) extends in a direction parallel to the longitudinal direction of the trench (6) in the top view of the semiconductor substrate.
With respect to claim 12, in view of KOBAYASHI, the semiconductor substrate (1) further includes an n-type drift layer (2) located below the plurality of n-type deep layers (5a) and being in contact with the plurality of n-type deep layers (5a), and the n-type drift layer (2) has a concentration (n-) being lower than (n) the plurality of n-type deep layers (5a).
With respect to claim 13, As best understood by the Examiner, in view of KOBAYASHI, each of the plurality of p-type deep layers (15) has a p-type impurity concentration being larger in a depth range corresponding to the n-type deep lower layer (5a) than a depth range corresponding to the n-type deep upper layer (5b).
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over NOBORIO and KOBAYASHI as applied to claim 1 above, and further in view of TANAK et al. (US. Pub. No. 2018/0315819).
As best understood by the Examiner, NOBORIO, in view of KOBAYASHI teaches the transistor as described in claim 1 above including the p-type trench lower layer located below the n-type source layer and extending in a longitudinal direction of the trench.
Thus, NOBORIO and KOBAYASHI are shown to teach all the features of the claim with the exception of explicitly disclosing a depth from the bottom surface of the trench to a lower surface of the p-type trench lower layer is identical to a depth from the upper surface of the semiconductor substrate to a lower surface of the p-type body layer.
However, TANAKA teaches a transistor including:
a p-type body layer (5); and
a p-type trench lower layer (8) located below n-type source layer (3),
wherein a depth from the bottom surface of trench (7) to a lower surface of the p-type trench lower layer (8) appears to be identical to a depth from the upper surface of the semiconductor substrate to a lower surface of the p-type body layer (5). (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the transistor of NOBORIO, in view of KOBAYASHI, having the depth from the bottom surface of trench to a lower surface of the p-type trench lower layer being identical to the depth from the upper surface of the semiconductor substrate to the lower surface of the p-type body layer as taught by TANAKA for the same intended purpose of provide protection for the gate insulating layer.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893