Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 30, 2026 has been entered.
Status of the Claims
Group I, Species #2, as shown in FIG. 11, is elected.
Amendment filed July 30, 2026 is acknowledged. New Claims 23-26 have been added. Claims 12-13 have been cancelled. Claim 1 has been amended. Non-Elected Invention and Species, Claims 4, 6-11 and 14-21 have been withdrawn from consideration. Claims 1-11 and 14-26 are pending.
Action on merits of Elected Invention and Species, claims 1-3, 5 and 22-26 follows.
Response to Arguments
Regarding to the support for the new limitation of claim 1, “the p-type trench lower layer extends below bottom surfaces of the plurality of n-type deep layers and the plurality of p-type deep layers in a third direction perpendicular to the first direction and the second direction”, Applicant asserts that, ¶ [0036] and FIG. 11 provide support for the new limitation.
Although FIG. 11 shows that the bottom of the p-type trench lower layer 35 is lower than that of n-type deep layer 37, hence lower than p-type deep layer 36. However, ¶ [0036] does not disclose such limitation.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 36 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “wherein a depth-direction concentration profile of each of the plurality of p-type trench lower layers matches a depth-direction concentration profile of the p-type body layer” (new claim 26) (emphasis added) in the application as filed.
Applicant must cancel the un-support new matters in response to the Office Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 22-23 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over NOBORIO et al. (US. Pub. No. 2012/0319136) of record, in view of SUZUKI et al. (US. Pub. No. 2016/0247910).
With respect to claim 1, NOBORIO teaches a field effect transistor substantially as claimed including:
a semiconductor substrate (1) having a trench (6) at an upper surface of the semiconductor substrate;
a gate insulating film (8) covering an inner surface of the trench (6); and
a gate electrode (9) located inside the trench (6), the gate electrode (9) being insulated from the semiconductor substrate through the gate insulating film (8),
wherein the semiconductor substrate includes:
an n-type source layer (4) being in contact with the gate insulating film (8) at a side surface of the trench;
a p-type body layer (3) being in contact with the gate insulating film (8) at the side surface of the trench below the n-type source layer (4);
a plurality of p-type deep layers (10);
a plurality of n-type deep layers; and
an n-type drift layer (2) located below and in contact with the plurality of n-type deep layers,
each of the plurality of p-type deep layers (10) protrudes and extends downward from the p-type body layer (3) to a location below a bottom surface of the trench (6),
each of the plurality of p-type deep layers (10) extends in a first direction (x) intersecting the trench (6) in the top view of the semiconductor substrate,
the plurality of p-type deep layers (10) are spaced at intervals in a second direction (y) perpendicular to the first direction (x) in the top view of the semiconductor substrate, and are in contact with the trench lower layer located below the trench,
the second direction (y) is the longitudinal direction of the trench (6),
each of the plurality of n-type deep layers is located in a corresponding one of the intervals, and is in contact with the gate insulating film (8) at the side surface of the trench (6) located below the p-type body layer (3),
each of the n-type deep layers includes:
an n-type deep lower layer (shown as n-); and
an n-type deep upper layer (2a) located above the n-type deep lower layer, the n-type deep upper layer (2a) having an n-type impurity concentration (n+) being higher than the n-type deep lower layer (shown as n-),
the n-type deep upper layer (2a) is located above the bottom surface of the trench (6), and
the n-type drift layer (2) has an n-type impurity concentration that is lower than the plurality of n-type deep layers, and
the trench (6) extends into the plurality of n-type deep layers (2a) and the plurality of p-type deep layers (10) in a third direction (z) perpendicular to the first direction (x) and the second direction (y). (See FIGs. 25A-F).
Thus, NOBORIO is shown to teach all the features of the claim with the exception of explicitly disclosing a p-type trench lower layer located below the trench.
However, SUZUKI teaches a field effect transistor including:
a p-type trench lower layer (10) located below the trench (7) and extending in a longitudinal direction of the trench (7) in a top view of the semiconductor substrate;
the p-type trench lower layer (10) extends below bottom surfaces of the n-type deep layers (3) in a third direction (z) perpendicular to the first direction (x) and the second direction (y). (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to the transistor of NOBORIO having the p-type trench lower layer located below the trench as taught by SUZUKI to prevent the gate oxide film from being damage.
Since the bottom surface of the plurality of p-type deep layer (10) of NOBORIO is at the same level as that of the plurality of n-type deep layers (2a), in view of SUZUKI, the p-type trench lower layer (10) extends below bottom surfaces of the n-type deep layers (3) and the plurality of p-type deep layers, of NOBORIO, in a third direction (z) perpendicular to the first direction (x) and the second direction (y).
With respect to claim 2, the n-type source layer (4) of NOBORIO extends in a direction parallel to the longitudinal direction of the trench (6) in the top view of the semiconductor substrate.
With respect to claim 3, the semiconductor substrate of NOBORIO further includes a contact layer (5) located above the p-type body layer (3) and having a p-type impurity concentration (N+) being higher than (p) the p-type body layer (3), and the contact layer (5) extends in a direction parallel to the longitudinal direction of the trench (6) in the top view of the semiconductor substrate.
With respect to claim 5, in view of SUZUKI, the field effect transistor has a thickness from the bottom surface of trench (7) to a lower surface of the p-type trench lower layer (10) and a thickness from the upper surface of the semiconductor substrate to a lower surface of the p-type body layer (4).
Thus, NOBORIO and SUZUKI are shown to teach all the features of the claim with the exception of explicitly disclosing the two thicknesses being identical.
Note that, the claimed identical thickness does not appear to be critical.
There is no correlation between the two thicknesses. In view of SUZUKI, the thickness of the p-type trench lower layer (10) contributes to the protection of the gate insulating film at the bottom of the trench; while the thickness from the upper surface of the substrate to the lower surface of the p-type body layer contributes, most likely, to the channel length.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the transistor of NOBORIO, in view of SUZUKI, having the thickness from the bottom surface of trench to a lower surface of the p-type trench lower layer being identical to the thickness from the upper surface of the semiconductor substrate to the lower surface for the same intended purpose of reduce electric field concentration in the gate insulating film.
Moreover, forming such thicknesses is well within the ability of one having ordinary skill in the art.
With respect to claim 22, each of the plurality of p-type deep layers (10) of NOBORIO is in contact with the p-type body layer (3) at both sides of the trench (6), and a p-type impurity concentration (E17 to E19cm-3) of each of the plurality of p-type deep layers (10) is higher than a p-type impurity concentration (5E15 to 5E16cm-3) of the p-type body layer (3).
With respect to claim 23, in view of SUZUKI, a p-type impurity concentration of the p-type trench lower layer (2E17 to 5E17cm-3) is lower than a p-type impurity concentration (E17 to E19cm-3) of each p-type deep layer (10a) of the plurality of p-type deep layers of NOBORIO.
With respect to claim 25, in view of SUZUKI, the p-type trench lower layer (10) includes a plurality of segments (10) separated from each other the second direction, and each p-type deep layer (10) of the plurality of p-type deep layers of NOBORIO passes through a region between two adjacent trenches (6), thus, in view of SUZUKI, passes through a region between two adjacent segments under the trenches (7) of the plurality of segments.
With respect to claim 26, As best understood by the Examiner, a depth-direction concentration profile of each of the plurality of p-type trench lower layer (10) of SUZUKI, matches a depth-direction concentration profile of the p-type body layer (4).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over NOBORIO ‘136 and SUZUKI ‘910 as applied to claim 1 above, and further in view of KOBAYASHI et al. (US. Pub. No. 2018/0040698).
NOBORI, in view of SUZUKI teaches the field effect transistor as described in claim 1 above including: each n-type deep layer (2a) of the plurality of n-type deep layers is in contact with a surface of a corresponding p-type deep layer (10) of the plurality of p-type deep layers.
Thus, NOBORIO and SUZUKI are shown to teach all the features of the claim with the exception of explicitly disclosing each n-type deep layer of the plurality of n-type deep layers is in contact with a bottom surface of a corresponding p-type deep layer.
However, KOBAYASHI teaches a field effect transistor including: each n-type deep layer (15a) of the plurality of n-type deep layers (15) is in contact with a bottom surface of a corresponding p-type deep layer (3a). (See FIG. 15).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the n-type deep layers of NOBORIO being in contact with a bottom surface of a corresponding p-type deep layer as taught by KOBAYASHI to enable suppression of short channel effects.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893
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