DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 9/14/2026 is acknowledged.
Applicant amended claims 1, 6-8, 13, and 14; and cancelled claim 21.
Applicant added claim 22.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/17/2026 has been entered.
Claim Objections
At the following locations, indicated by the notation [claim(s), line(s)], please make the following changes to provide better clarity, proper grammar, or proper antecedent basis:
[1, 9] change “the shallow trench isolation region, and;” to “the shallow trench isolation region; and”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0098750) (hereafter Lin), in view of Hsu et al. (US 2020/0091311) (hereafter Hsu).
Regarding claim 1, Lin discloses a semiconductor device, comprising:
a first semiconductor fin (first 204 from the left corner of Fig. 13, paragraph 0030) and a second semiconductor fin (second 204 from the left corner of Fig. 13, paragraph 0030) over a first area (left portion of 202 in Fig. 13) of a substrate 202 (Fig. 13, paragraph 0030);
a third semiconductor fin (third 204 from the left corner of Fig. 13, paragraph 0030) and a fourth semiconductor fin (fourth 204 from the left corner of Fig. 13, paragraph 0030) over a second area (right portion of 202 in Fig. 13) of the substrate 202 (Fig. 13);
a shallow trench isolation region 302 (Fig. 13, paragraph 0034) disposed in the substrate 202 (Fig. 13);
a first dielectric fin (lower layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13, paragraph 0038, wherein “forming cut features with multiple layers of different materials”) disposed between the first semiconductor fin (first 204 from the left corner of Fig. 13) and the second semiconductor fin (second 204 from the left corner of Fig. 13), and wherein a bottom surface of the first dielectric fin (lower layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13) is below the top surface of the shallow trench isolation region 302 (Fig. 13);
a first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13, paragraph 0038) that is disposed over the first dielectric fin (lower layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13) between the first semiconductor fin (first 204 from the left corner of Fig. 13) and the second semiconductor fin (second 204 from the left corner of Fig. 13);
a second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13, paragraph 0037) filled with a dielectric material (see paragraph 0037) is formed between the third semiconductor fin (third 204 from the left corner of Fig. 13) and the fourth semiconductor fin (fourth 204 from the left corner of Fig. 13);
wherein a first distance (horizontal length between first 204 and second 204 from the left corner of Fig. 13) between the first semiconductor fin (first 204 from the left corner of Fig. 13) and the second semiconductor fin (second 204 from the left corner of Fig. 13) is greater than a second distance (horizontal length between third 204 and fourth 204 from the left corner of Fig. 13) between the third semiconductor fin (third 204 from the left corner of Fig. 13) and the fourth semiconductor fin (fourth 204 from the left corner of Fig. 13); and
wherein a first variation (see Fig. 2A, wherein the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. See Fig. 3, wherein the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. See Fig. 4, wherein cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13, paragraph 0038, wherein “forming cut features with multiple layers of different materials”) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0) of a first distance (horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13) between respective inner sidewalls of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation (see Fig. 13, wherein the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) of a second distance (horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13) between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are each within a threshold.
Lin does not disclose a top surface of the first dielectric fin protrudes above a top surface of the shallow trench isolation region; and
a bottom surface of the first gate isolation structure contacts the top surface of the first dielectric fin.
Hsu discloses a top surface of the first dielectric fin (120 and 122 in Fig. 1E, paragraph 0028) protrudes above a top surface of the shallow trench isolation region 128 (Fig. 1E, paragraph 0029); and
a bottom surface of the first gate isolation structure (124 and first 148 from the right corner of Fig. 1E) contacts the top surface of the first dielectric fin (120 and 122 in Fig. 1E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form a top surface of the first dielectric fin protrudes above a top surface of the shallow trench isolation region; and a bottom surface of the first gate isolation structure contacts the top surface of the first dielectric fin, as taught by Hsu, since replacing a portion (Hsu, paragraph 0032) of the semiconductor fin with a dielectric material in a region where the gate structures are to be formed helps mitigate any potential structural defects introduced by the misalignment between the gate structures and the semiconductor fins.
Regarding claim 2, Lin further discloses the semiconductor device of claim 1, wherein the threshold (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13 is constant such that the first variation is 0; and the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) is less than about 20%.
Regarding claim 3, Lin further discloses the semiconductor device of claim 1, wherein a width of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13) is greater than a width of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13).
Regarding claim 4, Lin further discloses the semiconductor device of claim 1, wherein the first semiconductor fin (first 204 from the left corner of Fig. 13), the second semiconductor fin (second 204 from the left corner of Fig. 13), the third semiconductor fin (third 204 from the left corner of Fig. 13), and the fourth semiconductor fin (fourth 204 from the left corner of Fig. 13) each include a gate dielectric layer 1206 (Fig. 13, paragraph 0059).
Regarding claim 5, Lin further discloses the semiconductor device of claim 1, wherein the first gate isolation structure (see paragraph 0037, wherein “HfO, ZrO, AlO, LaO, BN, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and/or other suitable materials”) comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide.
Regarding claim 6, Lin further discloses the semiconductor device of claim 1, wherein a first active gate structure (1206, 1208, and 1210 in Fig. 13) over the first semiconductor fin (first 204 from the left corner of Fig. 13), wherein the first active gate structure (1206, 1208, and 1210 in Fig. 13) comprises a metal gate layer 1208 (Fig. 13, paragraph 0060, wherein “Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, and/or combinations thereof”) comprising at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
Regarding claim 7, Lin further discloses the semiconductor device of claim 1, wherein a first active gate structure (1206, 1208, and 1210 in Fig. 13) over the first semiconductor fin (first 204 from the left corner of Fig. 13), wherein the first active gate structure (1206, 1208, and 1210 in Fig. 13) comprises a metal gate layer 1208 (Fig. 13, paragraph 0060, wherein “Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi.sub.2, MoSi.sub.2, TaSi.sub.2, NiSi.sub.2, WN, other suitable p-type work function materials, and/or combinations thereof”) comprising at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, or NiSi2.
Regarding claim 22, Lin further discloses the semiconductor device of claim 1, wherein the first dielectric fin (lower layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13, paragraph 0038, wherein “forming cut features with multiple layers of different materials”) disposed between the first semiconductor fin (first 204 from the left corner of Fig. 13) and the second semiconductor fin (second 204 from the left corner of Fig. 13);
a first gate portion (1206, 1208, and 1210 vertically on first 204 from the left corner of Fig. 13) straddling the first semiconductor fin (first 204 from the left corner of Fig. 13) and comprising a first gate dielectric portion (1206 vertically on first 204 from the left corner of Fig. 13, paragraph 0070) and a first metal gate portion (1208 and 1210 vertically on first 204 from the left corner of Fig. 13, paragraph 0070) disposed over the first gate dielectric portion (1206 vertically on first 204 from the left corner of Fig. 13);
a second gate portion (1206, 1208, and 1210 vertically on second 204 from the left corner of Fig. 13) straddling the second semiconductor fin (second 204 from the left corner of Fig. 13), the second gate portion (1206, 1208, and 1210 vertically on second 204 from the left corner of Fig. 13) comprising a second gate dielectric portion (1206 vertically on second 204 from the left corner of Fig. 13, paragraph 0070) and a second metal gate portion (1208 and 1210 vertically on first 204 from the left corner of Fig. 13, paragraph 0070) disposed over the second gate dielectric portion (1206 vertically on second 204 from the left corner of Fig. 13;
wherein the first gate dielectric portion (1206 vertically on first 204 from the left corner of Fig. 13) is disposed between the first metal gate portion (1208 and 1210 vertically on first 204 from the left corner of Fig. 13) and a first inner sidewall (left sidewall of upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13) of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13, paragraph 0038), and wherein the second gate dielectric portion (1206 vertically on second 204 from the left corner of Fig. 13) is disposed between the second metal gate portion (1208 and 1210 vertically on first 204 from the left corner of Fig. 13) and a second inner sidewall (right sidewall of upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13) of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13) that is opposite to the first inner sidewall (left sidewall of upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13);
wherein the first gate dielectric portion (1206 vertically on first 204 from the left corner of Fig. 13) directly contacts and extends along the first inner sidewall (left sidewall of upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13), and is disposed between the first metal gate portion (1208 and 1210 vertically on first 204 from the left corner of Fig. 13) and the first inner sidewall (left sidewall of upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13); and
wherein the second gate dielectric portion (1206 vertically on second 204 from the left corner of Fig. 13) directly contacts and extends along the second inner sidewall (right sidewall of upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13) opposite to the first inner sidewall (left sidewall of upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13), and is disposed between the second metal gate portion (1208 and 1210 vertically on first 204 from the left corner of Fig. 13) and the second inner sidewall (right sidewall of upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13).
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2020/0098750) (hereafter Lin), in view of Hsu et al. (US 2020/0091311) (hereafter Hsu), in further view of Chang et al. (US 2019/0165155) (hereafter Chang).
Regarding claim 8, Lin discloses a semiconductor device, comprising:
a first semiconductor fin (first 204 from the right corner of Fig. 13, paragraph 0030) and a second semiconductor fin (second 204 from the right corner of Fig. 13, paragraph 0030) over a first area (right portion of 202 in Fig. 13) of a substrate 202 (Fig. 13, paragraph 0030); and
a third semiconductor fin (third 204 from the right corner of Fig. 13, paragraph 0030) and a fourth semiconductor fin (fourth 204 from the right corner of Fig. 13, paragraph 0030) over a second area (left portion of 202 in Fig. 13) of the substrate 202 (Fig. 13), wherein a first density of transistors formed in the first area (right portion of 202 in Fig. 13) is greater than (see Fig. 13, wherein a spacing between first 204 and second 204 is smaller than a spacing between third 204 and fourth 204 from the right corner of Fig. 13) a second density of transistors formed in the second area (left portion of 202 in Fig. 13);
a shallow trench isolation region 302 (Fig. 13, paragraph 0034) disposed in the substrate 202 (Fig. 13);
a first dielectric fin (lower layer of 402 formed between first 204 and second 204 from the right corner of Fig. 13, paragraph 0038, wherein “forming cut features with multiple layers of different materials”) disposed between the first semiconductor fin (first 204 from the right corner of Fig. 13) and the second semiconductor fin (second 204 from the right corner of Fig. 13), and wherein a bottom surface of the first dielectric fin (402 formed between first 204 and second 204 from the right corner of Fig. 13) is below the top surface of the shallow trench isolation region 302 (Fig. 13); and
a first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the right corner of Fig. 13, paragraph 0038, wherein “forming cut features with multiple layers of different materials”) that is disposed over the first dielectric fin (lower layer of 402 formed between first 204 and second 204 from the right corner of Fig. 13) between the first semiconductor fin (first 204 from the right corner of Fig. 13) and the second semiconductor fin (second 204 from the right corner of Fig. 13);
a second gate isolation structure (402 formed between third 204 and fourth 204 from the right corner of Fig. 13, paragraph 0037) filled with a dielectric material (see paragraph 0037) is formed between the third semiconductor fin (third 204 from the right corner of Fig. 13) and the fourth semiconductor fin (fourth 204 from the right corner of Fig. 13); and
wherein a first variation (see Fig. 2A, wherein the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. See Fig. 3, wherein the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. See Fig. 4, wherein cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the right corner of Fig. 13) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0) of a first distance (horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13) between respective inner sidewalls of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the right corner of Fig. 13) and a second variation (see Fig. 13, wherein the horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13 is constant such that the second variation is 0) of a second distance (horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13) between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the right corner of Fig. 13) are each within a threshold.
Lin does not disclose a top surface of the first dielectric fin protrudes above a top surface of the shallow trench isolation region; and
wherein a bottom surface of the first gate isolation structure contacts the top surface of the first dielectric fin.
Hsu discloses a top surface of the first dielectric fin (120 and 122 in Fig. 1E, paragraph 0028) protrudes above a top surface of the shallow trench isolation region 128 (Fig. 1E, paragraph 0029); and
wherein a bottom surface of the first gate isolation structure (124 and first 148 from the right corner of Fig. 1E) contacts the top surface of the first dielectric fin (120 and 122 in Fig. 1E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form a top surface of the first dielectric fin protrudes above a top surface of the shallow trench isolation region; and wherein a bottom surface of the first gate isolation structure contacts the top surface of the first dielectric fin, as taught by Hsu, since replacing a portion (Hsu, paragraph 0032) of the semiconductor fin with a dielectric material in a region where the gate structures are to be formed helps mitigate any potential structural defects introduced by the misalignment between the gate structures and the semiconductor fins.
Lin and Hsu do not disclose a bottom surface of the first dielectric fin is below the top surface of the shallow trench isolation region and contacts the substrate.
Chang discloses a bottom surface of the first dielectric fin 510 (Fig. 15B, paragraph 0056) is below the top surface of the shallow trench isolation region 120 (Fig. 15B, paragraph 0028) and contacts the substrate 110 (Fig. 15B, paragraph 0048).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Hsu to form a bottom surface of the first dielectric fin is below the top surface of the shallow trench isolation region and contacts the substrate, as taught by Chang, since the material composition (Chang, paragraph 0058) and the thicknesses of each of the layers in the multi-stack structure is configurable, the overall dielectric constant (k) value of the layer 510 (Chang, Fig. 15B, paragraph 0058) may be specifically configured optimize the functionality of the layer 510 (Chang, Fig. 15B, paragraph 0058), which is to provide electrical isolation between adjacent metal gate structures.
Regarding claim 9, Lin further discloses the semiconductor device of claim 8, wherein the threshold (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13 is constant such that the first variation is 0; and the horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13 is constant such that the second variation is 0) is less than about 20%.
Regarding claim 10, Lin further discloses the semiconductor device of claim 8, wherein the second distance (horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13) between the respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) is greater than the first distance (horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13) between the respective inner sidewalls of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the right corner of Fig. 13).
Regarding claim 11, Lin further discloses the semiconductor device of claim 8, wherein the first gate isolation structure (see paragraph 0037, wherein “HfO, ZrO, AlO, LaO, BN, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and/or other suitable materials”) comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide.
Regarding claim 12, Lin in view of Hsu and Chang discloses the semiconductor device of claim 8, however Lin does not disclose a width of the first gate isolation structure is greater than a width of the second gate isolation structure.
Hsu discloses a width (W4 in Fig. 1C, paragraph 0028, wherein “from about 30 nm to about 180 nm”) of the first gate isolation structure (124 and first 148 from the right corner of Fig. 1E) is greater than a width (W1 in Fig. 1C, paragraph 0028, wherein “from about 5 nm to about 15 nm”) of the second gate isolation structure (118B and third 148 from the right corner of Fig. 1E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form a width of the first gate isolation structure is greater than a width of the second gate isolation structure, as taught by Hsu, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 13-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hafez et al. (US 2020/0066897) (hereafter Hafez), in view of Hsu et al. (US 2020/0091311) (hereafter Hsu), in further view of Chang et al. (US 2019/0165155) (hereafter Chang), in another further view of Lin et al. (US 2020/0098750) (hereafter Lin).
Regarding claim 13, Hafez discloses a semiconductor device, comprising:
a first plurality of transistors (“low voltage device” (paragraph 0038) formed in 302 of Fig. 3A; and see “transistors” in paragraph 0015) over a substrate 306 (Fig. 3A, paragraph 0033), the first plurality of transistors comprising a first semiconductor fin (first 314 from the front of Fig. 3A, paragraph 0033) and a second semiconductor fin (second 314 from the front of Fig. 3A, paragraph 0033); and
a second plurality of transistors (“high voltage device” (paragraph 0033) with fins 314 formed in 304 of Fig. 3A; and see “transistors” in paragraph 0015) over the substrate 306 (Fig. 3A), the first plurality of transistors (“low voltage device” (paragraph 0038) formed in 302 of Fig. 3A) configured to operate under a lower gate voltage than the second plurality of transistors (“high voltage device” (paragraph 0033) with fins 314 formed in 304 of Fig. 3A).
Hafez does not disclose a shallow trench isolation region disposed in the substrate;
a first dielectric fin disposed between the first semiconductor fin and the second semiconductor fin, wherein a top surface of the first dielectric fin protrudes above a top surface of the shallow trench isolation region, and wherein a bottom surface of the first dielectric fin is below the top surface of the shallow trench isolation region and contacts the substrate;
the first plurality of transistors comprise a first transistor having a first active gate structure and a second transistor having a second active gate structure, the first and second active gate structures being separated from each other by a first gate isolation structure along a first direction, the first gate isolation structure being disposed over the first dielectric fin, wherein a bottom surface of the first gate isolation structure contacts the top surface of the first dielectric fin;
wherein the second plurality of transistors comprise a third transistor having a third active gate structure and a fourth transistor having a fourth active gate structure, the third and fourth active gate structures being separated from each other by a second gate isolation structure along the first direction.
Hsu discloses a shallow trench isolation region 128 (Fig. 1E, paragraph 0023) disposed in the substrate 102 (Fig. 1E, paragraph 0022);
a first dielectric fin (120 and 122 in Fig. 1E, paragraph 0028) disposed between the first semiconductor fin (first 106 from the right corner of Fig. 1E, paragraph 0031) and the second semiconductor fin (second 106 from the right corner of Fig. 1E, paragraph 0031), wherein a top surface of the first dielectric fin (120 and 122 in Fig. 1E) protrudes above a top surface of the shallow trench isolation region 128 (Fig. 1E), and wherein a bottom surface of the first dielectric fin (120 and 122 in Fig. 1E) is below the top surface of the shallow trench isolation region 128 (Fig. 1E);
the first plurality of transistors (“transistor (FinFET) device” (paragraph 0020) with first and second 106 from the right corner of Fig. 1E) comprise a first transistor (“transistor (FinFET) device” (paragraph 0020) with first 106 from the right corner of Fig. 1E) having a first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031) and a second transistor (“transistor (FinFET) device” (paragraph 0020) with second 106 from the right corner of Fig. 1E) having a second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the first (146B formed on the right hand side of 118D in Fig. 1E) and second active gate structures (146B formed between 118D and 118C in Fig. 1E) being separated from each other by a first gate isolation structure (first 148 from the right corner of Fig. 1E, paragraph 0028) along a first direction (horizontal direction in Fig. 1E), the first gate isolation structure (124 and first 148 from the right corner of Fig. 1E) being disposed over the first dielectric fin 118D (Fig. 1E), wherein a bottom surface of the first gate isolation structure (first 148 from the right corner of Fig. 1E) contacts the top surface of the first dielectric fin (120 and 122 in Fig. 1E);
wherein the second plurality of transistors (“transistor (FinFET) device” (paragraph 0020) with third and fourth 106 from the right corner of Fig. 1E) comprise a third transistor (“transistor (FinFET) device” (paragraph 0020) with third 106 from the right corner of Fig. 1E) having a third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031) and a fourth transistor (“transistor (FinFET) device” (paragraph 0020) with fourth 106 from the right corner of Fig. 1E) having a fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031), the third (146B formed between 118C and 118B in Fig. 1E) and fourth active gate structures (146B formed on the left hand side of 118B in Fig. 1E) being separated from each other by a second gate isolation structure (118B and third 148 from the right corner of Fig. 1E, paragraph 0028) along the first direction (horizontal direction in Fig. 1E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form a shallow trench isolation region disposed in the substrate; a first dielectric fin disposed between the first semiconductor fin and the second semiconductor fin, wherein a top surface of the first dielectric fin protrudes above a top surface of the shallow trench isolation region, and wherein a bottom surface of the first dielectric fin is below the top surface of the shallow trench isolation region and contacts the substrate; the first plurality of transistors comprise a first transistor having a first active gate structure and a second transistor having a second active gate structure, the first and second active gate structures being separated from each other by a first gate isolation structure along a first direction, the first gate isolation structure being disposed over the first dielectric fin, wherein a bottom surface of the first gate isolation structure contacts the top surface of the first dielectric fin; wherein the second plurality of transistors comprise a third transistor having a third active gate structure and a fourth transistor having a fourth active gate structure, the third and fourth active gate structures being separated from each other by a second gate isolation structure along the first direction, as taught by Hsu, since replacing a portion (Hsu, paragraph 0032) of the semiconductor fin with a dielectric material in a region where the gate structures are to be formed helps mitigate any potential structural defects introduced by the misalignment between the gate structures and the semiconductor fins.
Hafez and Hsu does not disclose a bottom surface of the first dielectric fin is below the top surface of the shallow trench isolation region and contacts the substrate.
Chang discloses a bottom surface of the first dielectric fin 510 (Fig. 15B, paragraph 0056) is below the top surface of the shallow trench isolation region 120 (Fig. 15B, paragraph 0028) and contacts the substrate 110 (Fig. 15B, paragraph 0048).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez in view of Hsu to form a bottom surface of the first dielectric fin is below the top surface of the shallow trench isolation region and contacts the substrate, as taught by Chang, since the material composition (Chang, paragraph 0058) and the thicknesses of each of the layers in the multi-stack structure is configurable, the overall dielectric constant (k) value of the layer 510 (Chang, Fig. 15B, paragraph 0058) may be specifically configured optimize the functionality of the layer 510 (Chang, Fig. 15B, paragraph 0058), which is to provide electrical isolation between adjacent metal gate structures.
Hafez, Hsu, and Chang do not disclose a first variation of a first distance between respective sidewalls of the first gate isolation structure along the first direction is about equal to a second variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction, wherein the first and second variations each range from about -20% to about 20%.
Lin discloses a first variation (see Fig. 2A, wherein the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. See Fig. 3, wherein the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. See Fig. 4, wherein cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13, paragraph 0038, wherein “forming cut features with multiple layers of different materials”) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0) of a first distance (horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13) between respective sidewalls of the first gate isolation structure (upper layer of 402 formed between first 204 and second 204 from the left corner of Fig. 13, paragraph 0038) along the first direction (horizontal direction in Fig. 13) is about equal to a second variation (see Fig. 13, wherein the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) of a second distance (horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13) between respective sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) along the first direction (horizontal direction in Fig. 13), wherein the first and second variations (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13 is constant such that the first variation is 0; and the horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13 is constant such that the second variation is 0) each range from about -20% to about 20%.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez in view of Hsu and Chang to form a first variation of a first distance between respective sidewalls of the first gate isolation structure along the first direction is about equal to a second variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction, wherein the first and second variations each range from about -20% to about 20%, as taught by Lin, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 14, Hafez in view of Hsu, Chang, and Lin discloses the semiconductor device of claim 13, however Hafez does not disclose the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN.
Hsu discloses the first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031), the second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031), and the fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031) each comprise (see paragraph 0064, wherein “Ru, Cu, W, Co, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Mo, WN, or any suitable materials”) at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN, as taught by Hsu, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 15, Hafez in view of Hsu, Chang, and Lin discloses the semiconductor device of claim 13, however Hafez does not disclose the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
Hsu discloses the first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031), the second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031), and the fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031) each comprise (see paragraph 0064, wherein “Ru, Cu, W, Co, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Mo, WN, or any suitable materials”) at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr, as taught by Hsu, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 17, Hafez in view of Hsu, Chang, and Lin discloses the semiconductor device of claim 13, however Hafez does not disclose the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a gate dielectric layer.
Hsu discloses the first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031), the second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031), and the fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031) each include (see paragraph 0063, wherein “the metal gate stacks 146 include a high-k gate dielectric layer and gate electrode”) a gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a gate dielectric layer, as taught by Hsu, since a gate dielectric layer can adjust threshold voltage.
Regarding claim 18, Hafez in view of Hsu, Chang, and Lin discloses the semiconductor device of claim 13, however Hafez does not disclose the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a metal gate layer.
Hsu discloses the first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031), the second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031), and the fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031) each include (see paragraph 0063, wherein “the metal gate stacks 146 include a high-k gate dielectric layer and gate electrode”) a metal gate layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a metal gate layer, as taught by Hsu, since a metal gate layer provides an electrostatic control of a channel.
Regarding claim 19, Hafez in view of Hsu, Chang, and Lin discloses the semiconductor device of claim 13, however Hafez does not disclose a width of the first gate isolation structure is greater than a width of the second gate isolation structure.
Hsu discloses a width of the first gate isolation structure (118D and first 148 from the right corner of Fig. 1E, paragraph 0028) is greater than a width of the second gate isolation structure (118B and third 148 from the right corner of Fig. 1E, paragraph 0028).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form a width of the first gate isolation structure is greater than a width of the second gate isolation structure, as taught by Hsu, since replacing a portion (Hsu, paragraph 0032) of the semiconductor fin with a dielectric material in a region where the gate structures are to be formed helps mitigate any potential structural defects introduced by the misalignment between the gate structures and the semiconductor fins.
Regarding claim 20, Hafez further discloses the semiconductor device of claim 13, wherein a first density of the first plurality of transistors (“low voltage device” (paragraph 0038) formed in 302 of Fig. 3A) is greater than (see Fig. 3A, wherein 302 is denser than 304) a second density of the second plurality of transistors (“high voltage device” (paragraph 0033) with fins 314 formed in 304 of Fig. 3A).
Response to Arguments
1. Applicant's arguments filed 9/14/2026 have been fully considered.
2. Applicant's arguments with respect to claims 1-15 and 17-21 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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