DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 3/20/2026 is acknowledged.
Applicant amended claims 5, 7, 10, and 11; and cancelled claim 16.
Applicant added claim 21.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 6 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 6, the limitations, "the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, and the fourth semiconductor fin each comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr” (Claim 6, Lines 1-3), it is unclear how each fin comprises at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. Paragraph 0036 filed on 8/9/2023 discloses “the active fins 402A-D may include silicon germanium (SixGe.sub.1-x, where x can be between 0 and 1), silicon carbide, pure or pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like”. These disclosed materials are semiconductor materials and do not include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr. In addition, paragraph 0089 filed on 8/9/2023 discloses “Example N-type work function metals that may be included in the gate structures for N-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof.” The materials, “Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr”, are N-type work function metals. It is unclear how a semiconductor fin can comprise N-type work function metals. Examiner is reading this limitation as “gate work function metals comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.”
In addition, regarding claim 7, the limitations, "the first semiconductor fin, the second semiconductor fin, the third semiconductor fin, and the fourth semiconductor fin each comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN” (Claim 7, Lines 1-3), it is unclear how each fin comprises at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN. Paragraph 0036 filed on 8/9/2023 discloses “the active fins 402A-D may include silicon germanium (SixGe.sub.1-x, where x can be between 0 and 1), silicon carbide, pure or pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like”. These disclosed materials are semiconductor materials and do not include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN. In addition, paragraph 0089 filed on 8/9/2023 discloses “Example P-type work function metals that may be included in the gate structures for P-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi.sub.2, MoSi.sub.2, TaSi.sub.2, NiSi.sub.2, WN, other suitable P-type work function materials, or combinations thereof.” The materials, “TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN”, are P-type work function metals. It is unclear how a semiconductor fin can comprise P-type work function metals. Examiner is reading this limitation as “gate work function metals comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2020/0098750) (hereafter Lin).
Regarding claim 1, Lin discloses a semiconductor device, comprising:
a first semiconductor fin (first 204 from the left corner of Fig. 13, paragraph 0030) and a second semiconductor fin (second 204 from the left corner of Fig. 13, paragraph 0030) over a first area (left portion of 202 in Fig. 13) of a substrate 202 (Fig. 13, paragraph 0030);
a third semiconductor fin (third 204 from the left corner of Fig. 13, paragraph 0030) and a fourth semiconductor fin (fourth 204 from the left corner of Fig. 13, paragraph 0030) over a second area (right portion of 202 in Fig. 13) of the substrate 202 (Fig. 13);
wherein a first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13, paragraph 0037) filled with a dielectric material (see paragraph 0037) is formed between the first semiconductor fin (first 204 from the left corner of Fig. 13) and the second semiconductor fin (second 204 from the left corner of Fig. 13), and a second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13, paragraph 0037) filled with the dielectric material (see paragraph 0037) is formed between the third semiconductor fin (third 204 from the left corner of Fig. 13) and the fourth semiconductor fin (fourth 204 from the left corner of Fig. 13);
wherein a first distance (horizontal length between first 204 and second 204 from the left corner of Fig. 13) between the first semiconductor fin (first 204 from the left corner of Fig. 13) and the second semiconductor fin (second 204 from the left corner of Fig. 13) is greater than a second distance (horizontal length between third 204 and fourth 204 from the left corner of Fig. 13) between the third semiconductor fin (third 204 from the left corner of Fig. 13) and the fourth semiconductor fin (fourth 204 from the left corner of Fig. 13); and
wherein a first variation (see Fig. 2A, wherein the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. See Fig. 3, wherein the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. See Fig. 4, wherein cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0) of a first distance (horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13) between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation (see Fig. 13, wherein the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) of a second distance (horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13) between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are each within a threshold.
Regarding claim 2, Lin further discloses the semiconductor device of claim 1, wherein the threshold (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13 is constant such that the first variation is 0; and the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) is less than about 20%.
Regarding claim 3, Lin further discloses the semiconductor device of claim 1, wherein a width of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) is greater than a width of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13).
Regarding claim 4, Lin further discloses the semiconductor device of claim 1, wherein the first semiconductor fin (first 204 from the left corner of Fig. 13), the second semiconductor fin (second 204 from the left corner of Fig. 13), the third semiconductor fin (third 204 from the left corner of Fig. 13), and the fourth semiconductor fin (fourth 204 from the left corner of Fig. 13) each include a gate dielectric layer 1206 (Fig. 13, paragraph 0059).
Regarding claim 5, Lin further discloses the semiconductor device of claim 1, wherein the first gate isolation structure (see paragraph 0037, wherein “HfO, ZrO, AlO, LaO, BN, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and/or other suitable materials”) comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide.
Regarding claim 6, Lin further discloses the semiconductor device of claim 1, wherein gate work function metals 1208 (Fig. 13, paragraph 0060, wherein “Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, and/or combinations thereof”) comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
Regarding claim 7, Lin further discloses the semiconductor device of claim 1, wherein gate work function metals 1208 (Fig. 13, paragraph 0060, wherein “Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi.sub.2, MoSi.sub.2, TaSi.sub.2, NiSi.sub.2, WN, other suitable p-type work function materials, and/or combinations thereof”) comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN.
Regarding claim 8, Lin discloses a semiconductor device, comprising:
a first semiconductor fin (first 204 from the right corner of Fig. 13, paragraph 0030) and a second semiconductor fin (second 204 from the right corner of Fig. 13, paragraph 0030) over a first area (right portion of 202 in Fig. 13) of a substrate 202 (Fig. 13, paragraph 0030); and
a third semiconductor fin (third 204 from the right corner of Fig. 13, paragraph 0030) and a fourth semiconductor fin (fourth 204 from the right corner of Fig. 13, paragraph 0030) over a second area (left portion of 202 in Fig. 13) of the substrate 202 (Fig. 13), wherein a first density of transistors formed in the first area (right portion of 202 in Fig. 13) is greater than (see Fig. 13, wherein a spacing between first 204 and second 204 is smaller than a spacing between third 204 and fourth 204 from the right corner of Fig. 13) a second density of transistors formed in the second area (left portion of 202 in Fig. 13);
wherein a first gate isolation structure (402 formed between first 204 and second 204 from the right corner of Fig. 13, paragraph 0037) filled with a dielectric material (see paragraph 0037) is formed between the first semiconductor fin (first 204 from the right corner of Fig. 13) and the second semiconductor fin (second 204 from the right corner of Fig. 13), and a second gate isolation structure (402 formed between third 204 and fourth 204 from the right corner of Fig. 13, paragraph 0037) filled with the dielectric material (see paragraph 0037) is formed between the third semiconductor fin (third 204 from the right corner of Fig. 13) and the fourth semiconductor fin (fourth 204 from the right corner of Fig. 13); and
wherein a first variation (see Fig. 2A, wherein the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. See Fig. 3, wherein the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. See Fig. 4, wherein cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0) of a first distance (horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13) between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the right corner of Fig. 13) and a second variation (see Fig. 13, wherein the horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13 is constant such that the second variation is 0) of a second distance (horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13) between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the right corner of Fig. 13) are each within a threshold.
Regarding claim 9, Lin further discloses the semiconductor device of claim 8, wherein the threshold (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13 is constant such that the first variation is 0; and the horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13 is constant such that the second variation is 0) is less than about 20%.
Regarding claim 10, Lin further discloses the semiconductor device of claim 8, wherein the second distance (horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13) between the respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) is greater than the first distance (horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13) between the respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13).
Regarding claim 11, Lin further discloses the semiconductor device of claim 8, wherein the first gate isolation structure (see paragraph 0037, wherein “HfO, ZrO, AlO, LaO, BN, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, and/or other suitable materials”) comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or silicon oxycarbide.
Regarding claim 12, Lin further discloses the semiconductor device of claim 8, wherein a width of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) is greater than a width of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 8 above, and further in view of Chi et al. (US 8674413 B1) (hereafter Chi).
Regarding claim 21, Lin discloses the semiconductor device of claim 8, however Lin does not disclose the first gate isolation structure is disposed over a first dummy fin between the first semiconductor fin and the second semiconductor fin;
the second gate isolation structure is disposed over a second dummy fin between the third semiconductor fin and the fourth semiconductor fin;
the first dummy fin comprises the dielectric material; and
the second dummy fin comprises the dielectric material.
Chi discloses the first gate isolation structure (first 52 from the left corner of Fig. 1M, Bridging paragraph from Col. 11 to col. 12) is disposed over a first dummy fin (first 40 from the left corner of Fig. 1M, first paragraph in Col. 11) between the first semiconductor fin (first 36 from the left corner of Fig. 1M) and the second semiconductor fin (second 36 from the left corner of Fig. 1M);
the second gate isolation structure (second 52 from the left corner of Fig. 1M, Bridging paragraph from Col. 11 to col. 12) is disposed over a second dummy fin (second 40 from the left corner of Fig. 1M, first paragraph in Col. 11) between the third semiconductor fin (fourth 36 from the left corner of Fig. 1M) and the fourth semiconductor fin (fifth 36 from the left corner of Fig. 1M);
the first dummy fin (first 40 from the left corner of Fig. 1M, first paragraph in Col. 11 wherein “silicon dioxide”) comprises the dielectric material; and
the second dummy fin (second 40 from the left corner of Fig. 1M, first paragraph in Col. 11 wherein “silicon dioxide”) comprises the dielectric material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form the first gate isolation structure is disposed over a first dummy fin between the first semiconductor fin and the second semiconductor fin; the second gate isolation structure is disposed over a second dummy fin between the third semiconductor fin and the fourth semiconductor fin; the first dummy fin comprises the dielectric material; and the second dummy fin comprises the dielectric material, as taught by Chi, since forming device isolations (Chi, Col. 13, Lines 21-23) that have an enhanced capability to electrically isolate adjacent devices.
Claims 13-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hafez et al. (US 2020/0066897) (hereafter Hafez), in view of Hsu et al. (US 2020/0091311) (hereafter Hsu), in further view of Lin et al. (US 2020/0098750) (hereafter Lin).
Regarding claim 13, Hafez discloses a semiconductor device, comprising:
a first plurality of transistors (“low voltage device” (paragraph 0038) formed in 302 of Fig. 3A; and see “transistors” in paragraph 0015); and
a second plurality of transistors (“high voltage device” (paragraph 0033) with fins 314 formed in 304 of Fig. 3A; and see “transistors” in paragraph 0015), the first plurality of transistors (“low voltage device” (paragraph 0038) formed in 302 of Fig. 3A) configured to operate under a lower gate voltage than the second plurality of transistors (“high voltage device” (paragraph 0033) with fins 314 formed in 304 of Fig. 3A).
Hafez does not disclose the first plurality of transistors comprise a first transistor having a first active gate structure and a second transistor having a second active gate structure, the first and second active gate structures being separated from each other by a first gate isolation structure along a first direction; and
wherein the second plurality of transistors comprise a third transistor having a third active gate structure and a fourth transistor having a fourth active gate structure, the third and fourth active gate structures being separated from each other by a second gate isolation structure along the first direction.
Hsu discloses the first plurality of transistors (“transistor (FinFET) device” (paragraph 0020) with first and second 106 from the right corner of Fig. 1E) comprise a first transistor (“transistor (FinFET) device” (paragraph 0020) with first 106 from the right corner of Fig. 1E) having a first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031) and a second transistor (“transistor (FinFET) device” (paragraph 0020) with second 106 from the right corner of Fig. 1E) having a second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the first (146B formed on the right hand side of 118D in Fig. 1E) and second active gate structures (146B formed between 118D and 118C in Fig. 1E) being separated from each other by a first gate isolation structure (118D and first 148 from the right corner of Fig. 1E, paragraph 0028) along a first direction (horizontal direction in Fig. 1E); and
wherein the second plurality of transistors (“transistor (FinFET) device” (paragraph 0020) with third and fourth 106 from the right corner of Fig. 1E) comprise a third transistor (“transistor (FinFET) device” (paragraph 0020) with third 106 from the right corner of Fig. 1E) having a third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031) and a fourth transistor (“transistor (FinFET) device” (paragraph 0020) with fourth 106 from the right corner of Fig. 1E) having a fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031), the third (146B formed between 118C and 118B in Fig. 1E) and fourth active gate structures (146B formed on the left hand side of 118B in Fig. 1E) being separated from each other by a second gate isolation structure (118B and third 148 from the right corner of Fig. 1E, paragraph 0028) along the first direction (horizontal direction in Fig. 1E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first plurality of transistors comprise a first transistor having a first active gate structure and a second transistor having a second active gate structure, the first and second active gate structures being separated from each other by a first gate isolation structure along a first direction; and wherein the second plurality of transistors comprise a third transistor having a third active gate structure and a fourth transistor having a fourth active gate structure, the third and fourth active gate structures being separated from each other by a second gate isolation structure along the first direction, as taught by Hsu, since replacing a portion (Hsu, paragraph 0032) of the semiconductor fin with a dielectric material in a region where the gate structures are to be formed helps mitigate any potential structural defects introduced by the misalignment between the gate structures and the semiconductor fins.
Hafez and Hsu does not disclose a first variation of a first distance between respective sidewalls of the first gate isolation structure along the first direction is about equal to a second variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction, wherein the first and second variations each range from about -20% to about 20%.
Lin discloses a first variation (see Fig. 2A, wherein the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. See Fig. 3, wherein the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. See Fig. 4, wherein cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0) of a first distance (horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13) between respective sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) along the first direction (horizontal direction in Fig. 13) is about equal to a second variation (see Fig. 13, wherein the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) of a second distance (horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13) between respective sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) along the first direction (horizontal direction in Fig. 13), wherein the first and second variations (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13 is constant such that the first variation is 0; and the horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13 is constant such that the second variation is 0) each range from about -20% to about 20%.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez in view of Hsu to form a first variation of a first distance between respective sidewalls of the first gate isolation structure along the first direction is about equal to a second variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction, wherein the first and second variations each range from about -20% to about 20%, as taught by Lin, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 14, Hafez in view of Hsu and Lin further discloses the semiconductor device of claim 13, however Hafez does not disclose the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN.
Hsu discloses the first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031), the second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031), and the fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031) each comprise (see paragraph 0064, wherein “Ru, Cu, W, Co, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Mo, WN, or any suitable materials”) at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, or WN, as taught by Hsu, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 15, Hafez in view of Hsu and Lin further discloses the semiconductor device of claim 13, however Hafez does not disclose the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
Hsu discloses the first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031), the second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031), and the fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031) each comprise (see paragraph 0064, wherein “Ru, Cu, W, Co, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Mo, WN, or any suitable materials”) at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each comprise at least one of Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, or Zr, as taught by Hsu, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 17, Hafez in view of Hsu and Lin further discloses the semiconductor device of claim 13, however Hafez does not disclose the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a gate dielectric layer.
Hsu discloses the first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031), the second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031), and the fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031) each include (see paragraph 0063, wherein “the metal gate stacks 146 include a high-k gate dielectric layer and gate electrode”) a gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a gate dielectric layer, as taught by Hsu, since a gate dielectric layer can adjust threshold voltage.
Regarding claim 18, Hafez in view of Hsu and Lin further discloses the semiconductor device of claim 13, however Hafez does not disclose the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a metal gate layer.
Hsu discloses the first active gate structure (146B formed on the right hand side of 118D in Fig. 1E, paragraph 0031), the second active gate structure (146B formed between 118D and 118C in Fig. 1E, paragraph 0031), the third active gate structure (146B formed between 118C and 118B in Fig. 1E, paragraph 0031), and the fourth active gate structure (146B formed on the left hand side of 118B in Fig. 1E, paragraph 0031) each include (see paragraph 0063, wherein “the metal gate stacks 146 include a high-k gate dielectric layer and gate electrode”) a metal gate layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form the first active gate structure, the second active gate structure, the third active gate structure, and the fourth active gate structure each include a metal gate layer, as taught by Hsu, since a metal gate layer provides an electrostatic control of a channel.
Regarding claim 19, Hafez in view of Hsu and Lin discloses the semiconductor device of claim 13, however Hafez does not disclose a width of the first gate isolation structure is greater than a width of the second gate isolation structure.
Hsu discloses a width of the first gate isolation structure (118D and first 148 from the right corner of Fig. 1E, paragraph 0028) is greater than a width of the second gate isolation structure (118B and third 148 from the right corner of Fig. 1E, paragraph 0028).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez to form a width of the first gate isolation structure is greater than a width of the second gate isolation structure, as taught by Hsu, since replacing a portion (Hsu, paragraph 0032) of the semiconductor fin with a dielectric material in a region where the gate structures are to be formed helps mitigate any potential structural defects introduced by the misalignment between the gate structures and the semiconductor fins.
Regarding claim 20, Lin further discloses the semiconductor device of claim 13, wherein a first density of the first plurality of transistors (“low voltage device” (paragraph 0038) formed in 302 of Fig. 3A) is greater than (see Fig. 3A, wherein 302 is denser than 304) a second density of the second plurality of transistors (“high voltage device” (paragraph 0033) with fins 314 formed in 304 of Fig. 3A).
Response to Arguments
1. Applicant's arguments filed 3/20/2026 have been fully considered.
2. The applicant argues (REMARKS, first paragraph in page 8) that “The Office's argument appears to be that because FIG. 13 of Lin shows a constant horizontal width of feature 402 at one cross-section, the "variation" is 0, and 0 is "within a threshold," so the claim element is met. However, the problem with this argument is that Lin never teaches any threshold-bounded variation of the distance between inner sidewalls of an isolation structure. Lin does not discuss any variation of the sidewall-to-sidewall distance of cut feature 402 along its length, does not state that such variation is constrained within any threshold, and does not compare such variation between two different areas of the substrate. The Office's allegation that the variation is zero is inferred solely from a schematic that is explicitly noted as not being drawn to scale (Lin [0005]), and there is neither an express nor inherent disclosure of a "variation ... within a threshold".” In addition, the applicant argues (REMARKS, first paragraph in page 10) that “Thus, Lin's methods will produce the very type of non-uniform trench that the device and method of claim 1 are specifically designed to avoid. Lin does not disclose that "a first variation of a first distance... [and] a second variation of a second distance... are each within a threshold" as recited in claim 1 of the present Application (e.g., Lin does not state that the variation in sidewall-to-sidewall distance is within 20%).” However, Lin et al. (US 2020/0098750) (hereafter Lin) disclose the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. In addition, Lin discloses the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. Furthermore, Lin discloses cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0. And Lin discloses a first variation (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13 is constant such that the first variation is 0) of a first distance (horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13) between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation (see Fig. 13, wherein the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) of a second distance (horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13) between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are each within a threshold.
3. The applicant argues (REMARKS, third paragraph in page 10) that “Claim 2 recites in part that "the threshold is less than about 20%." The Office alleges that "the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0... is less than about 20%." Office Action at page 5. However, Lin does not disclose that the sidewall-to-sidewall distance of cut feature 402 is within the +20%-type threshold described in Applicant's specification. Instead, Lin merely depicts an idealized cross-section where the illustrated width of feature 402 appears constant, without providing any teaching about acceptable variation or tolerance limits. Lin explicitly states that "various features are not drawn to scale" (Lin [0005]), and it nowhere identifies any numerical or percentage-based threshold for how much the distance between the inner sidewalls of feature 402 may vary along its length. The Office's assertion that the variation is "0%" and therefore "less than about 20%" is thus an inference based solely on a non-to-scale schematic.” However, Lin discloses the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. In addition, Lin discloses the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. Furthermore, Lin discloses cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0. And Lin discloses the threshold (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13 is constant such that the first variation is 0; and the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) is less than about 20%.
4. The applicant argues (REMARKS, third paragraph in page 11) that “The Office combines Hafez and Hsu for the general device structure and relies on Lin as disclosing "wherein a first variation of a first distance between respective sidewalls of the first gate isolation structure along the first direction is about equal to a second variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction, wherein the first and second variations each range from about -20% to about 20%." Even in combination, however, Hafez, Hsu, and Lin do not teach or suggest this claim element.” However, Lin discloses the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. In addition, Lin discloses the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. Furthermore, Lin discloses cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0.
5. The applicant argues (REMARKS, first paragraph in page 12) that “Furthermore, the Office's reliance on In re Wertheim and In re Woodruff is misplaced because Lin does not disclose any range for the variation at all. Lin neither teaches nor suggests any tolerance band or range of acceptable variation. By contrast, the present claims recite that "the first and second variations each range from about -20% to about 20%" and further require that the first and second variations be about equal. Accordingly, this is not an "overlapping range" situation and the cited case law on overlapping or encompassing ranges does not support a prima facie case of obviousness here.” However, Lin discloses a first variation (see Fig. 2A, wherein the fins 204 (Fig. 2A, paragraph 0031) may be patterned using one or more photolithography processes such that the fins 204 (Figs. 2A and 13) have vertical sidewalls. See Fig. 3, wherein the first dielectric layer 302 (Fig. 3, paragraph 0035) is deposited using Atomic Layer Deposition (ALD) such that the first dielectric layer 302 (Figs. 3 and 13) have vertical sidewalls. See Fig. 4, wherein cut features 402 (Fig. 4, paragraph 0036) are formed between the fins 204 (Fig. 4, paragraph 0036) in the trenches 304 (Fig. 3, paragraph 0036) in the first dielectric layer 302 (Fig. 4, paragraph 0036) such that the cut features 402 (Figs. 4 and 13) have vertical sidewalls. Therefore, a first variation of a first distance between respective inner sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) and a second variation of a second distance between respective inner sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) are 0) of a first distance (horizontal length of 402 formed between first 204 and second 204 from the left corner of Fig. 13) between respective sidewalls of the first gate isolation structure (402 formed between first 204 and second 204 from the left corner of Fig. 13) along the first direction (horizontal direction in Fig. 13) is about equal to a second variation (see Fig. 13, wherein the horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13 is constant such that the second variation is 0) of a second distance (horizontal length of 402 formed between third 204 and fourth 204 from the left corner of Fig. 13) between respective sidewalls of the second gate isolation structure (402 formed between third 204 and fourth 204 from the left corner of Fig. 13) along the first direction (horizontal direction in Fig. 13), wherein the first and second variations (see Fig. 13, wherein the horizontal length of 402 formed between first 204 and second 204 from the right corner of Fig. 13 is constant such that the first variation is 0; and the horizontal length of 402 formed between third 204 and fourth 204 from the right corner of Fig. 13 is constant such that the second variation is 0) each range from about -20% to about 20%. Lin discloses the first variation and the second variation are 0, wherein the first variation and the second variation lie inside ranges from about -20% to about 20%.
6. The applicant argues (REMARKS, second paragraph in page 12) that “Lin neither recognizes this density-induced non-uniformity problem nor discloses any variation range or requirement that variations in different regions be matched. Thus, even in the context of the information provided by Lin or the other cited references, there would not be any motivation to select and apply a ±20% variation threshold.” However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Hafez in view of Hsu to form a first variation of a first distance between respective sidewalls of the first gate isolation structure along the first direction is about equal to a second variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction, wherein the first and second variations each range from about -20% to about 20%, as taught by Lin, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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