Prosecution Insights
Last updated: August 17, 2026
Application No. 18/447,149

SILICON-GERMANIUM FINS AND METHODS OF PROCESSING THE SAME IN FIELD-EFFECT TRANSISTORS

Non-Final OA §102§103
Filed
Aug 09, 2023
Priority
Feb 19, 2020 — provisional 62/978,508 +1 more
Examiner
WILCZEWSKI, MARY A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 835 resolved
+16.9% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
39 currently pending
Career history
870
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
44.2%
+4.2% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 835 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office action is in response to the filing of this application on 09 August 2023. Claims 1-20 are pending in the application. Claims 1, 9, and 15 are independent. This application is a divisional of application Serial No. 17/126,594, filed 18 December 2020, now US Patent 12,136,651, which claims benefit to provisional application Serial No. 62/978,508, filed on 19 February 2020. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 4, 6, 7, and 8 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Tsai et al., US 2020/0006084, cited by Applicant on the Information Disclosure Statement (IDS) submitted on 31 October 2023.. With respect to claim 1, Tsai et al. disclose a method, shown in Figs. 5-14, comprising: providing a silicon-containing fin structure 250-251 and 254-255 and a germanium-containing fin 252-253 structure on a substrate 210, see Fig. 5 and paragraph [0029]; trimming, via a first process, the silicon-containing fin structure 250-251 and 254-255, see Fig. 6 and paragraph [0030]; trimming, via a second process, the germanium-containing fin structure 252-253, see Fig. 6 and paragraph [0030]; forming a silicon-containing layer 500 directly on the trimmed silicon-containing fin structure and the trimmed germanium-containing fin structure, see Figs. 8 and 9 and paragraphs [0041]; forming an interfacial layer 600 directly on the silicon-containing layer 500, see Figs. 12 and 13 and paragraph [0055]; forming a gate dielectric layer 700 directly on the interfacial layer 600, see Fig. 14 and paragraph [0057]: “Referring now to FIG. 14, a plurality of gate structures, such as gate structures 700 and 701, may be formed over the fin structures 250-255. For example, the gate structures 700-701 may each include a high-k gate dielectric and a metal gate electrode.”; and forming a gate electrode layer 700 on the gate dielectric layer, see Fig. 14 and paragraph [0057]. With respect to claim 2, in the method of Tsai et al., the silicon-containing fin structure 250-251 and 254-255 has a different material composition (fin structures 250-251 and 254-255 are fin structures for NFETs and include silicon (Si)) than the germanium-containing fin structure 252-253 ( fin structures 252-253 are fin structures for PFETs and include silicon germanium (SiGe), see paragraph [0029]. With respect to claim 4, the method of Tsai et al. further comprises: recessing a portion of the trimmed silicon-containing fin structure and a portion of the trimmed germanium-containing fin structure, as shown in Fig. 5, (see paragraph [0029]); forming a first source/drain feature (an oxide layer) on the portion of the recessed trimmed silicon-containing fin structure, see paragraph [0037]; and forming a second source/drain feature (an oxide layer) on the portion of the recessed trimmed germanium-containing fin structure, see paragraph [0037]. With respect to claim 6, the method of Tsai et al. further comprises: forming a dielectric isolation structure 270 on the substrate 210 between the silicon-containing fin structure 250-251 and 254-255 and the germanium-containing fin structure 252-253; and forming a liner layer 280 directly on the silicon-containing fin structure 250-251 and 254-255, the dielectric isolation structure 270 and the germanium-containing fin structure 252-253 such that the liner layer 280 extends continuously from the silicon-containing fin structure 250-251 and 254-255 to the germanium-containing fin structure 252-253, see Figs. 2-5 and paragraphs [0031]-[0035]. With respect to claim 7, in the method of Tsai et al., the liner layer 280 interfaces with the silicon-containing layer 500 disposed directly on the trimmed silicon-containing fin structure 250-251 and 254-255 and the trimmed germanium-containing fin structure 252-253, as shown in Fig. 9. With respect to claim 8, in the method of Tsai et al., wherein an upper portion of the trimmed silicon-containing fin structure 250-251 and 254-255 has a first width and an upper portion of the trimmed germanium-containing fin structure 252-253 has a second width that is different than the first width, since the surfaces of the fin structures exhibit a significant amount of topography variation, such as protrusions and dips, see Fig. 7 and paragraphs [0037]=[0040]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al., US 2020/0006084, as applied to claim 1 above, further in view of Fan et al., US 2019/0165139, also cited by Applicant on the Information Disclosure Statement (IDS) submitted on 31 October 2023.. With respect to claim 4, the method of Tsai et al. further comprises: recessing a portion of the trimmed silicon-containing fin structure and a portion of the trimmed germanium-containing fin structure, as shown in Fig. 5, (see paragraph [0029]). Tsai et al. also teach that fin structures 250-251 and 254-255 are fin structures for NFETs and include an n-type material, for example arsenic (As) or phosphorous (P), and that fin structures 252-253 are fin structures for PFETs and include a p-type material, for example, boron (B), see paragraphs [0028] and [0029]. However, Tsai et al. fail to teach forming a first source/drain feature on the portion of the recessed trimmed silicon-containing fin structure, and forming a second source/drain feature on the portion of the recessed trimmed germanium-containing fin structure, wherein the first source/drain feature includes a first dopant having a first type of conductivity and the second source/drain feature includes a second dopant having a second type of conductivity that is opposite the first type of conductivity. In the same field of endeavor, Fan et al. teach after trimming fin structures, a source/drain feature can grown on the trimmed fin structures and that the source/drain features can be in-situ doped during the epitaxial growth process, see paragraphs [0031]-[0032]. In light of the teachings of Tsai et al. and Fan et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a first source/drain feature on the portion of the recessed trimmed silicon-containing fin structure, and to form a second source/drain feature on the portion of the recessed trimmed germanium-containing fin structure, wherein the first source/drain feature includes a first dopant having a first type of conductivity and the second source/drain feature includes a second dopant having a second type of conductivity that is opposite the first type of conductivity. Claims 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al., US 2020/0006084, in view of Fan et al., US 2019/0165139, both cited by Applicant on the Information Disclosure Statement (IDS) submitted on 31 October 2023.. With respect to claim 15, Tsai et al. disclose a method, shown in Figs. 5-14, comprising: forming a semiconductor substrate 210 having a first region (region of substrate 210 where fins 252 and 253 are located) and a second region (region of substrate 210 where fins 250 and 251 are located), see Fig. 5; forming a first fin 253 protruding from the first region and a second fin 251 protruding from the second region, wherein the first fin 253 includes silicon-germanium (SiGe) and the second fin 251 includes silicon (Si) but is free of germanium (Ge), see Fig. 5 and paragraph [0029]; determining a thickness of a Si-containing layer 500 (see paragraph [0041]) to be deposited over the first fin 253, see paragraph [0044]; trimming the first fin 253 based on the thickness of the Si-containing layer, wherein trimming the first fin 253 forms a fin shoulder that protrudes from a sidewall of the trimmed first fin 253, see Figs. 6 and 7 and paragraphs [0036]-[0040]; depositing the Si-containing layer 500 to the determined thickness over the trimmed first fin 253, see Figs. 8 and 9 and paragraphs [0041]-[0044], wherein a portion of the Si-containing layer 500 laterally extends beyond the fin shoulder, as shown in Figs. 8 and 9; forming a dummy gate stack 700/701 (see paragraph [0059]: “the formation of the gate structures 700-701 may include a gate replacement process. In the gate replacement process, a dummy gate electrode (e.g., containing polysilicon) is formed initially and is then replaced later by the metal gate electrode. In some embodiments of the gate replacement process, a dummy gate dielectric (e.g., containing silicon oxide) may also be formed initially then then replaced later by the high-k gate dielectric.”) over a portion of the Si-containing layer 251, see Fig. 14; and replacing the dummy gate stack 700/701 with a metal gate stack, see paragraph [0059]. Tsai et al. fail to teach forming source/drain features adjacent to the dummy gate stack 700/701in the first fin 253 and the second fin 251. In the same field of endeavor, Fan et al. teach after trimming fin structures, a source/drain feature can be epitaxially grown on the trimmed fin structures and that the source/drain features can be in-situ doped during the epitaxial growth process, see paragraphs [0031]-[0032]. In light of the teachings of Tsai et al. and Fan et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form source/drain features adjacent to the dummy gate stack 700/701in the first fin 253 and the second fin 251, since the portion of the dielectric layer 600 located over/above the fin structures 250-255 are removed during the dummy gate etch process, and thus no portions of the dielectric layer 600 are shown above the fin structures in FIG. 14. With respect to claim 18, in the method of Tsai et al., the thickness of the Si-containing layer 500 is a first thickness, and wherein depositing (see Fig. 8) the Si-containing layer 500 forms the Si-containing layer 500 to a second thickness over the second fin 251 (see paragraph [0043]), and wherein the second thickness is less than the first thickness, since a subsequent oxidation step will consume some of the silicon-containing layer 500, see paragraphs [0041] and [0044]. Allowable Subject Matter Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record is Tsai et al., US 2020/0006084. Tsai et al. lack anticipation of the trimmed silicon-containing fin structure includes a first upper portion and a first lower portion, wherein the first upper portion has a first edge and an opposing second edge and the first lower portion has a third edge and an opposing fourth edge, wherein the trimmed silicon-containing fin structure further includes a first transition edge tapering away from the first edge to the third edge, the first edge and the third edge being on the same side of the trimmed silicon-containing fin structure, wherein the trimmed silicon-containing fin structure further includes a second transition edge tapering away from the second edge to the fourth edge, the second edge and the fourth edge being on the same side of the trimmed silicon-containing fin structure, and wherein the first transition edge extends to a greater height above the substrate than the second transition edge, and wherein the trimmed germanium-containing fin structure includes a second upper portion and a second lower portion, wherein the second upper portion has a fifth edge and an opposing sixth edge and the second lower portion has a seventh edge and an opposing eighth edge, wherein the trimmed germanium-containing fin structure further includes a third transition edge tapering away from the fifth edge to the seventh edge, the fifth edge and the seventh edge being on the same side of the trimmed germanium-containing fin structure, wherein the trimmed germanium-containing fin structure further includes a fourth transition edge tapering away from the sixth edge to the eighth edge, the sixth edge and the eighth edge being on the same side of the trimmed germanium-containing fin structure, and wherein the third transition edge extends to a greater height above the substrate than the fourth transition edge, as required in dependent claim 3. Claims 9-14 are allowable over the prior art of record. The following is a statement of reasons for the indication of allowable subject matter: Although the prior art teaches trimming fin structures, the prior art fails to teach or suggest a method comprising modifying the germanium-containing fin structure such that the modified trimmed germanium-containing fin structure includes: an upper portion having a first edge and an opposing second edge; a lower portion having a third edge and an opposing fourth edge; a first transition edge tapering away from the first edge to the third edge, the first edge and the third edge being on the same side of the modified germanium-containing fin structure; and a second transition edge tapering away from the second edge to the fourth edge, the second edge and the fourth edge being on the same side of the modified germanium-containing fin structure, and wherein the second transition edge extends to a greater height above the substrate than the first transition edge, as required in independent claim 9. Claims 10-14 are allowable by virtue of their dependency from independent claim 9. Claims 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record is Tsai et al., US 2020/0006084. Tsai et al. lack anticipation of before depositing the Si-containing layer 500: measuring a first width of the first fin; determining a first dimension based on the first width and the thickness of the Si-containing layer; comparing the first dimension with a first target dimension of the first fin; and trimming the first fin based on result of the comparing, wherein trimming the first fin is configured to remove portions of the first fin without substantially removing portions of the second fin. Claim 17 is objected to by virtue of its dependence on claim 16. Claims 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The closest prior art of record is Tsai et al., US 2020/0006084. Tsai et al. lack anticipation of before depositing the Si-containing layer: measuring a second width of the second fin; determining a second dimension based on the second width and the second thickness of the Si-containing layer; comparing the second dimension with a second target dimension of the second fin; and trimming the second fin based on result of the comparing, wherein trimming the second fin is configured to remove portions of the second fin without substantially removing portions of the first fin. Claim 20 is objected to by virtue of its dependence on claim 19. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose the trimming or modifying of fin structures. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARY A. WILCZEWSKI Primary Examiner Art Unit 2898 /MARY A WILCZEWSKI/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

Aug 09, 2023
Application Filed
Jul 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.1%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 835 resolved cases by this examiner. Grant probability derived from career allowance rate.

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