DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendments filed 12/29/2025 have been entered. Claims 1-2, 5-9, 11, and 14-25 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-9, 11-12, 14-17, 19-20, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al (US 20200119019 A1) hereinafter “Tsai” in view of Kim et al (US 20150187763 A1) hereinafter “Kim,” Chang et al (US 20120080760 A1) hereinafter “Chang,” Huang et al. (US 20190131185 A1) hereinafter “Huang”, and Ahn et al. (US 20140138795 A1) hereinafter “Ahn.”
Regarding Claim 1, Figure 27 of Tsai teaches: a semiconductor device (Paragraph 0015), comprising: a first transistor (Paragraph 0019) comprising a first gate stack (combination of 100, 102B/102, 116, and 120) in a first region (58C) of a silicon substrate (50), the first transistor comprising: a first gate dielectric layer (102B) on the silicon substrate, the first gate dielectric layer having a first thickness (Examiner notes the presence of the layer implies the layer has some thickness.), a first dipole layer residue (138; Figure 28; Paragraph 0065) on the first gate dielectric layer; a second dielectric layer (116; Paragraph 0053, where 116 is made of the same material as 112, TaN) on the first dipole layer; and a gate electrode layer (120) wherein the first transistor is characterized by a first threshold voltage (Paragraph 0065). [Examiner’s note: The material of layer 112, TaN, can be used as a gate dielectric layer, as evidenced by Huang Paragraph 0033.]
Further, the process limitation “the first dipole layer residue remaining following an annealing process on a first dipole layer” found in product Claim 1, invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of Claim 1, does not require that the first dipole layer residue is formed following an annealing process on a first dipole layer, but simply that the first dipole layer residue is capable of being formed by an annealing process. However, Tsai does teach an annealing process performed on a dipole layer (Paragraph 0066). Therefore, the process limitation does not structurally distinguish the claimed invention over the prior art.
Tsai does not teach: the first threshold voltage is determined by a distance between dipole inducing elements in the first dipole layer on the first dielectric layer and a surface of the semiconductor substrate.
Figure 3 of Kim teaches: transistors (TR5-8) on a substrate (100) with a first gate dielectric layer (152) has a thickness of T2 and a third gate dielectric layer (151) has a thickness of T1, wherein the thickness of the first dielectric layer is thinner than the third dielectric layer (Paragraph 0093.)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first threshold voltage be determined by a distance between dipole inducing elements in the first dipole layer on the first dielectric layer and a surface of the semiconductor substrate because Kim teaches that modifying the thickness of the dielectric layer varies the threshold voltage (Kim Paragraph 0093). As the dielectric layer of Tsai is between the dipole inducing layer and the substrate, the distance between the dipole inducing elements in the first dipole inducing layer and a surface of the semiconductor substrate will be directly impacted by the thickness of the dielectric layer. Therefore, the threshold voltage will be determined by tuning the thickness of the dielectric layer.
Tsai does not teach: a conductive work function layer on the second dielectric layer Figures 2D1-2D3 of Huang teach: a conductive work function layer (244) is formed over a gate dielectric layer (242/243)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a conductive work function layer on the second dielectric layer because the conductive work function layer tunes the work function of the device (Huang Paragraph 0034).
Tsai does not teach: the first gate dielectric layer comprising praseodymium oxide
Figure 3 of Chang teaches: a transistor (2), on a substrate (20) containing a gate dielectric layer (22) comprising praseodymium oxide (Paragraph 0038).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric layer of Tsai to include praseodymium oxide because praseodymium oxide has a high dielectric constant and high bandgap that effectively decreases the leakage current and the equivalent oxide thickness (EOT) of the device (Chang Paragraph 0052) .and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Tsai does not teach: the first gate dielectric layer comprising praseodymium oxide being substantially amorphous
Figure 1 of Anh teaches: a semiconductor device (110), with a praseodymium oxide dielectric layer (114) that is substantially amorphous
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first gate dielectric layer comprising praseodymium oxide being substantially amorphous because Anh teaches amorphous dielectric materials provide lower leakage currents due to the lack of defects along grain boundaries (Ahn Paragraph 0031).
Regarding Claim 2, the combination of Tsai, Kim, Chang, Huang, and Ahn teaches all of the limitations of the claimed invention as stated above.
Tsai does not teach: the second gate dielectric layer comprises praseodymium oxide.
Figure 3 of Chang teaches: a transistor (2), on a substrate (20) containing a gate dielectric layer (22) comprising praseodymium oxide (Paragraph 0038).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second gate dielectric layer comprise praseodymium oxide because praseodymium oxide has a high dielectric constant and high bandgap that effectively decreases the leakage current and the equivalent oxide thickness (EOT) of the device (Chang Paragraph 0052) .and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding Claim 5, Figures 1-28 of Tsai teaches: a second transistor (Paragraph 0019) comprising a second gate stack (combination of 100, 102A/102, 116, and 120) in a second region (58B) of the silicon substrate (50), the second transistor comprising: a third gate dielectric layer (102A/102) on the silicon substrate, the third dielectric layer having a second thickness (Examiner notes the presence of the layer implies the layer has some thickness.), the third dielectric layer including dipole inducing elements (Paragraph 0050); a fourth gate dielectric layer (116; Paragraph 0053, where 116 is made of the same material as 112, TaN) on the third dielectric layer; the gate electrode layer (120); and wherein the second transistor is characterized by a second threshold voltage determined by dipole inducing elements in the third dielectric layer (Paragraph 0014). [Examiner’s note: The material of layer 112, TaN, can be used as a gate dielectric layer, as evidenced by Huang Paragraph 0033.]
Tsai does not teach: wherein a thickness of the first dielectric layer is less than a thickness of the third dielectric layer
Figure 3 of Kim teaches: transistors (TR5-8) on a substrate (100) with a first gate dielectric layer (152) has a thickness of T2 and a third gate dielectric layer (151) has a thickness of T1, wherein the thickness of the first dielectric layer is thinner than the third dielectric layer (Paragraph 0093.)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first thickness be less than the second thickness because by changing the thicknesses of the dielectric layers the threshold voltages of the transistors will be different (Kim Paragraph 0093). Therefore, it would be desirable to tune the thickness of the dielectric layer to produce a desired threshold voltage.
Tsai does not teach: the conductive work function layer on the fourth dielectric layer
Figures 2D1-2D3 of Huang teach: a conductive work function layer (244) is formed over a gate dielectric layer (242/243)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a conductive work function layer on the second dielectric layer because the conductive work function layer tunes the work function of the device (Huang Paragraph 0034).
Tsai does not teach: the third gate dielectric layer comprising praseodymium oxide
Figure 3 of Chang teaches: a transistor (2), on a substrate (20) containing a gate dielectric layer (22) comprising praseodymium oxide (Paragraph 0038).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric layer of Tsai to include praseodymium oxide because praseodymium oxide has a high dielectric constant and high bandgap that effectively decreases the leakage current and the equivalent oxide thickness (EOT) of the device (Chang Paragraph 0052) .and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding Claim 6, the combination of Tsai, Kim, Chang, Huang, and Ahn teach all of the limitations of the claimed limitation as stated above.
Tsai does not teach: the first transistor is characterized by a first EOT and the second transistor is characterized by a second EOT, and the first EOT is less than or equal to the second EOT.
The combination of Tsai and Kim teaches the first dielectric of Tsai is thinner than the third dielectric of Tsai, because Kim teaches that by tuning the thickness of the dielectric layer, the threshold voltage of a transistor can be controlled. The threshold voltage of a transistor is directly proportional to oxide thickness, therefore the thinner the oxide thickness, the lower the threshold voltage. Therefore, the combination of Tsai and Kim teaches a transistor with a thinner dielectric layer, will have a lower threshold voltage, and a lower equivalent oxide thickness (EOT).
Regarding Claim 7, Figures 1-28 of Tsai teach: the dipole inducing elements in the third gate dielectric layer (102A) are derived from a second dipole layer (104), which is deposited on the third gate dielectric layer and subsequently removed (Paragraph 0053) following the annealing process (Paragraph 0050) to drive the dipole inducing elements into the third gate dielectric layer.
Regarding Claim 8, A semiconductor device (Paragraph 0015), comprising: a transistor (Paragraph 0019) comprising a gate stack (combination of 100, 102B, 116, and 120) on a silicon substrate (50) by at least: a first dielectric layer (102B) on the silicon substrate, a dipole layer residue (138) on the first dielectric layer; a second dielectric layer (116) on the dipole layer residue; and a gate electrode layer (120).
Further, the process limitation “the dipole layer residue remaining following an annealing process on a dipole layer” found in product Claim 8, invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of Claim 8, does not require that the dipole layer residue is formed following an annealing process on a dipole layer, but simply that the dipole layer residue is capable of being formed by an annealing process on a dipole layer. However, Tsai does teach an annealing process performed on a dipole layer (Paragraph 0066). Therefore, the process limitation does not structurally distinguish the claimed invention over the prior art.
Tsai does not teach: a distance between dipole inducing elements in the dipole layer and a surface of the silicon substrate is varied by tuning a thickness of the first gate dielectric layer to adjust a threshold voltage of the transistor.
Figure 3 of Kim teaches: transistors (TR5-8) on a substrate (100) with a first gate dielectric layer (152) has a thickness of T2 and a third gate dielectric layer (151) has a thickness of T1, wherein the thickness of the first dielectric layer adjusts the threshold voltage of the transistor (Paragraph 0093.)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a distance between dipole inducing elements in the dipole layer and a surface of the silicon substrate be varied by tuning a thickness of the first gate dielectric layer to adjust a threshold voltage of the transistor because Kim teaches that modifying the thickness of the dielectric layer varies the threshold voltage (Kim Paragraph 0093). As the dielectric layer of Tsai is between the dipole inducing layer and the substrate, the distance between the dipole inducing elements in the first dipole inducing layer and a surface of the semiconductor substrate will be directly impacted by the thickness of the dielectric layer. Therefore, the threshold voltage will be determined by tuning the thickness of the dielectric layer.
Tsai does not teach: a conductive work function layer on the second dielectric layer
Figures 2D1-2D3 of Huang teach: a conductive work function layer (244) is formed over a gate dielectric layer (242/243)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a conductive work function layer on the second dielectric layer because the conductive work function layer tunes the work function of the device (Huang Paragraph 0034).
Tsai does not teach: the first gate dielectric layer comprising praseodymium oxide
Figure 3 of Chang teaches: a transistor (2), on a substrate (20) containing a gate dielectric layer (22) comprising praseodymium oxide (Paragraph 0038).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric layer of Tsai to include praseodymium oxide because praseodymium oxide has a high dielectric constant and high bandgap that effectively decreases the leakage current and the equivalent oxide thickness (EOT) of the device (Chang Paragraph 0052) .and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Tsai does not teach: the first gate dielectric layer comprising praseodymium oxide is substantially amorphous
Figure 1 of Anh teaches: a semiconductor device (110), with a praseodymium oxide dielectric layer (114) that is substantially amorphous
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first gate dielectric layer comprising praseodymium oxide being substantially amorphous because Anh teaches amorphous dielectric materials provide lower leakage currents due to the lack of defects along grain boundaries (Ahn Paragraph 0031).
Regarding Claim 9, the combination of Tsai, Kim, Chang, Huang, and Ahn teaches all of the limitations of the claimed invention as stated above.
Tsai does not teach: the second gate dielectric layer comprises praseodymium oxide.
Figure 3 of Chang teaches: a transistor (2), on a substrate (20) containing a gate dielectric layer (22) comprising praseodymium oxide (Paragraph 0038).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second gate dielectric layer comprise praseodymium oxide because praseodymium oxide has a high dielectric constant and high bandgap that effectively decreases the leakage current and the equivalent oxide thickness (EOT) of the device (Chang Paragraph 0052) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding Claim 11, Tsai teaches: the first gate dielectric layer comprises an oxide or nitride of a rare earth metal having a bandgap energy of greater than 5.3 eV (Paragraph 0043; lists an oxide of La or Lanthanum as a potential dielectric material. Lanthanum oxide has a bandgap energy of approximately 5.8 eV).
Regarding Claim 14, the combination of Tsai, Kim, Chang, Huang, and Ahn teaches all of the limitations of the claimed invention as stated above.
Tsai does not teach: the transistor is characterized by a threshold voltage determined at least partly by a distance between dipole inducing elements in the dipole layer on the first gate dielectric layer and a surface of the silicon substrate.
Figure 3 of Kim teaches: transistors (TR5-8) on a substrate (100) with a first gate dielectric layer (152) has a thickness of T2 and a third gate dielectric layer (151) has a thickness of T1, wherein the thickness of the first dielectric layer adjusts the threshold voltage of the transistor (Paragraph 0093).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the transistor is characterized by a threshold voltage determined at least partly by a distance between dipole inducing elements in the dipole layer on the first gate dielectric layer and a surface of the silicon substrate because Kim teaches that modifying the thickness of the dielectric layer varies the threshold voltage (Kim Paragraph 0093). As the dielectric layer of Tsai is between the dipole inducing layer and the substrate, the distance between the dipole inducing elements in the first dipole inducing layer and a surface of the semiconductor substrate will be directly impacted by the thickness of the dielectric layer. Therefore, the threshold voltage will be determined by tuning the thickness of the dielectric layer of each transistor.
Regarding Claim 15, Figure 27 of Tsai teaches: A semiconductor structure (Paragraph 0015), comprising: a silicon substrate (50) comprising a first region (58C) and a second region (58B); a first transistor (Paragraph 0019; transistor in region 58B) disposed in the first region, wherein the first transistor comprises a first gate stack (combination of 100, 102B/102, 116, and 120) comprising: a first portion (portion in region 58C) of an interfacial layer (100) disposed on the silicon substrate in the first region; a first dielectric layer (102B) disposed on the first portion of the interfacial layer and having a first thickness (Examiner notes it is inherent that the layer has some thickness.); a first portion (portion in region 58C) of a dipole layer residue (104) disposed on the first gate dielectric layer; and a first portion of a second dielectric layer (116; Paragraph 0053 where 116 is made of the same material as 112, TaN) disposed on the first portion of the dipole layer residue; and a second transistor (Paragraph 0019; transistor in region 58C) disposed in the second region, wherein the second transistor comprises a second gate stack (combination of 100, 102, 116, and 120) comprising: a second portion (portion in region 58B) of the interfacial layer disposed on the silicon substrate in the second region; a third gate dielectric layer (102A) disposed on the second portion of the interfacial layer and having a second thickness (Examiner notes it is inherent that the layer has some thickness.), a second portion of the dipole layer residue (104) disposed on the first gate dielectric layer; and a second portion of the second gate dielectric layer (116) disposed on the second portion of the dipole layer residue; [Examiner’s note: The material of layer 112, TaN, can be used as a gate dielectric layer, as evidenced by Huang Paragraph 0033.]
Further, the process limitation “the first portion of the dipole layer residue remaining following an annealing process on a dipole layer” and “the second portion of the dipole layer residue remaining following the annealing process on the dipole layer” found in product Claim 15, invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of Claim 15, does not require that the first portion of the dipole layer residue is formed following an annealing process on a first dipole layer, but simply that the first portion of the dipole layer residue is capable of being formed by an annealing process. However, Tsai does teach an annealing process performed on a dipole layer (Paragraph 0066). Therefore, the process limitation does not structurally distinguish the claimed invention over the prior art.
Tsai does not teach: wherein the second thickness is larger than the first thickness; and wherein a first distance between dipole inducing elements in the first portion of the dipole layer and a bottom surface of the first portion of the interfacial layer is varied, by tuning the first thickness, to adjust a first threshold voltage of the first transistor, and wherein a second distance between dipole inducing elements in the second portion of the dipole layer and a bottom surface of the second portion of the interfacial layer, by tuning the second thickness, to adjust a second threshold voltage of the second transistor.
Figure 3 of Kim teaches: transistors (TR5-8) on a substrate (100) with a first gate dielectric layer (152) has a thickness of T2 and a third gate dielectric layer (151) has a thickness of T1, wherein the thickness of the first dielectric layer is thinner than the third dielectric layer (Paragraph 0093.)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first thickness be less than the second thickness because Kim teaches that modifying the thickness of the dielectric layer varies the threshold voltage (Kim Paragraph 0093). As the dielectric layer of Tsai is between the dipole inducing layer and the substrate, the distance between the dipole inducing elements in the first dipole inducing layer and a surface of the semiconductor substrate as well as the distance between the dipole inducing elements in the second dipole inducing layer and a surface of the semiconductor substrate, will be directly impacted by the thickness of the dielectric layer. Therefore, the threshold voltage will be determined by tuning the thickness of the dielectric layer.
Tsai does not teach: a first portion of a conductive work function layer disposed on the first portion of the second dielectric layer; a second portion of a conductive work function layer disposed on the second portion of the second dielectric layer;
Figures 2D1-2D3 of Huang teach: a conductive work function layer (244) is formed over a gate dielectric layer (242/243)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a first portion of a conductive work function layer disposed on the first portion of the second dielectric layer; a second portion of a conductive work function layer disposed on the second portion of the second dielectric layer because the conductive work function layer tunes the work function of the device (Huang Paragraph 0034).
Tsai does not teach: the first gate dielectric layer and the third gate dielectric layer comprising praseodymium oxide
Figure 3 of Chang teaches: a transistor (2), on a substrate (20) containing a gate dielectric layer (22) comprising praseodymium oxide (Paragraph 0038).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric layer of Tsai to include praseodymium oxide because praseodymium oxide has a high dielectric constant and high bandgap that effectively decreases the leakage current and the equivalent oxide thickness (EOT) of the device (Chang Paragraph 0052) .and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Tsai does not teach: the first gate dielectric layer and the third gate dielectric layer comprising praseodymium oxide is substantially amorphous
Figure 1 of Anh teaches: a semiconductor device (110), with a praseodymium oxide dielectric layer (114) that is substantially amorphous
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first gate dielectric layer comprising praseodymium oxide being substantially amorphous because Anh teaches amorphous dielectric materials provide lower leakage currents due to the lack of defects along grain boundaries (Ahn Paragraph 0031).
Regarding Claim 16, the combination of Tsai, Kim, Chang, Huang, and Ahn teach all of the limitations of the claimed limitation as stated above.
Tsai does not teach: the first transistor is characterized by a first EOT and the second transistor is characterized by a second EOT, and the first EOT is less than or equal to the second EOT.
The combination of Tsai and Kim teaches the first dielectric of Tsai is thinner than the third dielectric of Tsai, because Kim teaches that by tuning the thickness of the dielectric layer, the threshold voltage of a transistor can be controlled. The threshold voltage of a transistor is directly proportional to oxide thickness, therefore the thinner the oxide thickness, the lower the threshold voltage. Therefore, the combination of Tsai and Kim teaches a transistor with a thinner dielectric layer, will have a lower threshold voltage, and a lower equivalent oxide thickness (EOT).
Regarding Claim 17, the combination of Tsai, Kim, Chang, Huang, and Ahn teaches all of the limitations of the claimed invention as stated above.
Tsai does not teach: the second gate dielectric layer comprises praseodymium oxide.
Figure 3 of Chang teaches: a transistor (2), on a substrate (20) containing a gate dielectric layer (22) comprising praseodymium oxide (Paragraph 0038).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate dielectric layer of Tsai to include praseodymium oxide because praseodymium oxide has a high dielectric constant and high bandgap that effectively decreases the leakage current and the equivalent oxide thickness (EOT) of the device (Chang Paragraph 0052) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding Claim 19, the process limitation “the first portion of the interfacial layer and the second portion of the interfacial layer are formed simultaneously; the first portion of the dipole layer residue and the second portion of the dipole layer residue are formed simultaneously; and the first portion of the second gate dielectric layer and the second portion of the second gate dielectric layer are formed simultaneously” found in product claim 19 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of Claim 19 does not require that the first and second portion of the interfacial layer are formed simultaneously, the first and second portion of the dipole layer are formed simultaneously, and the first portion and second portion of the second dielectric layer are formed simultaneously, but simply that the first and second portion of the interfacial layer are formed, the first and second portion of the dipole layer are formed, and the first portion and second portion of the second dielectric layer are formed in the appropriate order and location. Tsai does teach an interfacial layer (100) with a first (portion in region 58C) and second portion (portion in region 58B), a first (138) and a second (104) dipole layer, and a first (portion in region 58C) and second (portion in region 58B) portion of the second dielectric layer (140). Therefore, the process limitation does not structurally distinguish the claimed product invention over the prior art.
Regarding Claim 20, the process limitation “the first gate dielectric layer is formed by performing a first number of atomic layer deposition (ALD) cycles; and the third gate dielectric layer is formed by performing the first number of ALD cycles, simultaneously while forming the first gate dielectric layer, followed by performing additional ALD cycles” found in product claim 19 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of Claim 20 does not require that the first dielectric layer is formed by performing a first number of atomic layer deposition (ALD) cycles; and the third dielectric layer is formed by performing the first number of ALD cycles, simultaneously while forming the first dielectric layer, followed by performing additional ALD cycles, but simply that the first dielectric layer and the third dielectric layer are capable of being formed by an ALD process. Tsai does teach; a first dielectric layer (102B) and a third dielectric layer (102A) by ALD (Tsai Paragraph 0043). Therefore, the process limitation does not structurally distinguish the claimed invention over the prior art.
Regarding Claim 24, the combination of Tsai, Kim, Chang, Huang, and Ahn teaches all of the limitations of the claimed invention as stated above.
Tsai does not teach: the conductive work function layer comprises titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, ZrSi2, MoSi2, TaSi2, or NiSi2
Figures 2D1-2D3 of Huang teach: the conductive work function layer (244) can comprise titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, ZrSi2, MoSi2, TaSi2, or NiSi2 (Huang Paragraph 0034).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the conductive work function layer comprises titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, ZrSi2, MoSi2, TaSi2, or NiSi2 because Huang teaches these are suitable examples of p-type work function materials to tune the work function of the device (Huang Paragraph 0034).
Claims 18 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al (US 20200119019 A1) hereinafter “Tsai” in view of Kim et al (US 20150187763 A1) hereinafter “Kim,” Chang et al (US 20120080760 A1) hereinafter “Chang,” Huang et al. (US 20190131185 A1) hereinafter “Huang”, Ahn et al. (US 20140138795 A1) hereinafter “Ahn” and Tong (US 20130316546 A1) hereinafter “Tong”.
Regarding Claim 18, the combination of Tsai, Kim, Chang, Huang, and Ahn teach all of the limitations of the claimed invention.
Tsai does not teach: the second gate dielectric layer comprises hafnium oxide.
Figure 2B of Tong teaches: a transistor (Paragraph 0029) with a gate dielectric layer (210) comprising hafnium oxide (Paragraph 0033)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second gate dielectric layer comprise hafnium oxide because Tong teaches hafnium oxide as a gate dielectric can improve the performance characteristics of semiconductor devices (Tong Paragraph 0033).
Regarding Claim 21, the combination of Tsai, Kim, Chang, Huang, and Ahn teach all of the limitations of the claimed invention.
Tsai does not teach: the second gate dielectric layer comprises hafnium oxide.
Figure 2B of Tong teaches: a transistor (Paragraph 0029) with a gate dielectric layer (210) comprising hafnium oxide (Paragraph 0033)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second gate dielectric layer comprise hafnium oxide because Tong teaches hafnium oxide as a gate dielectric can improve the performance characteristics of semiconductor devices (Tong Paragraph 0033).
Regarding Claim 22, the combination of Tsai, Kim, Chang, Huang and Ahn teach all of the limitations of the claimed invention.
Tsai does not teach: the second gate dielectric layer comprises hafnium oxide.
Figure 2B of Tong teaches: a transistor (Paragraph 0029) with a gate dielectric layer (210) comprising hafnium oxide (Paragraph 0033)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second gate dielectric layer comprise hafnium oxide because Tong teaches hafnium oxide as a gate dielectric can improve the performance characteristics of semiconductor devices (Tong Paragraph 0033).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al (US 20200119019 A1) hereinafter “Tsai” in view of Kim et al (US 20150187763 A1) hereinafter “Kim,” Chang et al (US 20120080760 A1) hereinafter “Chang,” Huang et al. (US 20190131185 A1) hereinafter “Huang”, Ahn et al. (US 20140138795 A1) hereinafter “Ahn” and Loubet et al. (US 20170323949 A1) hereinafter, “Loubet.”
Regarding Claim 25, the combination of Tsai, Kim, Chang, Huang and Ahn teach all of the limitations of the claimed invention.
Tsai does not teach: the annealing process is performed at a temperature ranging from about 800°C to about 1100°C.
Figures 2 and 3 of Loubet teach: a gate-all-around FET (Paragraph 0023) with a high-k dielectric (210) of Praseodymium oxide (Paragraph 0025) that undergoes an anneal (Paragraph 0027) performed at a temperature between 950 and 1200 degrees Celsius (Paragraph 0027).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the annealing process is performed at a temperature ranging from about 800°C to about 1100°C because annealing praseodymium oxide in this range densifies the high-k dielectric that results in an improvement in negative-bias temperature instability or positive-bias temperature instability which are reliability issues in MOSFETS (Loubet Paragraph 0027).
Furthermore, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists, MPEP 2144.05, In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, the claimed temperature range of 800 degrees Celsius to about 1100 degrees Celsius overlaps the range of Loubet of 950 to 1200 degrees Celsius.
Allowable Subject Matter
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 23, the prior art of record does not teach, suggest, or motivate one having ordinary skill in the art to have the first gate dielectric layer comprises a material which, in response to a 1 V potential, experiences a leakage current density less than 10-8 A/cm2, when having an equivalent oxide thickness (EOT) of 1.4 nm after being exposed to a temperature of about 1000° C for about 15 s along with all of the limitations of Claim 1.
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed 12/29/2025, with respect to the rejections of Claims 1, 8 and 15 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Tsai, Kim, Chang, Huang, and Ahn.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HALEE CRAMER/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891