Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 12/30/2025 is acknowledged. Claims 1-20 remain pending.
Drawings
The drawings are objected to because Fig. 4 contains the label 100B, but is labelled 110B in the specification (see Para. [0047]). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: In Para. [0048], the specification states “Furthermore, the dummy dies 150…may be disposed between the adjacent two of die regions 110A, 110B”. Examiner is unsure what this means.
Appropriate correction is required.
Claim Objections
Claim 6 is objected to because of the following informalities: the claim states in part “…are respectively disposed between adjacent two of the conductive connectors”. In the view of the Examiner, this should say “…between two adjacent conductive connectors.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation "the second regions of the interposer". There is insufficient antecedent basis for this limitation in the claim. Claim 20 refers to a second regions, but does not mention any plurality of second regions prior.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 8 are rejected under 35 U.S.C. 102a2 as being anticipated by US20240021640A1 (Liao).
Regarding Claim 1, Liao discloses a semiconductor device (Fig. 1, el. 10, Para. [0048]), comprising: an interposer (Fig. 1, el. 270, Para. [0055]), comprising a first region and a second region (see annotated Fig. 1 below); a first die (Fig. 1, el. 110, Para. [0048]) and a second die (Fig. 1, el. 110, Para. [0048]), bonded to a first surface of the interposer (Fig. 1, Para. [0064]), the first die disposed in the first region (see annotated Fig. 1 below), and the second die disposed in the second region (see annotated Fig. 1 below); and a third die (Fig. 1, el. 240, Para. [0055]) and a dummy die (Fig. 1, el. 250, Para. [0055]), bonded to a second surface (Fig. 1, el. 272, Para. [0060]) opposite to the first surface of the interposer (Fig. 1), wherein the third die is disposed in the first region and the dummy die is disposed in the second region (see annotated Fig. 1 below).
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Regarding Claim 2, Liao discloses the semiconductor device of claim 1, wherein the first die and the third die are overlapped along a stacking direction of the first die and the interposer, and the second die and the dummy die are overlapped along the stacking direction (see annotated Fig. 1 above).
Regarding Claim 3, Liao discloses the semiconductor device of Claim 1, wherein the third die is electrically connected to the first die through the interposer (Para. [0064]), and the dummy die is electrically isolated form the second die (Para. [0059]).
Regarding Claim 8, Liao discloses the semiconductor device of Claim 1, wherein the third die is an Large scale integrated (LSI) chip (Para. [0059] – where the third chip is described as a controller chip, which is an LSI chip).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of US20190096825A1 (Kim).
Regarding Claim 4, Liao discloses the semiconductor device of Claim 1, wherein the interposer comprises at least one active conductive pattern (Para. [0060] – “The upper redistribution layer 270 is electrically connected to the second conductive pillars 241 of the active device 240….”), and the third die is electrically connected to the at least one active conductive pattern (Fig. 1).
Liao does not disclose that the interposer comprises at least one dummy conductive pattern and the dummy die electrically connected to the least one dummy conductive pattern.
Kim discloses a semiconductor package (Fig. 9, el. 100, Para. [0073]) comprising a dummy die (Fig. 9, el. 132, Para. [0073]), an interposer (Fig. 9, el. 140, Para. [0073]) where the dummy die may be electrically connected to at least one dummy conductive pattern (Para. [0089]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to replace one of the active patterns in Liao with a dummy conductive pattern and connect the dummy die to that pattern, in the manner described by Kim. As disclosed by Kim, this may be helpful to perform a warpage reduction function (Para. [0089]).
Regarding Claim 5, Liao in view of Kim discloses the semiconductor device of claim 4, wherein the at least one active conductive pattern and the at least one dummy conductive pattern are provided within a same dielectric layer (Liao, Para. [0060]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liao.
Regarding Claim 6, Liao discloses the semiconductor device of Claim 1, further comprising a plurality of conductive pillars (Fig. 1, el. 220, Para. [0055]) disposed on the second surface of the interposer, wherein the third die and the dummy die are respectively disposed between adjacent two of the conductive pillars (Fig. 1), and the conductive pillars are connected to conductive connectors (Fig. 1, el. 280, Para. [0055])
Liao does not disclose that the third die and dummy die are respectively disposed between two adjacent conductive pillars.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to remove the conductive connectors between the conductive pillars (the ones that are not connected to any conductive pillars). This has the benefit of simplifying the design and saving material.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liao.
Regarding Claim 7, Liao discloses the semiconductor device of claim 1, further comprising an underfill surrounding the third die and the dummy die (Para. [0058]).
Liao does not disclose that the underfill surrounds the interposer.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to extend the underfill so that it surrounds the interposer. This would have the benefit of providing better structural support for the device.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over US20240162101A1 (Li) in view of US20190371694A1 (Hsu).
Regarding Claim 9, Li discloses a semiconductor device (Figs 3G, el. 3, Para. [0069]), comprising: an interposer (Figs. 3A-3G, el. 26, Para. [0055]), a first integrated circuit (Fig. 3G, el. 22 – the chip on the right side of the figure, Para. [0062]) and a second integrated circuit (Fig. 3G, el. 22 – the chip on the left side of the figure, Para. [0062]), bonded to a first surface of the interposer (Fig. 3G, Para. [0062]); and a functional die (Fig. 3G, el. 21, Para. [0055]) and a dummy die (Fig. 3G, el. 28, Para. [0055]), wherein the functional die is overlapped with and electrically connected to the first integrated circuit through the interposer (Para. [0085]), and the dummy die is overlapped with the second integrated circuit (Fig. 3H).
Li does not disclose that the functional die and the dummy die are bonded to a second surface of the interposer.
Hsu discloses a semiconductor package (Figs 5, Para. 0042]) comprising a dummy die (Fig. 5, el. 140, Para. [0042]), a functional die (Fig. 5, el. 110, Para. [0042]), an RDL layer (Fig. 5, RDL1) where the dummy die and functional die are attached to the RDL layer (Para. [0018] – which describes the die attach film DAF used to attach the dies to the RDL layer).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to attach the dummy die and functional die to the interposer, as described in Hsu. This would have the benefit of providing a more secure package.
Regarding Claim 10, Li discloses the semiconductor device of claim 9, further comprising a first encapsulant disposed on a first surface of the interposer (Fig. 3E, el. 24, Para. [0063]), wherein the first encapsulant encapsulates the first integrated circuit and the second integrated circuit (Fig. 3E, Para. [0063]), and a top surface of the first encapsulant is substantially coplanar with top surfaces of the first integrated circuit and the second integrated circuit (Para. [0065]).
Regarding Claim 11, Li discloses the semiconductor device of claim 9, further comprising a first encapsulant (Fig. 3E, el. 24, Para. [0063]) disposed on the first surface of the interposer (Fig. 3E) and a second encapsulant (Para. [0062] – where the underfill can be considered as a second encapsulant) between the first integrated circuit and the second integrated circuit (the underfill would be between the two semiconductor chips 22), wherein the first encapsulant encapsulates the first integrated circuit, the second integrated circuit, and the second encapsulant (Para. [0063]).
Regarding Claim 12, Li discloses the semiconductor device of claim 9, further comprising a first encapsulant disposed on the first surface of the interposer (Fig. 3E, el. 24, Para. [0063]) and a third encapsulant, wherein the third encapsulant encapsulates the functional die, the dummy die
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Hsu.
Regarding Claim 13, Li discloses the semiconductor device of claim 9.
Li does not disclose that the dummy die comprises a plurality of conductive connectors bonded to the second surface of the interposer without extending into the interposer.
Hsu discloses a semiconductor package (Fig. 3A-3F, Para. [0032]), comprising a dummy die (Fig. 3B, el. 140, Para. [0034]), another die (Fig. 3B, el. 130, Para. [0034]), a redistribution layer (Fig. 3C, el. RDL2, Para. [0036]), where the dummy die comprises a plurality of conductive connectors (Fig. 3C, el. 146, Para. [0019]) bonded to a surface of the redistribution layer (Fig. 1C, Para. [0022]) without extending into the redistribution layer (Fig. 1C).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add conductive connectors to the dummy die of Li without extending into the interposer, as disclosed by Hsu. As implied by Hsu, the dummy die may not be completely non-functional (Para. [0022]), and it may be advantageous to have some active elements in the dummy die that can connect to the rest of the circuit. Not extending the conductive connectors into the interposer makes manufacturing the layers and connectors easier.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Hsu.
Regarding Claim 14, Li in view of Hsu discloses the semiconductor device of Claim 9, further comprising a package substrate (Li, Fig. 3G, el. 201, Para. [0069], such that the functional die and the dummy die are disposed between the interposer and the package substrate (Li, Fig. 3G).
Li does not disclose that the interposer is bonded to the substrate.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add bonding structures between the interposer and package substrate to produce a more secure package.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US20200006252A1 (Yu) in view of US20190371694A1 (Hsu).
Regarding Claim 15, Yu discloses a semiconductor device (Figs. 1-9 which disclose method steps for building the device 60 in Fig. 9, Para. [0014] and [0028]) comprising: an interposer (Fig. 7, el. 56, Para. [0024]) comprising a first region (see annotated Fig. 9 below); a first integrated circuit (see annotated Fig. 9 below, el. 62, Para. [0029], bonded to a first surface of the interposer (Fig. 9, Para. [0029]) and disposed in the first region (see annotated Fig. 9 below); and a plurality of functional dies (Fig. 1, el. 26, Para. [0016]) and at least one dummy die (Fig. 2, el. 36, Para. [0018], that extend so that they touch a second surface of the interposer (see annotated Fig. 4 below) wherein the functional dies and the at least one first dummy die are disposed in the first region (see annotated Fig. 9 below).
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Yu does not disclose that the plurality of functional dies and the at least one dummy die are attached to the second surface of the interposer.
Hsu discloses a semiconductor package (Figs 5, Para. 0042]) comprising a dummy die (Fig. 5, el. 140, Para. [0042]), a functional die (Fig. 5, el. 110, Para. [0042]), an RDL layer (Fig. 5, RDL1) where the dummy die and functional die are attached to the RDL layer (Para. [0018] – which describes the die attach film DAF used to attach the dies to the RDL layer).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to attach the dummy die and functional die to the interposer, as described in Hsu. This would have the benefit of providing a more secure package.
Regarding Claim 16, Yu in view of Hsu discloses the semiconductor device of claim 15, wherein the at least one first dummy die is disposed between the functional dies (Yu, Fig. 17, Para. [0041]).
Regarding Claim 17, Yu in view of Hsu discloses the semiconductor device of claim 15, wherein the functional dies and the at least one dummy die are disposed in an array (Yu, Figs. 12A, 12B, and 13-15, Para. [0041]).
Regarding Claim 18, Yu in view of Hsu discloses the semiconductor device of claim 15, wherein the at least one second dummy die is disposed at a corner region of the first region (Yu, Fig. 12B, Para. [0039]).
Regarding Claim 19, Yu in view of Hsu discloses the semiconductor device of claim 15, further comprising: a second integrated circuit (Yu, see annotated Fig. 9 above, el. 62, Para. [0029])), bonded to the first surface of the interposer (Fig. 9, Para. [0029]) and disposed in a second region of the interposer (see annotated Fig. 9 above); and at least one second dummy die (see annotated Fig. 9 above, el. 36), bonded to the second surface opposite to the first surface of the interposer and disposed in the second region of the interposer (see annotated Fig. 9 above).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Hsu.
Regarding Claim 20, Yu in view of Hsu discloses the semiconductor device of claim 15, further comprising: a second integrated circuit (Yu, see annotated Fig. 9 above, el. 62, Para. [0029])), bonded to the first surface of the interposer (Fig. 9, Para. [0029]) and disposed in a second region of the interposer (see annotated Fig. 9 above); and at least one second dummy die (see annotated Fig. 9 above, el. 36), bonded to the second surface opposite to the first surface of the interposer.
Yu in view of Hsu does not disclose that the second dummy die is disposed between the first region and the second region or between the second regions of the interposer.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to place a dummy die between the first region and the second region. Such a placement would be an example of a simple rearrangement of parts (MPEP 2144.04(VI)(C)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899