DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 24, 2026 has been entered.
Status of the Claims
Species 1 is Elected.
Amendment filed June 26, 2026 is acknowledged. Claims 1, 8, and 15 have been amended. Claims 1-3 and 5-21 are pending.
Action on merits of Species 1, claims 1-3 and 5-21 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-3 and 5-21 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “wherein a portion of the substrate is disposed on a top surface of the p-type region, and
wherein the top surface of the p-type region is disposed below the top surface of the substrate;” (amended claims 1, 8 and 15) (emphasis added) in the application as filed.
Note that on top surface of the p-type region 308 is the “buffer oxide” ass shown in FIGS. 3C, 5E-5H.
As shown in FIG. 5H, above the finFET is the “buffer oxide” 358a,b.
Therefore the limitations: “wherein a portion of the substrate is disposed on a top surface of the p-type region, and wherein the top surface of the p-type region is disposed below the top surface of the substrate;” are new matters.
As shown in FIG. 5H, above the finFET is the “buffer oxide” 358a,b.
Applicant must cancel the un-support new matters in response to the Office Action.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, 5 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over LYU (US. Pub. No. 2006/0084195) in view of AMARI (US. Patent No. 8,937,349) both of record, and STEVENS et al. (US. Patent No. 6,730,899).
With respect to claim 1, LYU teaches a pixel sensor substantially as claimed, including:
a substrate (100);
a photodiode (PD) included in the substrate, the photodiode including:
an n-type region (156), and
a p-type region (155) over the n-type region (156),
wherein top surface of the p-type region (155) is disposed below a top surface of gate insulation layer; and
a transfer fin field effect transistor (finFET) (TG), configured to transfer a photocurrent from the photodiode (PD) to a drain region (160) of the pixel sensor, comprising:
at least a portion of the n-type region (156),
a drain extension region (160a) coupled to the drain region (160),
a channel fin (104) coupling the n-type region (156) and the drain extension region (160a), and
a transfer gate (120) at least partially surrounding the channel fin. (See FIGs. 4A-B).
Thus, Lyu is shown to teach all the features of the claim with the exception of explicitly disclosing a portion of the substrate is disposed on a top surface of the p-type region; and the finFET comprising a plurality of channel fins.
However, STEVENS teaches a pixel sensor including:
a substrate (73);
a photodiode (69) included in the substrate (73), the photodiode comprising:
an n-type region (70), and
a p-type region (72) over the n-type region (70),
wherein a portion of the substrate is disposed on a top surface of the p-type region (72), and
wherein the top surface of the p-type region (72) is disposed below the top surface of the substrate; and
a transfer field effect transistor configured to transfer a photocurrent from the photodiode (69) to a drain region (80) of the pixel sensor. (See FIG. 4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the photodiode of LYU comprising the top surface of the p-type region being disposed below the top surface of the substrate as taught by STEVENS to reduce dark current.
Further, AMARI teaches a semiconductor device including:
a substrate (101);
a fin field effect transistor (finFET), configured to transfer a current from a source region (112s) to a drain region (112Hd), comprising:
a drain extension region (112Ld) coupled to the drain region (112HD),
a plurality of channel fin (101c) coupling the source region (112s) and the drain extension region (112Ld), and
a transfer gate (111g) at least partially surrounding the channel fins (101c),
wherein the source region (112s) is spaced away downward from a top surface of the substrate (101). (See FIGs. 1-4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the transfer finFET of LYU comprising the plurality of channel fins as taught by AMARI to increase effective channel width.
With respect to claim 3, As best understood by the Examiner, in view of AMARI, the semiconductor device further comprises:
a first buffer oxide region (SZ, left) between the transfer gate (111g) and the source region (112s); and
a second buffer oxide region (SZ, right) between the transfer gate (111g) and the drain extension region (112Ld).
With respect to claim 5, in view of AMARI, the drain extension region (112Ld) is spaced away from a top surface of a silicon substrate.
With respect to claim 21, the pixel sensor of LYU or STEVENS further comprises: a metallization layer above the substrate; and an interconnect that electrically connects the drain region (160) with the metallization layer.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over LYU, STEVENS ‘899 and AMARI ‘349 as applied to claim 1 above, and further in view of KAWAGUCHI (US. Pub. No. 2010/0327345) of record.
With respect to claim 2, LYU, in view of STEVENS and AMARI, teaches the pixel sensor as described in claim 1 above including: a transfer gate (111g) at least partially surrounding the channel fins.
Thus, LYU and AMARI are shown to teach all the features of the claim with the exception of explicitly disclosing another p-type region, below the transfer gate.
However, KAWAGUCHI teaches a semiconductor device including:
a transfer gate (122) at least partially surrounding a plurality of channel fins (108); and
another p-type region (130), below the transfer gate (122), configured to provide electrical isolation for the transfer gate. (See FIG. 14C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pixel sensor of LYU further comprising another p-type region, below the transfer gate as taught by KAWAGUCHI to improve subthreshold characteristic of the transistor.
With respect to claim 7, in view of KAWAGUCHI, the channel fins further comprises:
an extension implant (132) over the plurality of channel fins (108); and
an oxide layer (162) over the extension implant (132).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over LYU, STEVENS and AMARI as applied to claim 1 above, and further in view of RHODES et al. (US. Pub. No. 2005/0167708) of record.
LYU, in view of AMARI and STEVENS, teaches the pixel sensor as described in claim 1 above including: the photodiode comprising the n-type region.
Thus, LYU, AMARI and STEVENS are shown to teach all the features of the claim with the exception of explicitly disclosing a plurality of deep n-type region below the n-type region.
However, RHODES teaches a pixel sensor including:
a photodiode (PD) comprising an n-type region (900); and
a plurality of deep n-type regions (901, 902) below the n-type region. (See FIG. 3C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pixel sensor of LYU further including the plurality of deep n-type regions below the n-type region as taught by RHODES to minimize leakage.
Claims 8, 10, 13-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LYU (US. Pub. No. 2006/0084195) of record, in view of STEVENS ‘899 and KAWAGUCHI ‘345.
With respect to claim 8, As best understood by the Examiner, LYU teaches a pixel sensor substantially as claimed including:
a substrate (100);
a channel fin (104) in the substrate;
an n-type region (156) coupled to the channel fin (104) at a first side of the channel fin;
a first p-type region (155) over the n-type region (156),
wherein top surface of the p-type region (155) is disposed below a top surface of gate insulation layer;
a drain extension region (160a) coupled to the channel fin (104) at a second side of the channel fin opposing the first side;
a drain region (160b) coupled to the drain extension region (160a); and
a transfer gate (120) above and surrounding at least three sides of the channel fins (104). (See FIG. 4A).
Thus, Lyu is shown to teach all the features of the claim with the exception of explicitly disclosing a portion of the substrate is disposed on a top surface of the p-type region; and the channel fin being a plurality channel fins.
However, STEVENS teaches a pixel sensor including:
a substrate (73);
a channel in the substrate;
an n-type region (70) coupled to the channel at a first side of the channel;
a first p-type region (72) over the n-type region (70),
wherein a portion of the substrate is disposed on a top surface of the p-type region (72), and
wherein the top surface of the p-type region (72) is disposed below the top surface of the substrate;
a second p-type region (75a) below the channel; and
a transfer gate (76) above the p-type configured to transfer a photocurrent from the photodiode (69) to a drain region (80) of the pixel sensor. (See FIG. 4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the photodiode of LYU comprising the top surface of the p-type region being disposed below the top surface of the substrate as taught by STEVENS to reduce dark current.
Further, KAWAGUCHI teaches a semiconductor device including:
a substrate (102);
a plurality of channel fins (108) in the substrate (102);
a second p-type region (130) below the plurality of channel fins (108); and
a transfer gate (122) above the second p-type region (130) and surrounding at least three sides of the plurality of channel fins (108). (See FIG. 14C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pixel sensor of LYU comprising the transfer gate above the second p-type region as taught by KAWAGUCHI to improve subthreshold characteristic of the transistor.
With respect to claim 10, in view of KAWAGUCHI, the semiconductor device further comprises: a first buffer oxide region (140, left) above the second p-type region (130) and between the transfer gate (122) and the source region, thus, n-type region; and a second buffer oxide region (140, right) above the second p-type region (130) and between the transfer gate (122) and the drain region (113), hence extension region.
With respect to claim 13, in view of STEVENS, the drain region (80) is spaced away from the top surface of the substrate, thus, in view of STEVENS, the drain extension region of LYU would spaced away from the top surface of the substrate.
With respect to claim 14, the transfer gate (120) of LYU or STEVENS or KAWAGUCHI, is coupled to a gate electrode stack (TG).
With respect to claim 15, As best understood by the Examiner, LYU teaches a pixel sensor substantially as claimed including:
a substrate (100)
an n-type region (156);
a first p-type region (155) over the n-type region (156);
wherein top surface of the p-type region (155) is disposed below a top surface of gate insulation layer;
a drain extension region (160a);
a channel fin (104) coupling the n-type region (156) and the drain extension region (160a); and
a transfer gate (120) at least partially surrounding the channel fin (104). (See FIG. 4A).
Thus, LYU is shown to teach all the features of the claim with the exception of explicitly disclosing a portion of the substrate is disposed on a top surface of the p-type region; the channel fin being a plurality channel fins; and a second p-type region below the transfer gate.
However, STEVENS teaches a semiconductor device including:
a substrate (73);
an n-type region (70);
a first p-type region (72) over the n-type region (70),
wherein a portion of the substrate is disposed on a top surface of the p-type region (72), and
wherein the top surface of the p-type region (72) is disposed below the top surface of the substrate;
a channel coupling the n-type region (70) and the drain region (80);
a transfer gate (76) over the channel; and
a second p-type region (75a) below the transfer gate (76). (See FIG. 4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pixel sensor of LYU comprising the top surface of the p-type region being disposed below the top surface of the substrate as taught by STEVENS to reduce dark current.
Further, KAWAGUCHI teaches a semiconductor device including:
a substrate (102);
a plurality of channel fins (108) in the substrate (102);
a transfer gate (122) at least partially surrounding the plurality of channel fins (108); and
a second p-type region (130) below the transfer gate (122). (See FIG. 14C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pixel sensor of LYU comprising the second p-type region below the transfer gate as taught by KAWAGUCHI to improve subthreshold characteristic of the transistor.
With respect to claim 20, in view of KAWAGUCHI, the transistor further comprises: a plurality of isolation regions in between the plurality of channel fins.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over LYU, STEVENS and KAWAGUCHI, as applied to claim 8 above, and further in view of LEE et al. (US. Pub. No. 2020/0176581) of record.
LYU, in view of STEVENS and KAWAGUCHI, teaches the pixel sensor as described in claim 8 above including transfer gate surrounding at least three sides of the plurality of channel fins.
Thus, LYU, STEVENS and KAWAGUCHI are shown to teach all the features of the claim with the exception of explicitly disclosing the transfer gate being layers structure.
However, LEE teaches a semiconductor device including a finFET, wherein the transfer gate including:
a first titanium nitride layer (83);
a tantalum nitride layer over the first titanium nitride layer;
a second titanium nitride layer over the tantalum nitride layer;
a titanium aluminum layer over the second titanium nitride layer; and
a tungsten layer (88) over the titanium aluminum layer. (See FIG. 1A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the transfer gate of LYU utilizing the layers structure as taught by LEE to form a gate electrode.
Note that layer 86 of LEE is a multilayer of two or more of the materials: TaN, TiN, TiAl.
Moreover, given a finite number of materials and their compounds, it is obvious to try without undue experimentation.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over LYU, STEVENS and KAWAGUCHI, as applied to claim 8 above, and further in view of GOTO (US. Pub. No. 2010/0176460) of record.
LYU, in view of STEVENS and KAWAGUCHI, teaches the pixel sensor as described in claim 8 above including a transfer gate electrode (120c) coupled to the transfer gate (120b,c).
Thus, LYU, STEVENS and KAWAGUCHI are shown to teach all the features of the claim with the exception of explicitly disclosing an n-doped upper transfer gate electrode region over the transfer gate electrode.
However, GOTO teaches a semiconductor device including:
a transfer gate electrode (12a); and
an n-doped upper transfer gate electrode region (12b) over the transfer gate electrode (12a). (See FIG. 4E).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the transfer gate of LYU including the n-doped upper transfer gate electrode over the transfer gate electrode as taught by GOTO for the same intended purpose of forming the transfer gate.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over LYU, STEVENS and KAWAGUCHI as applied to claim 8 above, and further in view of RHODES ‘708 .
LYU, in view of STEVENS and KAWAGUCHI, teaches the pixel sensor as described in claim 8 above including: the photodiode comprising the n-type region; and the first p-type region.
Thus, LYU, in view of STEVENS and KWAGUCHI, is shown to teach all the features of the claim with the exception of explicitly disclosing a plurality of deep n-type region below the n-type region.
However, RHODES teaches a pixel sensor including:
a photodiode (PD) comprising an n-type region (900); and
a first deep n-type region (902);
a second deep n-type region (901) over the first deep n-type region (902). (See FIG. 3C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pixel sensor of LYU, in view of STEVENS, further including the plurality of deep n-type regions below the n-type region as taught by RHODES to minimize leakage.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over LYU, STEVENS and KAWAGUCHI as applied to claim 15 above, and further in view of NOZAKI et al. (US. Pub. No. 2013/0248937) of record.
With respect to claim 16, LYU, in view of STEVENS and KAWAGUCHI, teaches the pixel sensor as described in claim 15 above, including the drain extension region, the transfer gate and the second p-type region.
Thus, LYU, STEVENS and KAWAGUCHI are shown to teach all the features of the claim with the exception of explicitly disclosing a cell p-well region (CPW) over a deep P-well region (PDW).
However, NOZAKI teaches a pixel sensor including:
a deep p-well region (DPW) (375); and
a cell p-well region (CPW) (370) over the DPW (375),
wherein the CPW (370) and the DPW (375) surround at least the drain region (320), the transfer gate (360) , and the second p-type region (385) . (See FIG. 3A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the pixel sensor of LYU further including the cell p-well (CPW) over the deep p-well (DPW) as taught by NOZAKI to isolate one pixel from another.
With respect to claim 17, the CPW (370) of NOZAKI further comprises: an isolation structure (STI) that comprises one or more trenches.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over LYU, STEVENS, KAWAGUCHI and NOZAKI, as applied to claim 17 above, and further in view of ENDO (US. Pub. No. 2011/0089513) of record.
With respect to claim 18, LYU, in view of STEVENS, KAWAGUCHI and NOZAKI, teaches the pixel sensor as described in claim 17 above including the isolation structure (STI).
Thus, LYU, STEVENS, KAWAGUCHI and NOZAKI, are shown to teach all the features of the claim with the exception of explicitly disclosing a field implant layer.
However, ENDO teaches a pixel sensor including:
an isolation structure (104) that comprises one or more trenches, wherein the isolation structure (104) further comprises a field implant layer (FIL) (116) on sidewalls and a bottom surface of the isolation structure (104).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the isolation structure of LYU further including the field implant layer (FIL) on sidewalls and a bottom surface of the isolation structure as taught by ENDO to keep the dark current arising from the vicinity of the isolation structure to a minimum.
With respect to claim 19, in view of ENDO, the isolation structure further comprises an oxide layer (104) over the FIR (116).
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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