Prosecution Insights
Last updated: August 14, 2026
Application No. 18/447,482

INDUCTIVE DEVICE

Non-Final OA §103§112
Filed
Aug 10, 2023
Priority
Jul 29, 2020 — continuation of 11/322,576 +1 more
Examiner
ADHIKARI DAWADI, BIPANA
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Non-Final)
100%
Grant Probability
Favorable
2-3
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
8 granted / 8 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
36 currently pending
Career history
56
Total Applications
across all art units

Statute-Specific Performance

§103
49.5%
+9.5% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
38.5%
-1.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 8 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Regarding claim 10 objection, applicant amendment has been fully considered. The amendment overcomes the objection; hence the objection is withdrawn for claim 10. Regarding claims 1-7 rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections, hence 35 U.S.C. 112(b) rejection is withdrawn for claims 1-7. Applicant’s arguments with respect to claim(s) 1, 8 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The prior 35 U.S.C. § 102 rejection of claims 1 and 8 over Gardner is withdrawn in view of the amendments. However, the claims remain unpatentable under newly applied § 103 grounds. For claim 1, Crawford teaches forming magnetic material directly on conductive structures. For claims 8 and 14, Mizoguchi teaches locating a magnetic layer opening directly above the conductor as explained in the rejections below. Accordingly, Applicant’s arguments do not overcome the newly stated §103 rejections. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner (US 20010030591 A1) in view of Crawford (US 20060088971 A1). Re: Independent Claim 1 (Currently Amended), Gardner discloses a method, comprising: forming a first magnetic layer (Gardner, Fig 7, magnetic layer 312) directly on a second magnetic layer (Gardner, Fig 7, magnetic layer 304), a plurality of insulating layers, (first magnetic layer is over dielectric layers 306 and 310), wherein each of the plurality of insulating layers resides directly above of the second magnetic layer (insulating layers 306 and 310 resides directly above the second magnetic layer 304); and removing one or more portions, of the first magnetic layer, to form one or more openings in the first magnetic layer (forming slot 342 in the magnetic layer 312). Gardner is silent regarding, forming a first magnetic layer directly on one or more conductors. However, Crawford teaches forming a first magnetic layer directly on one or more conductors (Crawford teaches, in Fig. 5d and ¶ [0038], forming magnetic material 530 over first conductive layer 510 and, in Figs. 6a-6d and ¶ [0044], forming magnetic material 530 inside and around conductive layer 605). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gardner’s integrated inductor structure by forming the upper magnetic layer directly on exposed conductor portions, as taught by Crawford, because Crawford teaches, in ¶ [0027], that surrounding or contacting the conductive inductor structure with magnetic material increases magnetic flux and provides higher inductance per area, thereby allowing the inductor size to be reduced. Crawford further teaches, in ¶ [0028], that its conductive solenoid structure provides low resistance, making the inductor suitable for power-delivery applications. Thus, applying Crawford’s conductor-contacting magnetic-material arrangement to Gardner would have predictably improved magnetic coupling/integration and improved low-resistance conductor performance. Re: Claim 2 (Currently Amended), Gardner and Crawford disclose all the limitations of claim 1 on which this claim depends. Gardner further discloses, wherein the second magnetic layer has a first insulating layer, of the plurality of insulating layers, on at least a portion of a surface of the second magnetic layer (Garden shows, in Fig 7, dielectric layer 306 is on at least a portion of second magnetic layer 304). Re: Claim 3 (Original), Gardner and Crawford disclose all the limitations of claim 1 on which this claim depends. Gardner further discloses, wherein removing the one or more portions of the first magnetic layer comprises: forming a photoresist layer on the first magnetic layer; patterning the photoresist layer; and etching, after patterning the photoresist layer, the one or more portions of the first magnetic layer (Gardner, in ¶ [0065], teaches forming patterned mask over magnetic layer 312, etching and removing portions of the magnetic layer 312 to form slots 342 is performed using photoresist patterning and etching process). Re: Claim 4 (Currently amended), Gardner and Crawford disclose all the limitations of claim 1 on which this claim depends. Gardner further discloses, further comprising: forming the one or more conductors on a first insulating layer of the plurality of insulating layers (Gardner, Fig 7., conductive layers 308 on dielectric layer 306); forming a second insulating layer, of the plurality of insulating layers, on the first insulating layer and the one or more conductors (forming second dielectric layer 310 on first dielectric layer 306 and conductive layer 308); and forming the first magnetic layer to cover the second insulating layer and the one or more portions of the second magnetic layer (magnetic layer 312 covers dielectric layer 310 and magnetic layer 304). Re: Claim 5 (Original), Gardner and Crawford disclose all the limitations of claim 1 on which this claim depends. Gardner further discloses, wherein removing the one or more portions of the first magnetic layer comprises: determining, based on one or more performance parameters for an inductive device, at least one of: a respective shape for each of the one or more openings, a respective size for each of the one or more openings, or a respective location in the first magnetic layer for each of the one or more openings; and removing the one or more portions of the first magnetic layer to form the one or more openings based on the at least one of: the respective shape for each of the one or more openings, the respective size for each of the one or more openings, or the respective location in the first magnetic layer for each of the one or more openings (Gardner (¶ [0028], Fig. 1) teaches magnetic layer 120 for one embodiment defines slots, such as slots 122 and 124 for example, to help further reduce any Eddy currents in the substrate. Magnetic layer 120 may define any suitable number of one or more slots with any suitable dimensions and orientation at any suitable one or more locations relative to conductor 110. One or more slots may be perpendicular to or at any other suitable angle relative to the flow of current through conductor 110. Gardner further explains that defining slots in magnetic layer 120 also reduces Eddy currents that can form in magnetic layer 120 and helps to increase the resonance frequency for inductor 100. Thus, Gardner teaches that the shape/orientation, size/dimensions and location of the openings (slots 122, 124, 342) in the magnetic layer are design variables that affect performance parameters of the inductive device, including eddy current reduction and resonant frequency. While Gardner does not recite in express words a separate "determining" step, it is clear from this disclosure that a person of ordinary skill in the art, implementing Gardner's structure, would select the shape, size and/or location of the slots in the first magnetic layer based on desired performance parameters of the inductor, such as reducing eddy currents and increasing resonance frequency. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the method of removing portions of the magnetic layer by first determining, based on one or more performance parameters for the inductive device, at least one of: the shape, the size and/or location of each opening in the first magnetic layer, and then to form the corresponding openings by masking and etching the first magnetic layer in accordance with that selected geometry, exactly as Gardner already teaches for slots 122, 124, 342 in order to reducing eddy currents and increasing resonance frequency. Re: Claim 7 (Original), Gardner and Crawford disclose all the limitations of claim 5 on which this claim depends. Gardner further discloses, wherein a shape of an opening of the one or more openings includes a trench; and wherein a size of the opening includes a length parameter of the trench, a width parameter of the trench, and a depth parameter of the trench (Fig. 7, ¶¶ [0064]-[0065], Gardner's slot 342 are elongated openings i.e., they are formed by etching through the thickness of the magnetic layer to expose the underlying dielectric, and they extend laterally along the magnetic layer with a finite length and width. Thus, Gardner teaches or at least renders obvious openings in the first magnetic layer that are trench-shaped slots whose size includes a length parameter, a width parameter, and a depth parameter). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the opening is a "trench" and that its size includes length/width/depth that form the conventional geometric parameters of the elongated slots already disclosed by Gardner. Selecting and characterizing the openings in terms of these three parameters would have been an obvious deign choice based on Gardner's teaching that the slots may have any suitable dimensions and are used to tune inductor performance (Gardner ¶ [0038]). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gardner (US 20010030591 A1) in view of Crawford (US 20060088971 A1) further in view of Cappabianca (US 20190221365 A1). Re: Claim 6 (Original), Gardner and Crawford disclose all the limitations of claim 5 on which this claim depends. Gardner and Crawford are silent regarding, wherein the one or more performance parameters include at least one of a maximum inductance for the inductive device or a saturation current for the inductive device. However, Cappabianca teaches wherein the one or more performance parameters include at least one of a maximum inductance for the inductive device or a saturation current for the inductive device (Cappabianca, in Fig. 2, ¶ [0035], teaches that shell gaps 205c and 205d in a magnetized shell 202 and 203) are added to control a saturation current of Inductor 200 and the gap geometry in the magnetic structure is selected to control these values). Gardner, Crawford and Cappabianca teach method of forming inductors, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention when implementing Gardner's inductor and already choosing slot shape/size/location in the first magnetic layer to affect performance (eddy currents and resonance frequency), to additionally include as performance parameters a desired saturation current level for the inductive device, and to adjust the slot geometry accordingly in order to allow Inductor to pass higher current than without the opening/gaps (Cappabianca, ¶ [0035]). Claim 8-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner (US 20010030591 A1) in view of Mizoguchi (US 6593841 B1). Re: Independent Claim 8 (Currently Amended), Gardner discloses a method, comprising: forming a first insulating layer on a first magnetic layer ((Gardner, Fig 2 and Fig. 7) dielectric layer 306 on magnetic layer 304); forming one or more conductors on the first insulating layer ((Gardner, Fig 2 and Fig. 7) conductive layer 308 on dielectric layer 306); forming a second insulating layer over one or more conductors ((Gardner, Fig 2 and Fig. 7) dielectric layer 310 on conductive layer 308); forming a second magnetic layer on the second insulating layer and one or more portions of the first magnetic layer ((Gardner, Fig 2 and Fig. 7) magnetic layer 312 on dielectric layer 310 and one or more portion of magnetic layer 304); and forming one or more openings through the second magnetic layer ((Gardner, Fig 2 and Fig. 7) opening/slot 342 on second magnetic layer 312). Regarding the limitation “wherein the one or more openings are directly above the one or more conductors”, Gardner teaches, in ¶ [0064], that magnetic layer 312 may be patterned to define any suitable number of one or more slots with any suitable dimensions and orientation at any suitable one or more locations. However, Gardner does not expressly show that slot 342 is directly above conductor 308. Mizoguchi teaches, in Fig. 60, groove/opening in magnetic layer 1 which is directly above conductive/wiring layer 95. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to locate Gardner’s slot/opening 342 through magnetic layer 312 directly above conductor 308 as taught by Mizoguchi in order to improve high-frequency and current-handling performance. Re: Claim 9 (Original), Gardner and Mizoguchi disclose all the limitations of claim 8 on which this claim depends. Gardner further discloses, further comprising: removing, based on forming the second insulating layer, one or more portions of the second insulating layer (Gardner teaches, in Figs. 2, 5-7 and ¶ [0059] forming dielectric layer 310 over conductive layer 308 and then patterning and etching dielectric 310 to create recesses/vias down to magnetic layer 304 in selected regions before forming magnetic layer 312. The removal of portions of dielectric 310 occurs after and in response to forming dielectric 310, as a normal part of the process sequence for opening access to magnetic layer 304. Accordingly, this corresponds to removing, based on forming the second insulating layer, one or more portions of the second insulating layer), wherein the one or more openings are formed via the one or more portions removed from the second insulating layer (In Fig. 2 and Fig. 7 and ¶ [0059], Gardner further teaches that magnetic layer 312 is deposited over dielectric 310 such that magnetic layer 312 fills the recesses/via formed in dielectric 310 and contacts magnetic layer 304 in those regions, and then magnetic layer 312 is patterned and etched to form slots 342 (openings) in the second magnetic layer. Because the second insulating layer 310 has already been removed in the via regions, the portions of magnetic layer 312 formed in and over those recesses are directly defined by, and extended through, the removed portions of dielectric 310). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, in view of Gardner's process flow, to align at least some of the openings (slots 342) in magnetic layer 312 with the regions where dielectric 310 was previously removed (the vias), such that the openings in the second magnetic layer are formed via those removed portions of the second insulating layer- for example to us ethe existing via pattern for alignment, simplify lithography, and eddy current reduction in the inductor. Re: Claim 10 (Currently Amended), Gardner and Mizoguchi disclose all the limitations of claim 9 on which this claim depends. Gardner further discloses, wherein the one or more portions of the second insulating layer are removed via a patterned photoresist layer (¶ [0060], dielectric layer 310 is patterned by forming a patterned mask over dielectric layer 310, etching dielectric layer 310 to pattern dielectric layer 310 in accordance with the patterned mask, and removing the patterned mask. The patterned mask may comprise photoresist, formed to any suitable thickness and may be patterned using any suitable technique. Accordingly, the second insulting layer are removed via a patterned photoresist layer). Re: Claim 11 (Currently Amended), Gardner and Mizoguchi disclose all the limitations of claim 8 on which this claim depends. Gardner further teaches, wherein the one or more conductors are formed via at least one of: a chemical vapor deposition process, a physical vapor deposition process, or a plating process (Gardner, ¶ [0054], conductive layer 308 is formed by sputter depositing an aluminum-copper (AlCu) alloy, i.e., a physical vapor deposition process). Re: Claim 13 (Original), Gardner and Mizoguchi disclose all the limitations of claim 8 on which this claim depends. Gardner further discloses, wherein the second insulating layer is further formed on one or more portions of the first insulating layer (dielectric layer 310 is formed on one or more portions of dielectric layer 306). Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Gardner (US 20010030591 A1) in view of Mizoguchi (US 6593841 B1) further in view of Huang (US 20180204902 A1). Re: Claim 12 (Currently Amended), Gardner and Mizoguchi disclose all the limitations of claim 8 on which this claim depends. Gardner is silent regarding, wherein the one or more conductors are formed via a patterned photoresist layer. However, Huang teaches wherein the one or more conductors are formed via a patterned photoresist layer (Huang teaches, in ¶ [0043], forming a conductive seed layer, depositing a photoresist layer over the seed layer, patterning the photoresist to expose only those portions where the inductor coil is desired, and then electroplating copper onto the exposed seed layer through the patterned photoresist openings to form the inductor coil. After plating, the photoresist is removed and any unwanted seed metal is etched away, leaving the patterned conductive inductor coil. Accordingly, Huang therefore teaches a conductive layer (inductor coil) formed via a patterned photoresist layer (i.e., the conductor geometry is defined by the patterned photoresist)). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention starting from Gardner's method (which already uses photolithography and etching for patterning other layers such as magnetic layer 312), to implement the formation of Gardner's conductive layer 308 using the well-known photoresist-defined plating process taught by Huang in order to define the inductor conductor geometry with good thickness control and pattern fidelity. Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner (US 20010030591 A1) in view of Crawford (US 20060088971 A1) further in view of Mizoguchi (US 6593841 B1). Re: Independent Claim 14 (Currently Amended), Gardner discloses a method, comprising: forming a first magnetic layer directly on a first insulating layer (Gardner, Fig 7, forming magnetic layer 312 on dielectric layer 306), a second insulating layer (dielectric layer 310), and a second magnetic layer (magnetic layer 304), wherein the first insulating layer and the second insulating layer encapsulate one or more conductors (dielectric layer 306 and dielectric layer 310 encapsulate/surround conductive layer 308); and Regarding “forming one or more openings through the second magnetic layer, wherein the one or more openings are directly above the one or more conductors”, Gardner further teaches that magnetic layers 304 and 312 are patterned to define slots (openings) 322 and 342. But Gardner is silent regarding forming one or more openings through the second magnetic layer wherein the one or more openings are directly above the one or more conductors. However, Crawford teaches forming a first conductive layer 510 on a package substrate 500; forming a magnetic layer 530 over the first conductive layer 510; and forming sidewall trenches 540 and isolation trenches 545 by etching through the magnetic layer 530 until the first conductive layer 510 is exposed. Thus, Crawford explicitly discloses forming openings (trenches 540, 545) through a magnetic layer 530 that is over a conductive layer 510, with the etch proceeding down to the conductor -i.e., openings through the magnetic layer and over the conductor. Regarding the limitation “wherein the one or more openings are directly above the one or more conductors”, Gardner teaches, in ¶ [0064], that magnetic layer 312 may be patterned to define any suitable number of one or more slots with any suitable dimensions and orientation at any suitable one or more locations. However, Gardner does not expressly show that slot 342 is directly above conductor 308. Mizoguchi teaches, in Fig. 60, groove/opening in magnetic layer 1 which is directly above conductive/wiring layer 95. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Gardner’s magnetic-layer inductor to form openings through the magnetic layer directly above the conductor, as taught by Crawford and Mizoguchi, because Crawford teaches forming openings through magnetic material over a conductor, and Mizoguchi teaches that aligning grooves along the conductor avoids readily saturated magnetic regions and improves DC current characteristics. Re: Claim 15 (Original), Gardner, Crawford and Mizoguchi disclose all the limitations of claim 14 on which this claim depends. Gardner further teaches, further comprising: forming a photoresist layer on the first magnetic layer, wherein the one or more openings are formed via a pattern of the photoresist layer; and removing the photoresist layer (Gardner, ¶ [0065] and Fig 7, Gardner teaches forming patterned mask over magnetic layer 312, the patterned mask may comprise any suitable material, such as photoresist; etching and removing portions of the magnetic layer 312 to form slots 342 is performed using photoresist patterning and etching process, and subsequently removing the patterned mask). Re: Claim 16 (Original), Gardner, Crawford and Mizoguchi disclose all the limitations of claim 14 on which this claim depends. Gardner further teaches, wherein the one or more openings are a plurality of holes (Gardner, in Figs. 1 and 7, ¶ [0064], teaches that the magnetic layer may define any suitable number of openings (slots) with any suitable dimensions. In particular, Gardner describes magnetic layers (e.g., layers 120/312 that define multiple slots (e.g., slots 122, 124, 342) in the magnetic material; these slots are elongate openings formed by etching through the thickness of the magnetic layer. Accordingly, each such etched opening constitutes a "hole" in the magnetic layer, and Gardner explicitly contemplates a plurality of such openings). Re: Claim 17 (Original), Gardner, Crawford and Mizoguchi disclose all the limitations of claim 16 on which this claim depends. Gardner further teaches, wherein the one or more holes are a single trench (Gardner, Figs. 11 and 12, ¶ [0103], Gardner teaches, in step 1206, magnetic layer 1104 is patterned to define trenches for inductor 1100.) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the openings of claim 16 as a single trench, as in Gardner's patterned magnetic layer 1104 in order to help align the magnetic flux across each row and therefore help increase the resulting inductance of inductor. Re: Claim 18 (Original), Gardner, Crawford and Mizoguchi disclose all the limitations of claim 14 on which this claim depends. Gardner further teaches, wherein forming the one or more openings comprises: determining, based on one or more performance parameters for an inductive device, at least one of: a respective shape for each of the one or more openings, a respective size for each of the one or more openings, or a respective location in the first magnetic layer for each of the one or more openings; and forming the one or more openings based on the at least one of: the respective shape for each of the one or more openings, the respective size for each of the one or more openings, or the respective location in the first magnetic layer for each of the one or more openings (Gardner (¶ [0028], Fig.1) teaches magnetic layer 120 for one embodiment defines slots, such as slots 122 and 124 for example, to help further reduce any Eddy currents in the substrate. Magnetic layer 120 may define any suitable number of one or more slots with any suitable dimensions and orientation at any suitable one or more locations relative to conductor 110. One or more slots may be perpendicular to or at any other suitable angle relative to the flow of current through conductor 110. Gardner further explains that defining slots in magnetic layer 120 also reduces Eddy currents that can form in magnetic layer 120 and helps to increase the resonance frequency for inductor 100. Thus, Gardner teaches that the shape/orientation, size/dimensions and location of the openings (slots 122, 124, 342) in the magnetic layer are design variables that affect performance parameters of the inductive device, including eddy current reduction and resonant frequency. While Gardner does not recite in express words a separate "determining" step, it is clear from this disclosure that a person of ordinary skill in the art, implementing Gardner's structure, would select the shape, size and/or location of the slots in the first magnetic layer based on desired performance parameters of the inductor, such as reducing eddy currents and increasing resonance frequency). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the method of forming openings of the magnetic layer by first determining, based on one or more performance parameters for the inductive device, at least one of: the shape, the size and/or location of each opening in the first magnetic layer, and then to form the corresponding openings by masking and etching the first magnetic layer in accordance with that selected geometry, exactly as Gardner already teaches for slots 122, 124, 342 in order to reducing eddy currents and increasing resonance frequency. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner (US 20010030591 A1) in view of Crawford (US 20060088971 A1) further in view of Mizoguchi (US 6593841 B1) and further in view of Cappabianca (US 20190221365 A1). Re: Claim 19 (Original), Gardner, Crawford and Mizoguchi disclose all the limitations of claim 18 on which this claim depends. Gardner, Crawford and Mizoguchi are silent regarding, wherein the one or more performance parameters includes a maximum inductance for the inductive device. However, Cappabianca teaches wherein the one or more performance parameters includes a maximum inductance for the inductive device (Cappabianca, in ¶ [0058], teaches inductors in which conductors are surrounded by magnetized shell segments, and gaps or channels in the magnetic shell (e.g., gaps between shell segments) are deliberately sized and placed to control inductive performance. Cappabianca explains that the amount of inductance and the saturation current of the inductive device are design targets and that the geometry of shell gaps/channels (their width, length and placement) is adjusted during manufacturing specifically to achieve desired inductance characteristics). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention when implementing Gardner's inductor and already choosing slot shape/size/location in the first magnetic layer to affect performance (eddy currents and resonance frequency), to additionally include as performance parameters a desired/maximum inductance for the inductive device in order to achieve a high-performance inductive device. Re: Claim 20 (Original), Gardner, Crawford and Mizoguchi disclose all the limitations of claim 18 on which this claim depends. Gardner, Crawford and Mizoguchi are silent regarding, wherein the one or more performance parameters includes a saturation current for the inductive device. However, Cappabianca teaches wherein the one or more performance parameters includes a saturation current for the inductive device (Cappabianca (Fig. 2, ¶ [0035] teaches that shell gaps 205c and 205d in a magnetized shell 202 and 203) are added to control a saturation current of Inductor 200 and the gap geometry in the magnetic structure is selected to control these values). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention when implementing Gardner's inductor and already choosing slot shape/size/location in the first magnetic layer to affect performance (eddy currents and resonance frequency), to additionally include as performance parameters a desired saturation current level for the inductive device, and to adjust the slot geometry accordingly in order to allow Inductor to pass higher current than without the opening/gaps (Cappabianca, ¶ [0035]). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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Prosecution Timeline

Show 1 earlier event
Jan 13, 2026
Non-Final Rejection mailed — §103, §112
Mar 13, 2026
Interview Requested
Mar 19, 2026
Examiner Interview Summary
Apr 09, 2026
Response Filed
Jun 04, 2026
Final Rejection mailed — §103, §112
Jun 28, 2026
Interview Requested
Jul 09, 2026
Examiner Interview Summary
Jul 27, 2026
Response after Non-Final Action

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2-3
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 3m (~2m remaining)
Median Time to Grant
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