DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/447,580, application filed on 08/10/2023. Claims 1-20 are currently pending in this application.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 08/10/2023 and 09/13/2023, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being controller anticipated by Tetiker et al. (US PG Pub No. 2018/0314148).
6. With respect to independent claim 1, Tetiker teaches:
determining, by a controller, adjusted etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on a semiconductor device (see parameters that are adjusted during optimization of etch process, para 76; controller to adjust input parameters for optimizing etch process, para 140-143; see atomic layer etch, para 351; atomic layer etching, para 81; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B),
wherein the adjusted etch process parameters are determined using an analysis model trained to determine the adjusted etch process parameters based on target etch characteristics for an etch resulting from the iteration of the ALE process (see determining a set of etch process parameters using a trained model or models, para 84-85; etch process profiles used as inputs to train, optimize and improve etch profile models, para 88; see training to optimize etch process including etch process with atomic layer etching, para 80-85; see iterating over error between etch profiles from theoretical and experimental etch, Fig 4A; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B); and
providing, by the controller, the adjusted etch process parameters to the etch tool to permit the etch tool to perform the iteration of the ALE process on the semiconductor device according to the adjusted etch process parameters (improving accuracy of etch model by providing fundamental/physical input parameters to improve etch process, para 65-70; see parameters provided, parameters tuned or adjusted to optimize etch process, atomic layer etch, para 75-81; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B).
7. With respect to claim 2, Tetiker teaches:
wherein determining the adjusted etch process parameters comprises:
generating predicted etch characteristics based on trial adjusted etch process parameters (see predictive etch model parameters, based on actual substrate etch process, para 68-71; see initial trial etch, para 204; model parameters are tuned or adjusted during optimization, para 76), the predicted etch characteristics being generated by providing the trial adjusted etch process parameters as an input to the analysis model (see adjusted model parameters used as independent input to etch optimization process, para 76);
determining whether the predicted etch characteristics match the target etch characteristics (whether experimental etch profiles match to calculated etch profiles, para 129); and
determining the adjusted etch process parameters based on whether the predicted etch characteristics match the target etch characteristics (adjusting parameters/coefficients based on match or error between etch processes, para 144-150).
8. With respect to claim 3, Tetiker teaches:
wherein the iteration of the ALE process is a first iteration, and the method further comprises:
determining actual etch characteristics associated with the iteration of the ALE process after the iteration of the ALE process is performed according to the adjusted etch process parameters (see actual etch profile parameters for atomic etch processes, para 80-85); and
updating the analysis model based on the actual etch characteristics, a result of updating the analysis model being an updated analysis model, wherein the updated analysis model is to be used to determine other adjusted etch process parameters to be used by the etch tool to perform a second iteration of the ALE process (see etch model optimization process, experiments in the optimization routine for iterations until convergence, para 80-87).
9. With respect to claim 4, Tetiker teaches:
wherein the first iteration of the ALE process and the second iteration of the ALE process are a first cycle of the ALE process and a second cycle of the ALE process, respectively (see number of iterations of cycles for etch model parameter optimization, para 162-165; see repetitive cycle of collecting experimental etch profile parameters/models, comparison to target, optimization and/or adjust of parameters via iterations, para 97-101).
10. With respect to independent claim 5, Tetiker teaches:
determining, by a controller, adjusted etch process parameters to be used by an etch tool to perform an iteration of an etch process on a semiconductor device (see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B),
wherein the adjusted etch process parameters identify process parameters to be utilized for the iteration of the etch process and is based on current etch process parameters and target etch characteristics (see determining etch profile characteristics for target etch profiles, para 139; see matching target feature profile based on characteristics of etch profile target feature and adjusting process parameters, para 246-248), and
wherein the adjusted etch process parameters correspond to one or more conditions or one or more parameters of the iteration of the etch process that are modifiable, changeable, or adjustable (see modifying, adjusting or changing process parameters for etch process/profile, para 10-15); and
providing, by the controller, the adjusted etch process parameters to the etch tool to permit the etch tool to perform the iteration of the etch process on the semiconductor device according to the adjusted etch process parameters (improving accuracy of etch model by providing fundamental/physical input parameters to improve etch process, para 65-70; see parameters provided, parameters tuned or adjusted to optimize etch process, atomic layer etch, para 75-81; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B).
11. With respect to claim 6, Tetiker teaches:
wherein the adjusted etch process parameters are determined using an analysis model (see model used for optimizing etch model profile using iterative procedure, para 160-165).
12. With respect to claim 7, Tetiker teaches:
wherein the target etch characteristics include one or more of: a target etch depth after the iteration of the etch process, a target etch depth at one or more intermediate stages or one or more phases of the iteration of the etch process, a target etch area or a target etch size of the iteration of the etch process, a target etch uniformity of the iteration of the etch process, or a target for another characteristic of the etch process resulting from of the iteration of the etch process (see etch depth, para 208; see uniformity of etch across substate, para 177; size of feature etch, para 316).
13. With respect to claim 8, Tetiker teaches:
wherein the current etch process parameters include one or more current parameters or one or more current conditions of processing equipment associated with performing the etch process (set of process conditions, given process conditions, para 198; semiconductor processing equipment, para 348).
14. With respect to claim 9, Tetiker teaches:
wherein the one or more current parameters or the one or more conditions of the processing equipment comprise: a current age of an ampoule to be utilized in the iteration of the etch process, a type of a material that will be utilized in the iteration of the etch process, a phase of the material that will be utilized in the iteration of the etch process, or a length of a plumbing fixture to be used to carry a fluid or the material into an etch chamber of the etch tool (recipe phase, etch chamber, iterations for equipment processes, para 336-340).
15. With respect to claim 10, Tetiker teaches:
wherein the current etch process parameters relate to the semiconductor device to be etched in the iteration of the etch process (iteration of etch process, process phase, improving accuracy of etch model by providing fundamental/physical input parameters to improve etch process, para 65-70; see parameters provided, parameters tuned or adjusted to optimize etch process, atomic layer etch, para 75-81; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B).
16. With respect to claim 11, Tetiker teaches:
wherein the current etch process parameters comprise:
an effective exposed plain area of the semiconductor device, an exposed effective plain area crystal orientation of the semiconductor device, an exposed effective plain area roughness index of the semiconductor device, an exposed effective sidewall area of the semiconductor device, an exposed effective side wall tilt angle of the semiconductor device, or a wafer rotation or a tilt parameter associated with the semiconductor device (see sidewall, para 213; see sidewall angle, para 246).
17. With respect to claim 12, Tetiker teaches:
wherein determining the adjusted etch process parameters comprises: generating predicted etch characteristics based on trial adjusted etch process parameters (predicting etch process parameters/values based on experimental etch process profile without having to run full physics-based model every time, para 246-247).
18. With respect to claim 13, Tetiker teaches:
wherein generating the predicted etch characteristics comprises:
providing the trial adjusted etch process parameters as an input to an analysis model (improving accuracy of etch model by providing fundamental/physical input parameters to improve etch process, para 65-70; see parameters provided, parameters tuned or adjusted to optimize etch process, atomic layer etch, para 75-81; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B; see adjusted model parameters used as independent input to etch optimization process, para 76); and
receiving the predicted etch characteristics as an output of the analysis model (see predicted outputs of etch model as output of optimization analysis, para 300-304).
19. With respect to claim 14, Tetiker teaches:
wherein generating the predicted etch characteristics further comprises: determining whether the predicted etch characteristics match the target etch characteristics (adjusting parameters/coefficients based on match or error between etch processes, para 144-150).
20. With respect to claim 15, Tetiker teaches:
wherein generating the predicted etch characteristics further comprises:
modifying the trial adjusted etch process parameters to obtain modified trial adjusted etch process parameters (improving accuracy of etch model by providing fundamental/physical input parameters to improve etch process, para 65-70; see parameters provided, parameters tuned or adjusted to optimize etch process, atomic layer etch, para 75-81; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B);
providing the modified trial adjusted etch process parameters as an input to the analysis model (see adjusted model parameters used as independent input to etch optimization process, para 76; see predicted outputs of etch model as output of optimization analysis, para 300-304); and
receiving modified predicted etch characteristics as the output of the analysis model (see predicted outputs of etch model as output of optimization analysis, para 300-304).
21. With respect to independent claim 16, Tetiker teaches:
determining, by a controller and using an analysis model, a first set of adjusted etch process parameters to be used by an etch tool to perform an iteration of an etch process on one or more semiconductor devices (improving accuracy of etch model by providing fundamental/physical input parameters to improve etch process, para 65-70; see parameters provided, parameters tuned or adjusted to optimize etch process, atomic layer etch, para 75-81; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B);
providing, by the controller, the first set of adjusted etch process parameters to the etch tool to permit the etch tool to perform the iteration of the etch process on the one or more semiconductor devices according to the first set of adjusted etch process parameters (see determining a set of etch process parameters using a trained model or models, para 84-85; etch process profiles used as inputs to train, optimize and improve etch profile models, para 88; see training to optimize etch process including etch process with atomic layer etching, para 80-85; see iterating over error between etch profiles from theoretical and experimental etch, Fig 4A; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B);
determining, by the controller, actual etch characteristics associated with the iteration of the etch process (see actual measured etch profile, para 66; see actual etch profiles which result from actual etch processes and set of etch parameters, para 84; );
updating, by the controller and based on the actual etch characteristics, the analysis model to obtain an updated analysis model (see optimizing etch process parameters and etch process by using actual etch profile characteristics, para 84); and
determining, by the controller and using the updated analysis model, a second set of adjusted etch process parameters to be used by the etch tool to perform an upcoming iteration of the etch process on the one or more semiconductor devices (improving accuracy of etch model by providing fundamental/physical input parameters to improve etch process, para 65-70; see parameters provided, parameters tuned or adjusted to optimize etch process, atomic layer etch, para 75-81; see iteration of parameter set optimization process for improving etch process for semiconductor device, Fig 4A, 4B).
22. With respect to claim 17, Tetiker teaches:
wherein the actual etch characteristics are determined to include characteristics of the etch process as actually performed by the etch tool according to the adjusted etch process parameters (experimental etch profile parameters adjusted and etch profiles created, then compared to target etch model and their parameters, para 96-101).
23. With respect to claim 18, Tetiker teaches:
wherein determining the actual etch characteristics comprises: receiving the actual etch characteristics (actual etch profile characteristics result from actual etch processes, para 84-85).
24. With respect to claim 19, Tetiker teaches:
wherein updating the analysis model comprises: training the analysis model based on the actual etch characteristics and the first set of adjusted etch process parameters (train model for optimization of various experiments, including actual etch process parameters optimized using training model, para 83-87).
25. With respect to claim 20, Tetiker teaches:
wherein the first set of adjusted etch process parameters are determined to be used by the etch tool to perform the iteration of the etch process on a first semiconductor device of the one or more semiconductor devices (see etch model optimization process, experiments in the optimization routine for iterations until convergence, para 80-87), and
wherein the second set of adjusted etch process parameters are determined to be used by the etch tool to perform the upcoming iteration of the etch process on a second semiconductor device of the one or more semiconductor devices (see optimization for parameters for a number of upcoming/subsequent iterations, para 164-166).
Conclusion
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
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