DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mizushima et al (US 6163042 A, hereafter Mizushima) in view of Kang (US 20150249111 A1, hereafter Kang).
Regarding claim 10, Mizushima teaches: A method, comprising: forming a first core region (Mizushima 1, Col 3, Lines 22-29) over a substrate (Mizushima 20)(Mizushima fig 2, Col 3, Lines 22-29);
forming a first ring region (Mizushima 2a-2d) over the substrate, and surrounding the first core region (Mizushima fig 2); and
forming at least one first input/output (IO) pattern (Mizushima 25, Col 3, Lines 30-32) in the first ring region (Mizushima fig 2) to electrically couple the first core region to external circuitry outside the first core region (Mizushima Col 2, Lines 32-44, IO unit cells electrically connected between bonding pads 4 and core area 1),
wherein the at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction (Mizushima fig 2, Col 3, Lines 30-32).
Mizushima does not explicitly teach: the first core region comprising: at least one active region elongated along a first direction; and
at least one gate region extending across the at least one active region and elongated along a second direction transverse to the first direction.
Kang, in the same field of endeavor of semiconductor device manufacturing, teaches: at least one active region (Kang 111, ¶0044, 0050) elongated along a first direction (Kang fig 3, ¶0044, 0050); and
at least one gate region (Kang 122, ¶0047, 0052) extending across the at least one active region and elongated along a second direction transverse to the first direction (Kang fig 3, ¶0052).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Mizushima to include the active region and gate regions, as taught by Kang, as the predetermined circuits of Mizushima to the core region, in order to provide the core region with functional transistors with reduced switching area, thereby reducing switching resistance and/or improving device characteristics or simplifying manufacturing (Kang ¶0095).
Regarding claim 11, Mizushima in view of Kang teaches: The method of claim 10, further comprising:
forming at least one second IO pattern in the first ring region to electrically couple the first core region to external circuitry outside the first core region,
wherein the at least one second IO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction,
the at least one first IO pattern is formed in a first metal layer, and the at least one second IO pattern is formed in a second metal layer different from the first metal layer.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Guo et al (US 20170141029 A1, hereafter Guo) in view of Teig et al (US 20050240893 A1, hereafter Teig).
Regarding claim 18, Guo teaches: A method (Guo ¶0024-0025), comprising:
forming a circuit region over a substrate (Guo 202, ¶0041, fig 13A), the circuit region corresponding to an intellectual property (IP) block (Guo “standard cells” 1-7, ¶0039, 0043, fig 13B, under a broadest reasonable interpretation (BRI) of “IP block”, an IP block is nothing more than a cell or combination of cells developed by and IC designer, spec ¶0022), the circuit region comprising:
a boundary (Guo fig 12A, 12B, 13B, ¶0039, the space between adjacent power rails defines the placement boundary of each standard cell row; standard ells are placed in the bounded space between power rails),
an elongated active region inside the boundary (Guo ¶0043, at least FINFET contain elongated active regions extending along a single direction within a cell), and
a plurality of input/output (IO) patterns (Guo 204, 208) inside the boundary (Guo ¶0041, 0043, fig 13A, 13B);
forming a first via (Guo 206) over and electrically coupled to a first IO pattern among the plurality of IO patterns of the circuit region (Guo ¶0041, fig 13A); and
forming, in a first metal layer over the first via, an access pattern (Guo 208) which extends from outside the boundary of the circuit region to inside the boundary to overlap and electrically contact the first via (Guo fig 13 A, 13B, ¶0041, 208 in M0 layer extends along the X direction across multiple standard call boundaries, from outside one cell boundary to inside, overlapping and contacting via 206).
Guo does not explicitly teach: wherein the access pattern and the first IO pattern form an acute angle therebetween.
Teig, in the same field of endeavor of semiconductor device manufacturing, teaches: adjusting an angle of an access pattern with respect to a different layer (Teig fig 4a, fig 22, ¶0070-0076, 0082-0083, 0134-0137).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the angle of the access pattern with respect to the first IO pattern of Guo, such that it forms an acute angle, in order to reduce total wire length and/or improve routing efficiency (Teig ¶0069, 0078, 0082), thereby providing more flexible routing options across layers.
Allowable Subject Matter
Claims 1-9 are allowed.
Claims 11-17, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein the at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction, and
the at least one second IO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction. (Applicant fig 2, ¶0032-0035).
Rostoker et al (US 6407434 B1, hereafter Rostoker) teaches: A method, comprising: forming a circuit region (Rostoker 34, 96) over a substrate (Rostoker 32, 95, fig 36), the circuit region comprising:
at least one active region (Rostoker 36) extending along a first direction (Rostoker fig 36); and
at least one gate region (Rostoker 48) extending across the at least one active region and along a second direction transverse to the first direction (Rostoker fig 36, 36 extends at least horizontally with regard to fig 36, 48 extends at least vertically with respect to fig 36);
forming, in a first metal layer (Rostoker 117, Col 14, Lines 53-63, fig 4), at least one first input/output (IO) pattern (Rostoker 122, Col 15 Lines 1-14, fig 4, at least capable of); and
forming, in a second metal layer different from the first metal layer (Rostoker 118, Col 14, Lines 53-63, fig 4), at least one second IO (Rostoker 128, Col 15 Lines 1-14, fig 4, at least capable of);
where in the first and second IO patterns extend along different directions (Rostoker fig 4).
Kang et al (US 20150249111 A1, hereafter Kang) teaches: forming a circuit region (Kang LYSW/MAT, ¶0035, 0043) over a substrate (Kang 100, ¶0049)(Kang fig 4), the circuit region comprising:
at least one active region (Kang 111, ¶0044) extending along a first direction (Kang fig 3); and
at least one gate region (Kang 122, ¶0047) extending across the at least one active region and along a second direction transverse to the first direction (Kang fig 3, 4);
forming, in a first metal layer (Kang layer above 140, at least contains conductors 152, 162), at least one first input/output (IO) pattern (Kang 152, under a BRI of “input/output pattern”) to electrically couple the circuit region to external circuitry outside the circuit region (Kang fig 3, 4); and
forming, at least one second IO pattern (Kang 162) to electrically couple the circuit region to external circuitry outside the circuit region (Kang fig 3, 4).
Teig et al (US 20050240893 A1, hereafter Teig) teaches: forming, in a first metal layer (Teig L3, ¶0073, 0076), at least one first input/output (IO) pattern (Teig 140, ¶0076, fig 4a, under a BRI of “input/output pattern”); and
forming, in a second metal layer (Teig L4, ¶0073, 0076) different from the first metal layer (Teig fig 4a), at least one second IO pattern (Teig 140, ¶0076, fig 4a, under a BRI of “input/output pattern”);
Andreev et al (US 20140103959 A1, hereafter Andreev) teaches: forming, in a first metal layer (Andreev M6-M8, ¶0079, 0097), at least one first input/output (IO) pattern (Andreev 130, 170) to electrically couple a circuit region (Andreev 115, ¶0073, fig 1) to external circuitry (Andreev MGIO 140, ¶0075) outside the circuit region (Andreev ¶0073, 0104); and
forming, in a second metal layer (Andreev M2-M4, ¶0100) different from the first metal layer, at least one second IO pattern (Andreev 180) to electrically couple the circuit region to external circuitry outside the circuit region (Andreev ¶0073, 0104).
Rostoker in view of Kang, Teig, and Andreev, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Rostoker, Kang, Teig, Andreev, Mizushima or any other prior arts of record so that all of limitations of claim 1 as a whole can be met.
Regarding claims 2-9, the dependent claims are allowed for their dependency to claim 1.
Regarding claim 11, it is allowable, notwithstanding above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
forming at least one second IO pattern in the first ring region to electrically couple the first core region to external circuitry outside the first core region,
wherein the at least one second IO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction,
the at least one first IO pattern is formed in a first metal layer, and
the at least one second IO pattern is formed in a second metal layer different from the first metal layer.
Mizushima in view of Kang, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Rostoker, Kang, Teig, Andreev, Mizushima, Guo or any other prior arts of record so that all of limitations of claim 11 as a whole can be met.
Regarding claim 12, the dependent claim is allowable for its dependency to claim 11.
Regarding claim 13, it is allowable, notwithstanding above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
forming a second core region over the substrate;
forming a second ring region over the substrate, and surrounding the second core region; and
forming at least one second IO pattern in the second ring region to electrically couple the second core region to external circuitry outside the second core region.
Teig et al (US 20050240893 A1, hereafter Teig) teaches: at least one second IO pattern (Teig 140, ¶0076, fig 4a, under a BRI of “input/output pattern”) extends along a fourth direction oblique to both a first direction and a second direction, the fourth direction transverse to a third direction (Teig fig 4a, ¶0072-0076),
at least one first IO pattern (Teig 140, ¶0076, fig 4a) is formed in a first metal layer (Teig L3, ¶0073, 0076),
the at least one second IO pattern is formed in a second metal layer (Teig L4, ¶0073, 0076) different from the first metal layer (Teig fig 4a, ¶0072-0076), and
the at least one first IO pattern overlaps the at least one second IO pattern (Teig fig 4a).
Guo et al (US 20170141029 A1, hereafter Guo: forming at least one via (Guo 206) electrically coupling at least one first IO pattern (Guo 204) to at least one second IO pattern (Guo 208)(Guo ¶0041, 0043, fig 13A, 13B).
Mizushima in view of Kang, Teig and Guo, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Rostoker, Kang, Teig, Andreev, Mizushima, Guo or any other prior arts of record so that all of limitations of claim 13 as a whole can be met.
Regarding claim 14, the dependent claim is allowable for its dependency to claim 13.
Regarding claim 15, it is allowable, notwithstanding above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
forming a second core region over the substrate;
forming a second ring region over the substrate, and surrounding the second core region; and
forming at least one second IO pattern in the second ring region to electrically couple the second core region to external circuitry outside the second core region,
wherein the at least one second IO pattern extends along the third direction and is formed in a same metal layer as the at least one first IO pattern, and
the method further comprises forming, in the metal layer, at least one extension pattern extending along the third direction and contiguous to both the at least one first IO pattern and the at least one second IO pattern to electrically couple the first core region to the second core region.
Mizushima in view of Kang, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Rostoker, Kang, Teig, Andreev, Mizushima, Guo or any other prior arts of record so that all of limitations of claim 15 as a whole can be met.
Regarding claim 16, it is allowable, notwithstanding above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
forming a second core region over the substrate;
forming a second ring region over the substrate, and surrounding the second core region; and
forming at least one second IO pattern in the second ring region to electrically couple the second core region to external circuitry outside the second core region,
wherein the at least one second IO pattern extends along the third direction and is formed in a same first metal layer as the at least one first IO pattern,
the fourth direction is oblique to both the first direction and the second direction, and is transverse to the third direction, and
forming a second via electrically coupling the access pattern to the at least one second IO pattern.
Teig et al (US 20050240893 A1, hereafter Teig) teaches: in a second metal layer (Teig L3, ¶0073, 0076) different from the first metal layer (Teig L2, ¶0073, 0076), at least one access pattern (Teig 140, ¶0076, fig 4a, under a BRI of “access pattern”),
the at least one access pattern extends along a fourth direction to overlap both an at least one first IO pattern and an at least one second IO pattern (Teig 140, ¶0076, fig 4a, under a BRI of “input/output pattern”).
Guo et al (US 20170141029 A1, hereafter Guo: forming at least one via (Guo 206) electrically coupling access pattern (Guo 204) to at least one first IO pattern (Guo 208)(Guo ¶0041, 0043, fig 13A, 13B).
Mizushima in view of Kang, Teig and Guo, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Rostoker, Kang, Teig, Andreev, Mizushima, Guo or any other prior arts of record so that all of limitations of claim 16 as a whole can be met.
Regarding claim 17, it is allowable, notwithstanding above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
forming a second core region over a further substrate;
forming a second ring region over the further substrate, and surrounding the second core region;
forming at least one second IO pattern in the second ring region to electrically couple the second core region to external circuitry outside the second core region; and
stacking the substrate and the further substrate one on top another so that the first core region and the second core region are stacked one on top another, and the at least one first IO pattern overlaps the at least one second IO pattern.
Teig et al (US 20050240893 A1, hereafter Teig) teaches: at least one second IO pattern (Teig 140, ¶0076, fig 4a, under a BRI of “input/output pattern”) extends along a fourth direction oblique to both a first direction and a second direction, the fourth direction transverse to a third direction (Teig fig 4a, ¶0072-0076),
at least one first IO pattern (Teig 140, ¶0076, fig 4a) is formed in a first metal layer (Teig L3, ¶0073, 0076),
the at least one second IO pattern is formed in a second metal layer (Teig L4, ¶0073, 0076) different from the first metal layer (Teig fig 4a, ¶0072-0076).
Guo et al (US 20170141029 A1, hereafter Guo) teaches: forming at least one via (Guo 206) electrically coupling at least one first IO pattern (Guo 204) to at least one second IO pattern (Guo 208)(Guo ¶0041, 0043, fig 13A, 13B).
Mizushima in view of Kang ,Teig and Guo, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Rostoker, Kang, Teig, Andreev, Mizushima, Guo or any other prior arts of record so that all of limitations of claim 17 as a whole can be met.
Regarding claim 19, it is allowable, notwithstanding above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
before said forming the first via, forming, in a second metal layer over the substrate, a further pattern in the second metal layer and outside the boundary of the circuit region;
forming a second via over and electrically coupled to the further pattern; and
forming, in a third metal layer over the second via,
the plurality of IO patterns parallel to each other, and
an extension pattern which is contiguous to a second IO pattern among the plurality of IO patterns, and extends from inside the boundary of the circuit region to outside the boundary where the extension pattern overlaps and is electrically coupled to the second via,
wherein the extension pattern extends transversely to and overlaps the further pattern in the second metal layer, and
the access pattern and the further pattern form an acute angle therebetween.
Guo in view of Teig, in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Rostoker, Kang, Teig, Andreev, Mizushima, Guo or any other prior arts of record so that all of limitations of claim 19 as a whole can be met.
Regarding claim 20, the dependent claim is allowable for its dependency to claim 19.
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818