DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 7/13/2026 is acknowledged. Claims 1, 5-8, 10, 17 have been amended.
Response to Arguments
Applicant's arguments filed 7/13/2026 have been fully considered but they are not persuasive.
Regarding claim 1, the Applicant contends that the claim amendment have overcome the prior art of record. The Applicant mainly argued that Noh does not teach all the limitations of the above claims, in particular, the limitations “upper surface of the first/second portion of the substrate defines a first/second plane”. The Examiner respectfully disagree.
As written, the claim language does not place any restriction on what constitutes a substrate, or what material it is made of, or whether it is entirely made of a single material or can include multiple materials,… Thus, the definition of the substrate can be defined very broadly to be a multi-layered structure that includes all elements beneath the gate structure that are connected together. This is a reasonable definition in the art. For example, a SOI substrate is a well-known substrate in semiconductor industry that includes a base substrate, a buried oxide layer, and a silicon-on-insulator layer. With this definition in mind, in the first portion (region II in Figs. 2-3 of Noh) of the substrate, the substrate can be defined to include the base substrate 100, the base fin 104, sacrificial line 114, and the semiconductor line 124; and in the second portion (region I in Figs. 2-3 of Noh) of the substrate, the substrate can be defined to include the base substrate 100, the base fin 102. This definition had been used in the previous rejections of the claims 1, 10 and 17 based on the reference Noh; and is stated explicitly here for the purpose of clarification. The term “upper surface of the first/second portion of the substrate” are then defined as stated in the body of the rejection below.
Regarding claims 10 and 17, the Applicant contends that Noh does not teach the limitation “an isolation structure between the first plurality of nanosheets and the second plurality of nanosheets in the second direction. The Applicant argues that the isolation structure 162/164 are below level of the nanosheets and at the level of the nanosheets, only gate structure is between the first and second pluralities of nanosheets. The Examiner respectfully disagrees.
The claim language specifically states that the “isolation structure between the first plurality of nanosheets and the second plurality of nanosheets in the second direction”. This “second direction” is the direction of the width of the nanosheets as stated in the claim language of claims 10 and 17, so it is a lateral direction, and is parallel to the major plane of substrate. There is nothing in the claim language regards the level of nanosheets and the relative positions of the nanosheets to the isolation structure. All the claim language requires is that the isolation structure be positioned in the second direction between the first plurality of nanosheets and the second plurality of nanosheets. According to Fig. 2 of Noh, this is the exact positions of the isolation structure 162/164. If the Applicant wants to claim the levels of nanosheets relative to that of the isolation structure, such language needs to be written explicitly in the claim to be considered.
Other arguments of the above claims and their dependent claims revolve mainly around the above arguments. The response is the same and will not be repeated here.
The rejections of claims 1, 10 and 17 are therefore maintained. The rejections of other claims are updated accordingly.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, 10-13, 15, 17-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Noh et al. (US 10937787 B1).
Regarding claim 1, Noh teaches a semiconductor device (device in Figs. 1-3 of Noh), comprising:
a substrate (100 in Fig. 2 of Noh);
a first transistor (the nanowire transistor over region II) over a first portion (region II) of the substrate, wherein the first transistor comprises a first nanosheet stack of N nanosheets (stack of nanosheets 128); and
a second transistor (the nanowire transistor over region I) over a second portion (region I) of the substrate, wherein the second transistor comprises a second nanosheet stack of M nanosheets (stack of nanosheets 126), wherein N is different from M (as shown in Figs. 2-3 of Noh),
an upper surface (upper surface of 124 that is contacted by gate structure 364) of the first portion of the substrate defines a first plane (the plane containing the top surface of 124); and
an upper surface (upper surface of base fin 102) of the second portion of the substrate defines a second plane (the plane containing the top surface of 102), wherein a first vertical offset (difference in heights of the first plane and second plane) exists between the first plane and the second plane.
Regarding claim 2, Noh teaches all limitations of the semiconductor device of claim 1, and further comprising an isolation region (isolation pattern 162 in Fig. 2 of Noh) separating the first transistor and the second transistor.
Regarding claim 3, Noh teaches all limitations of the semiconductor device of claim 2, and also teaches wherein the isolation region further comprises a dielectric structure (the dielectric material 160 in Fig. 8 of Noh) extending into the substrate (100) between the first and second transistors.
Regarding claim 4, Noh teaches all limitations of the semiconductor device of claim 1, and also teaches wherein both N and M are integers and each have a value of from 1 to 5 (as shown in Fig. 2 of Noh).
Regarding claim 5, Noh teaches all limitations of the semiconductor device of claim 1, and also teaches wherein a distance between adjacent nanosheets of N nanosheets is equal to a distance between adjacent nanosheets of the M nanosheets (as shown in Fig. 2 of Noh).
Regarding claim 7, Noh teaches all limitations of the semiconductor device of claim 1, and also teaches wherein the first vertical offset distance is at most twice a thickness of a single nanosheet (as shown in Fig. 5 of Noh, the thickness of layers 110 and 120 are the same, so the vertical offset is about twice the thickness of single nanosheet).
Regarding claim 10, Noh teaches a semiconductor device (device in Figs. 1-3 of Noh) comprising:
a first transistor (nanowire transistor over region II) over a substrate (100), wherein the first transistor comprises a first plurality of nanosheets (nanowires 128) separated from one another in a first direction (vertical direction), the first transistor has a first sheet width (width of the nanowire 128) in a second direction (lateral direction) perpendicular to the first direction, and the first transistor has a first power efficiency (power efficiency of the first transistor);
a second transistor (nanowire transistor over region II) over the substrate, wherein the second transistor comprises a second plurality of nanosheets (nanowires 126), the second transistor has the first sheet width (width of nanowires 126), and the second transistor has a second power efficiency different from the first power efficiency (since power efficiency is a function of number of nanowires and its geometry, the first and second transistors have different power efficiency because they have different number of nanowires); and
an isolation structure (162) between the first plurality of nanosheets and the second plurality of nanosheets in the second direction.
Regarding claim 11, Noh teaches all limitations of the semiconductor device of claim 10, and also teaches wherein the first transistor has a first maximum frequency, the second transistor has a second maximum frequency, and the first maximum frequency is different from the second maximum frequency (as disclosed in [0030] of the specification of the instant application, the maximum frequency and power efficiency of the nanowire device is a function of number of nanowires, and width. Since Noh’s device also disclose the nanowires, the definitions of maximum frequency must be the same. The number of nanowires of Noh’s first and second transistors are different while their widths the same, so the respective maximum frequencies must be different).
Regarding claim 12, Noh teaches all limitations of the semiconductor device of claim 10, and also teaches wherein a thickness of the substrate below the first transistor is different from a thickness of the substrate below the second transistor (thickness of substrate is measured from the bottom surface of the substrate 100 to the bottom surface of the bottommost portion of gate 362 in Fig. 3. As such, the thickness substrate below the first transistor is different than that of the second transistor).
Regarding claim 13, Noh teaches all limitations of the semiconductor device of claim 10, and also teaches wherein a height of the first plurality of nanosheets is different from a height of the second plurality of nanosheets (the height is defined as the distance from the top surface of the substrate to the top of the gate. The top surface of the substrate is identified as the bottom of the bottommost portion of gate 362 in Fig. 3 of Noh. Thus, as can be seen in Fig. 3 of Noh, the first and second transistors have different height).
Regarding claim 15, Noh teaches all limitations of the semiconductor device of claim 10, and also teaches wherein a top-most surface of the first transistor is offset from a top-most surface of the second transistor in a direction perpendicular to a top surface of the substrate by equal to or less than about 10 nanometers (nm) (the two transistors have the same height so the offset is zero. Zero is less than 10nm).
Regarding claim 17, Noh a semiconductor device (device in Figs. 1-3 of Noh) comprising:
a first transistor (the nanowire transistor over region II) over a substrate (100), wherein the first transistor comprises a first plurality of nanosheets (128) separated from one another in a first direction (vertical direction), and the first plurality of nanosheets has a first height (height of the stack of nanosheets 128 as measured from the surface 322 of the layer 124 in Fig. 2 of Noh to the top surface of the topmost layer 128 in Fig. 2);
a second transistor (the nanowire transistor over region II) over the substrate, wherein the second transistor comprises a second plurality of nanosheets (126), the second plurality of nanosheets has a second height (height of the stack of nanosheets 126 as measured from the surface 322 of the base 102 in Fig. 2 of Noh to the top surface of the topmost layer 126 in Fig. 2), and the second height is different from the first height (as shown in Fig. 2 of Noh); and
an isolation structure (164/162) between the first plurality of nanosheets and the second plurality of nanosheets in a second direction (lateral direction in Fig. 2) perpendicular to the first direction.
Regarding claim 18, Noh teaches all limitations of the semiconductor device of claim 17, and also teaches wherein a top-most surface of the first transistor is offset from a top-most surface of the second transistor in a direction perpendicular to a top surface of the substrate by equal to or less than about 10 nanometers (nm) (the two transistors have the same height so the offset is zero. Zero is less than 10nm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Noh, as applied to claim 1 above, and further in view of Balakrishnan et al. (US 10038053 B2).
Regarding claim 6, Noh teaches all limitations of the semiconductor device of claim 1, and also teaches wherein N and M satisfy a relationship N < M (2 < 3).
But Noh does not teach that wherein the first vertical offset is within a range of 10-60 nm.
Balakrishnan teaches a stack of alternating semiconductor layers (16,18 in Fig. 1 of Balakrishnan) that is to be used to make nanowire transistors. These layers have the same thickness of about 8nm to 10nm (see column 5 lines 15-19 of Balakrishnan).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the layers 114 and 124 of Noh of the same thickness in the range of 8nm to 10nm, as disclosed by Balakrishnan, in order to simplify the manufacturing process.
As incorporated, the first vertical offset is within the range of 10 to 60nm.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Noh, as applied to claim 1 above, and further in view of Lee et al. (US 2017/0162583 A1).
Regarding claim 8, Noh teaches all limitations of the semiconductor device of claim 1, but does not teach the semiconductor device further comprising: a third transistor over a third portion of the substrate, wherein the third transistor comprises a third nanosheet stack of O nanosheets, wherein O is different from each of N and M.
Lee teaches a device with different nanowire transistors formed on three different regions (see Fig. 9 of Lee). The number of nanowire channels is different for each device (see Fig. 9 of Lee).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a third transistor over a third portion of the substrate, wherein the third transistor comprises a third nanosheet stack of O nanosheets, wherein O is different from each of N and M, in situation where transistors with different numbers of nanowire channels are needed such as the situations in Fig. 9 of Lee.
Regarding claim 9, Noh teaches all limitations of the semiconductor device of claim 8, and also teaches wherein an upper surface of the third portion of the substrate defines a third plane, wherein a second vertical offset distance exists between the second plane and the third plane (as combined in claim 8 above, second and third transistors would have different vertical offsets from the substrate).
Claims 14 are rejected under 35 U.S.C. 103 as being unpatentable over Noh, as applied to claim 10 above, and further in view of Glass et al. (US 2013/0161756 A1).
Regarding claim 14, Noh teaches all limitations of the semiconductor device of claim 10, but does not teach wherein each of the first plurality of nanosheets comprises silicon germanium and silicon (the phrase “silicon germanium and silicon” is interpreted as silicon germanium. Silicon is treated as redundant).
Glass discloses a nanowire device in which SiGe is used as nanowire channel layer and the silicon is used as sacrificial layer (see [0002] and [0012] of Glass).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used SiGe as nanowire channel layers in order to improve mobility of the carriers.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Noh, as applied to claim 10 above, and further in view of Chang et al. (US 2011/0031473 A1).
Regarding claim 16, Noh teaches all limitations of the semiconductor device of claim 10, but does not teach wherein the first width ranges from about 15 nm to about 70 nm.
Chang teaches a nanowire device where the nanowire width ranges from 5nm to 40nm (see [0094] of Chang).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the first width ranges from about 5nm to 40nm, as disclosed by Chang, since this is a known working range for nanowire widths.
As incorporated, since the claimed ranges of 15 to 70 nm "overlap or lie inside ranges disclosed by the prior art", a prima facie case of obviousness exists. Therefore, it would have been obvious at the effective filing date of the claimed invention to a person having ordinary skill in the art to have made the first width to be in a range of about 15 to 70 nanometers. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Noh, as applied to claim 17 above, and further in view of Xiao (US 2020/0105762 A1).
Regarding claim 19, Noh teaches all limitations of the semiconductor device of claim 17, but does not teach wherein each of the first plurality of nanosheets has a first width, each of the second plurality of nanosheets has a second width, and the second width is different from the first width.
Xiao teaches two nanowire transistors (Figs. 1a-1b of Xiao) wherein each of the nanowire of the first transistor has a different width than that of each of the second transistor (see Fig. 1b of Xiao).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the second width different from the first width in applications where the two transistors have different widths.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Noh, as applied to claim 17 above, and further in view of Kang et al. (US 2020/0091349 A1).
Regarding claim 20, Noh teaches all limitations of the semiconductor device of claim 17, but does not teach wherein a first sidewall of the first plurality of nanosheets is aligned with a first sidewall of the second plurality of nanosheets in a first direction parallel to a top surface of the substrate, and a second sidewall of the first plurality of nanosheets is offset from a second sidewall of the second plurality of nanosheets in a second direction parallel to the top surface of the substrate.
Kang teaches a layout of nanowire transistors where the gates (G1-G3 in Fig. 7 of Kang) are positioned parallel to each other and the nanowires have different widths (WX1-WX3 in Fig. 7 of Kang), wherein a first sidewall (upper sidewall of 111) of the first plurality of nanosheets (111) is aligned with a first sidewall (upper sidewall of 111) of the second plurality of nanosheets (113) in a first direction (x-direction) parallel to a top surface of the substrate, and a second sidewall (bottom sidewall of 111) of the first plurality of nanosheets is offset from a second sidewall (lower sidewall of 113) of the second plurality of nanosheets (113) in a second direction (y-direction) parallel to the top surface of the substrate.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used the layout of Kang’s for ease of scaling up (as discussed in [0004] of Kang).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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