DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 09/08/2026 Amendment.
Claims 1-5, 9-15 and 19-26 are pending and examined. Claims 6-8 and 16-18 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 19-26 are rejected under 35 U.S.C. 103 as being unpatentable over US 5,592,001 to Asano (hereafter Asano) in view of US 11, 217,595 to Li et al. (hereafter Li) in view of US 9,917,090 to Cheng (hereafter Cheng).
Regarding dependent claim 1, Asano teaches a memory bit cell, comprising:
a first memory cell including a first floating gate transistor and a first selection transistor electrically connected in series, wherein a source or drain terminal of the first selection transistor is connected to a bit line (FIG. 10: comprising floating gate transistor 2A and select transistor 1A, wherein one terminal of select transistor 1A is connected to data line DL);
a second memory cell including a second floating gate transistor and a second selection transistor electrically connected in series, wherein a source or drain terminal of the second selection transistor is connected to the bit line (FIG. 10: comprising floating gate transistor 2B and select transistor 1B, wherein one terminal of select transistor 1B is connected to the data line DL);
a first word line connected to gate terminals of the first and second floating gate transistors (FIG. 10: word line CG connected to floating gate transistors 2A and 2B); and
a second word line connected to gate terminals of the first and second selection transistors (FIG. 10: word line WL connected to select transistors 1A and 1B);
wherein a portion of the bit line connecting the first selection transistor to the second selection transistor is disposed parallel to the first word line and the second word line (see annotated FIGS. 8 and 10 of Asano below);
;
wherein the first and second floating gate transistors are programmed simultaneously by a single word line program signal applied to the first word line (see FIG. 10 and TABLE 1, either WRITE(“0”) or WRITE (“1”), VWL is at H voltage), such that the first floating gate transistor and the second floating gate transistor are concurrently programmed during a single programming operation (FIG. 10: because floating gate transistors 2A and 2B are both applied with same voltages at gates, drains and sources); and
wherein, during a read operation, the first selection transistor and the second selection transistor are turned on concurrently (see FIG. 10 and Readout of TABLE 1, when the data “0” is stored, the threshold values of floating gate transistors 2A and 2B equal to -5V. With VWL of 5V and VCG of 0V, transistors 1A, 1B, 2A and 2B would turn on concurrently, see 8:16-25) such that read currents from the first floating gate transistor and the second floating gate transistor flow in parallel onto the bit line such that the bit line senses an electrically summed read current (FIG. 10: because floating gate transistors 2A and 2B are both applied with same voltages at gates, drains and sources).
Annotated FIGS. 8 and 10 of Asano
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Asano teaches first and second floating gate transistors for storing data instead of antifuse transistors.
Li teaches an antifuse bit cell structure comprising first and second antifuse memory cells, each memory cell comprises a [capacitor-connected] antifuse transistor (FIG. 2A: antifuse capacitor 220 comprises structure of a transistor with gate 225, doped region drain/source 221 and doped region source/drain 222) and a select transistor (FIG 2A: select transistor 210); wherein a first thickness of gate dielectric layers of the first and second antifuse transistors is less than a second thickness of gate dielectric layers of the first and second selection transistors (FIG. 2a: gate dielectric 226 of capacitor-connected antifuse transistor 220 is less than gate dielectric 216 of select transistor 210), and wherein each of the first and second antifuse transistors comprises a metal-oxide-semiconductor structure having a gate electrode disposed over a channel region defined between source and drain diffusion regions on or over a semiconductor substrate (see annotated FIG. 1A below). However, the program method of antifuse of Li is different from recited limitations.
Cheng teaches an antifuse cell comprising antifuse transistor, the antifuse transistor is programmed by application of a word line program signal to the word line causes dielectric breakdown of the gate dielectric layers of the antifuse transistor to form permanent electrically conductive paths between the corresponding gate electrodes and channel regions (FIG. 3: applying program voltage to WLP, see 8:4-16).
Since Asano, Li and Cheng are from the same field of endeavor, the purpose disclosed by Asano and Cheng would have been recognized in the pertinent art of Li.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
apply the arrangement of word line and bit line of floating gate memory bit cell structure of Asano to the antifuse bit cell structure of Li because both memory cells have the same self-redundancy function (see Asano, 2:37-56 and Li, 7:2-11);
applying the programming method of Cheng to the antifuse transistor of Li because they are functional equivalent.
Annotated FIG. 1A of Li
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Regarding dependent claim 2, Asano teaches wherein the first floating gate transistor is selectable between a first state or a second state in response to the word line program signal, and wherein the second floating gate transistor is selectable between the first state or the second state in response to the word line program signal (FIG. 10: with CG line turns on, see 7:44-67).
Regarding dependent claim 3, Asano teaches wherein the first selection transistor is configured to provide access to the first floating gate transistor in response to the word line read signal, and wherein the second selection transistor is configured to provide access to the second floating gate transistor in response to the word line read signal (FIG. 10: with WL line turns on).
Regarding dependent claim 4, Li teaches wherein the first state is a low resistance state and the second state is a high resistance state (see 1:20-35).
Regarding dependent claim 5, Li teaches wherein each of the first and second antifuse transistors has a permanent electrically conductive path associated with the first state (because that is the characteristics of antifuses).
Regarding dependent claim 9, Li teaches wherein the first antifuse transistor and the first selection transistor include a first active area on or over a substrate extending in a first direction (see FIG. 2A), and wherein the second antifuse transistor and the second selection transistor include a second active area on or over the substrate extending in the first direction (because FIG. 3 depicts a parallel connection between first and second antifuse memory cells).
Asano teaches similar features, wherein the first floating gate transistor and the first selection transistor include a first active area on or over a substrate extending in a first direction (see FIG. 9), and wherein the second floating gate transistor and the second selection transistor include a second active area on or over the substrate extending in the first direction (because FIG. 10 depicts a parallel connection between first and second memory cells).
Regarding dependent claim 10, Asano teaches wherein the first word line includes a first conductive gate strip extending over the first active area and the second active area in a second direction crossing the first direction, the first conductive gate strip connected to gates of the first and second floating gate transistors (FIG. 8: conductive strip 97), and wherein the second word line includes a second conductive gate strip extending over the first active area and the second active area in the second direction connected to gates of the first and second selection transistors (FIG. 8: conductive strip 99).
Regarding dependent claim 11, Asano teaches comprising a conductive track extending over the first active area and the second active area in the second direction connected to a drain or a source of the first selection transistor and to a drain or a source of the second selection transistors (FIG. 8: conductive tract 100).
Regarding independent claim 19, Asano teaches a method, comprising:
applying a program single signal to a first word line electrically connected to gate terminals of first and second floating gate transistors to select a first state or a second state of the first and second floating gate transistors (FIG. 10: applying 0V to CG during write operation as shown in TABLE 1), and program the first and second floating gate transistors simultaneously, such that dielectric breakdown occurs concurrently in gate dielectric layers of the first and second floating gate transistors during a single programming operation (FIG. 10: because floating gate transistors 2A and 2B are both applied with same voltages at gates, drains and sources),
after programmed (because the memory cell is subject to read after the data has been stored), applying a read signal to a second word line electrically connected to gate terminals of first and second selection transistors to turn on first and second selection transistors concurrently (see FIG. 10 and Readout of TABLE 1, when the data “0” is stored, the threshold values of floating gate transistors 2A and 2B equal to -5V. With VWL of 5V and VCG of 0V, transistors 1A, 1B, 2A and 2B would turn on concurrently, see 8:16-25), the first and second selection transistors connected in series with a respective one of the first and second floating gate transistors (see FIG. 10); and
during a read operation (see Readout of TABLE 1), conducting first and second read currents through the first and second floating gate transistors between respective source and drain terminals through respective channel regions as storage devices, such that the first and second read currents flow in parallel onto a bit line electrically connected to the first and second selection transistors and the bit line senses an electrically summed read current the first read current flowing, on a portion of the bit line, from the first selection transistor to the second selection transistor parallel to the first word line and the second word line (FIG. 10: according to Kirchhoff's current law, current flowing on DL is split between paths to first selection transistor 1A and second selection transistor 1B. As the result, the current on DL is equal to the sum of currents flowing through first selection transistor 1A and second selection transistor 1B).
Asano teaches first and second floating gate transistors for storing data instead of antifuse transistors.
Li teaches an antifuse bit cell structure comprising first and second antifuse memory cells, each memory cell comprises an antifuse transistor and a select transistor (see FIG 3), wherein each of the first and second antifuse transistors comprises a metal-oxide semiconductor structure having a gate electrode disposed over a channel region defined between source and drain diffusion regions on or over a semiconductor substrate (see annotated FIG. 1A above). However, the program method of antifuse of Li is different from recited limitations.
Cheng teaches an antifuse cell comprising antifuse transistor, the antifuse transistor is programmed by application of a word line program signal to the word line causes dielectric breakdown of the gate dielectric layers of the antifuse transistor to form permanent electrically conductive paths between the corresponding gate electrodes and channel regions (FIG. 3: applying program voltage to WLP, see 8:4-16).
Since Asano, Li and Cheng are from the same field of endeavor, the purpose disclosed by Asano and Cheng would have been recognized in the pertinent art of Li.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
apply the arrangement of word line and bit line of floating gate memory bit cell structure of Asano to the antifuse bit cell structure of Li because both memory cells have the same self-redundancy function (see Asano, 2:37-56 and Li, 7:2-11);
applying the programming method of Cheng to the antifuse transistor of Li because they are functional equivalent.
Regarding dependent claim 20, Li teaches wherein applying the program signal to the first word line includes creating a permanent electrically conductive path in the first and second antifuse transistors associated with the first state (see 1:20-46).
Regarding dependent claims 21-22, Asano and Li implicitly teach the recited limitations because Li suggests the OTP memory cell 300 of FIG. 3 can be scaled to include multiple 1T1C structures to provide additional redundancy (see 7:25-35).
Regarding dependent claim 23, Li teaches wherein the first state is a low resistance state and the second state is a high resistance state (because it is characteristics of antifuses).
Regarding dependent claim 24, Asano teaches wherein the bit line is electrically connected to a source or drain terminal of the first and second selection transistors (FIG. 10: data line DL is connected to a terminal of select transistors 1A and 1B).
Regarding dependent claim 25, Cheng teaches wherein each of the first and second antifuse transistors and each of the first and second selection transistors comprise fin field-effect transistors (FinFETs) (see 8:4-16).
Regarding dependent claim 26, Cheng teaches a plurality of vertical interconnect accesses including program vias connected to the gates of the first and second antifuse transistors and data vias connected to the first and second selection transistors, the program vias configured to receive the word line program signal and the data vias configured to provide electrical connection to the bit line (see FIG. 2A).
Allowable Subject Matter
Claims 12-15 allowed.
The following is a statement of reasons for the indication of allowance:
The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitations, in combination with the remaining claimed limitations.
With respect to independent claim 12: a conductive track extending over the first active area, the second active area, the third active area and the fourth active area in the second direction, the conductive track connected to a drain or a source of the first selection transistor, a drain or a source of the second selection transistor, a drain or a source of the third selection transistor and a drain or a source of the fourth selection transistor such that across the first selection transistor, the second selection transistor, the third selection transistor, and the fourth selection transistor, the conductive track is parallel to the first word line and the second word line.
Response to Arguments
Applicant's arguments filed 03/12/2026 have been fully considered and they are partially persuasive.
The rejections of claims 12-15 have been withdrawn, and these claims are hereby allowed.
Claims 1-5 and 19-26 remain rejected. The Examiner kindly refers the Applicant to the above rejections for details.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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October 12, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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