Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I: claims 1-10 in the reply filed on 12/15/2025 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 and subsequent depending claims 2-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a first gate electrode formed on the first gate electrode layer" without first establishing “the first gate electrode layer”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al. ( US 20220181457 A1).
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CLAIM 1: Yoon et al. discloses a buried gate structure, disposed in a gate trench in a semiconductor substrate and between a source region 130 and a drain region 130 (Yoon Fig. 1), comprising:
a first gate dielectric layer 108 formed on a surface of a lower portion of the gate trench, wherein the first gate dielectric layer comprises a negative capacitance dielectric material (¶30 & 32 – 108 may be formed of hafnium oxide, zirconium oxide, of hafnium zirconium oxide among other materials recognized to be negative capacitance dielectric materials, and listed in the applicants as materials which have the required property.);
a first gate electrode 112a formed on the first gate electrode layer; a second gate dielectric layer 108b formed on a surface of an upper portion of the gate trench, wherein the second gate dielectric layer comprises a different dielectric material than the negative capacitance dielectric material (The second layer 108b may be considered a different dielectric material than the first layer 108 because it has a distinct chemical composition and different electrical properties [0032], [0058].) , and wherein an interface between the first gate dielectric layer and the second gate dielectric layer is lower than a bottom surface of the source region and the drain region (Fig. 1); and
an insulating cap layer 122 formed on the first gate electrode to fill a remaining space of the gate trench (Fig. 1 ¶49).
CLAIM 2. Yoon et al. discloses the buried gate structure as claimed in claim 1, wherein the interface is not higher than a top surface of the first gate electrode (Fig. 1 -110a+112a+116+118 may be considered parts of the first gate as they are disclosed as gate layer (i.e. barrier ¶31).).
CLAIM 3. Yoon et al. discloses the buried gate structure as claimed in claim 1, further comprising: a barrier layer 110a formed between the first gate electrode 112a and the first gate dielectric layer 108; and a second gate electrode 120a formed between the first gate electrode and the insulating cap layer 122, wherein the interface is not higher than a bottom surface of the second gate electrode (i.e. The interface is at the interface of the first gate and second gate structures.).
CLAIM 4. Th Yoon et al. discloses the e buried gate structure as claimed in claim 1, wherein the negative capacitance dielectric material comprises hafnium zirconium oxide, doped hafnium oxide, doped zirconium oxide, potassium dihydrogen phosphate, barium titanate, lead zirconate titanate, bismuth ferrite, strontium bismuth tantalate, aluminum scandium nitride, or a combination thereof (¶30 & 32 – See regarding claim 1).
CLAIM 5. Yoon et al. discloses the buried gate structure as claimed in claim 1, wherein the dielectric material comprises silicon oxide, silicon oxynitride, low-k dielectric material or a combination thereof (¶30 & 32 – See regarding claim 1).
CLAIM 6. The buried gate structure as claimed in claim 1, further comprising a second gate electrode 120a formed between the first gate electrode 114 and the insulating cap layer 122, wherein the interface is lower than a bottom surface of the second gate electrode (Fig. 1; i.e. The interface is at the interface of the first gate and second gate structures.).
CLAIM 8. Yoon et al. discloses the buried gate structure as claimed in claim 6, further comprising: a first barrier layer 110a formed between the first gate electrode 112a and the first gate dielectric layer 108; and a second barrier layer 116 formed between the first gate electrode 112a and the second gate electrode layer 120a, wherein the first gate electrode comprises a metal material (¶35) and the second gate electrode comprises a polysilicon material (¶46), and wherein a sidewall of the second gate electrode is in direct contact with the second gate dielectric layer (Fig. 1).
CLAIM 9. Yoon et al. discloses the buried gate structure as claimed in claim 6, wherein a maximum width of the second gate electrode is greater than a maximum width of the first gate electrode, and a maximum thickness of the second gate electrode is less than a maximum thickness of the first gate electrode (Fig. 1 – Both gate electrodes are vertically integrated within the same trench. Because the first gate requires a barrier layer between the metal electrode and the gate dielectric, its maximum lateral width is inherently constrained—reduced by twice the thickness of said barrier layer. In contrast, the polysilicon gate electrode does not require a barrier layer; consequently, it occupies the full available width of the trench. Therefore, the second gate electrode possesses a maximum lateral width that exceeds the first gate electrode by a margin equal to the total thickness of the omitted barrier layers.).
CLAIM 10. Yoon et al. discloses the dynamic random access memory structure, comprising: a semiconductor substrate 100 having a source region 130, a drain region 130 and a gate trench between the source region and the drain region (Fig. 1); a buried gate structure as claimed in claim 1 (Fig. 1); a bit line electrically connected to the source region or the drain region; and a capacitor electrically connected to the other of the source region or the drain region (¶157 & Fig. 17).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. ( US 20220181457 A1).
CLAIM 7. Yoon et al. discloses the buried gate structure as claimed in claim 6, further comprising: a first barrier layer 110a formed between the first gate electrode 112a and the first gate dielectric layer 108; and, wherein the first gate electrode 112a and the second gate electrode 120acomprise metal materials (¶35 & 172 – While the embodiment illustrated in Figure 1 utilizes doped polysilicon for the second gate material, paragraph 172 explicitly identifies several functional equivalents that include conventionally recognized high work function metals. Given this disclosure, it would be an obvious modification for a Person of Ordinary Skill in the Art (POSITA) to substitute a high work function metal for the second gate electrode. Such materials were well-known in the industry and utilized for similar gate structures, as evidenced by the subsequent embodiments disclosed by Yoon et al..).
While Yoon et al. does not explicitly disclose a "second barrier layer formed between the second gate electrode and the second gate dielectric layer" in the embodiment of Figure 1, this addition would be an obvious modification for a POSITA.
The motivation for this modification arises directly from the substitution of polysilicon with a metal gate material. It is a well-established principle in semiconductor fabrication that metal atoms have a high propensity to migrate or diffuse into adjacent dielectric layers during thermal processing, which can degrade gate integrity and alter threshold voltages.
Because the underlying first gate electrode already utilizes a barrier metal pattern 110a to protect the first gate dielectric from metal migration, a POSITA would find it a matter of routine engineering to implement a functionally identical barrier layer for the second metal gate electrode. Extending this existing structural safeguard to the second gate stack is a predictable application of known techniques to achieve the same protective result.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
1/2/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898