DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Agrawal et al. (PG Pub. No. US 2021/0408283 A1) in view of Xie et al. (PG Pub. No. US 2023/0038957 A1) and Chen et al. (PG Pub. No. US 2020/0295135 A1).
Regarding claim 1, Agrawal teaches a method comprising:
forming a plurality of first nanostructures (¶ 0045: PMOS nanowires 224) over a substrate (¶ 0043 & fig. 2A: 224 formed over substrate 202);
forming a plurality of second nanostructures (¶ 0044: NMOS nanowires 214) over the substrate (fig. 2A: 214 formed over 202);
epitaxially growing a first source/drain region (¶ 0045: p-type source/drain 230) adjacent the plurality of first nanostructures (fig. 2A: 230 grown adjacent to 224);
epitaxially growing a second source/drain region (¶ 0044: n-type source/drain 220) adjacent the plurality of second nanostructures (fig. 2A: 220 grown adjacent to 214);
performing an implantation process (¶ 0046: 240) to implant impurities into the second source/drain region (¶ 0046: impurity ions implanted into 220), wherein the implantation process forms an amorphous region within the second source/drain region (¶ 0046: ion implant 240 results in amorphization of source/drain structures 220); and
performing at least one thermal process on the second source/drain region (¶ 0047: thermal anneal), wherein performing each thermal process recrystallizes a portion of the amorphous region (¶ 0047: thermal anneal converts 230 into recrystallized S/D 246).
Agrawal fails to teach the thermal process includes a rapid thermal process, the method includes forming the plurality of second nanostructures (224) over the plurality of first nanostructures (214), or epitaxially growing the second source/drain region (230) over the first source/drain region (220).
Xie teaches a second nanostructure device stacked on a first nanostructure device (¶¶ 0049, 0059: nanosheet CMOS including upper nFET and lower pFET, or upper pFET and lower nFET), by a method including forming a plurality of second nanostructures over a plurality of first nanostructures (¶ 0040, fig. 5: upper nanosheets 130 formed on lower nanosheets 130), and epitaxially growing a second source/drain region over a first epitaxial source/drain region (¶¶ 0056-0058 & fig. 5: second source/drain 440 epitaxially grown over first epitaxial source/drain region 430).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Agrawal with the stacked device structure of Xie, as a means to enable reduced footprints for CMOS device architectures (Xie, ¶ 0035), improving chip scaling and manufacturing efficiency.
Agrawal in view of Xie fails to teach the thermal process includes a rapid thermal process.
Chen teaches a method including performing at least one rapid thermal process on an amorphous source/drain region (¶ 0042: RTA process performed on amorphized epitaxial source/drain region 92), wherein performing the at least one rapid thermal process recrystallizes a portion of an amorphous region (¶ 0042: RTA re-crystallizes any of the epitaxy source/drain regions 92 that was amorphous).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the thermal anneal of Agrawal in view of Xie with a rapid thermal anneal, as a means to perform the recrystallization of Agrawal with reduced thermal budget, minimizing impact to other device elements such as dopant distribution.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, the rapid thermal process could be combined with the source/drain recrystallization anneal of Agrawal, methods with no change in their respective functions and yielding nothing more than predictable results.
Regarding claim 2, Agrawal in view of Xie and Chen teaches the method of claim 1, wherein the first source/drain region is p-type and the second source/drain region is n-type (Agrawal, ¶ 0056: in at least one embodiment, source/drain 230 region is p-type, and source/drain region 220 is n-type).
Regarding claim 3, Agrawal in view of Xie and Chen teaches the method of claim 1, comprising impurities (Agrawal, ¶ 0046: impurity ions in traduced into 220). Agrawal in view of Xie and Chen further teaches source/drain regions comprising dopants such as phosphorous and arsenic (Agrawal, ¶ 0066).
Agrawal in view of Xie and Chen as applied to claim 1 above is silent to wherein the impurities comprise arsenic or diphosphorus.
However, Chen does teach implanting arsenic-containing species to amorphize at least upper portions of n-type epitaxy source/drain regions (¶ 0039).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the amorphization ion implant of Agrawal in view of Xie and Chen with arsenic impurities, as a means to provide amorphization with impurities suitable for n-type source/drain regions such as those of Agrawal and/or Xie.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, arsenic is known in the art as suitable for use with the source/drain regions of Agrawal in view of Xie and Chen, as evidenced by Chen.
Regarding claim 4, Agrawal in view of Xie and Chen teaches the method of claim 1, wherein after performing the at least one rapid thermal process, the first source/drain region exerts compressive strain on the plurality of first nanostructures (Agrawal, ¶ 0051).
Regarding claim 5, Agrawal in view of Xie and Chen teaches the method of claim 1, wherein each rapid thermal process heats the second source/drain region to a temperature less than 1250 °C (Chen, ¶ 0042: RTA temperature from 400 °C to 650 °C).
Regarding claim 7, Agrawal in view of Xie and Chen teaches the method of claim 1, wherein performing the at least one rapid thermal process fully recrystallizes the amorphous region (Chen, ¶ 0042: anneal may further re-crystallize any of the epitaxy source/drain regions 92 that was amorphous).
Regarding claim 8, Agrawal in view of Xie and Chen teaches the method of claim 1, wherein the implantation process forms an amorphous region that extends a depth from a top surface of the second source/drain region (Agrawal, ¶ 0046: 240 forms amorphous region that extends from top surface of 220).
Agrawal in view of Xie and Chen as applied to claim 1 above is silent to wherein the depth is between 5 nm and 15 nm.
However, Chen does teach an amorphous region that extends a depth from a top surface of a source/drain region that is between 2 nm and 20 nm (Chen, ¶ 0039: amorphous region in 92 extends to a depth in a range from about 2 nm to about 20 nm).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the implantation process of Agrawal in view of Xie and Chen to form the amorphous region to a depth between 2 nm and 20 nm, as a means to facilitate formation of a low-resistance silicide region (Chen, ¶ 0042: 114), improving electrical properties of the device.
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range (5 nm to 15 nm) lies inside the range disclosed by Chen (2 nm to 20 nm).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Agrawal in view of Xie and Chen as applied to claim 1 above, and further in view of Chan et al. (PG Pub. No. US 2012/0190216 A1).
Regarding claim 6, Agrawal in view of Xie and Chen teaches the method of claim 1, comprising at least one rapid thermal process (Chen, ¶ 0042).
Agrawal in view of Xie and Chen fails to teach wherein each rapid thermal process heats the second source/drain region for a duration of time that is less than 10ms.
Chan teaches that source/drain crystallization happens in about 1 ms or less (¶ 0052).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the rapid thermal process of Agrawal in view of Xie and Chen to heat the second source/drain region for a duration of time that is less than 10ms, as a means to optimize junction dopant activation and junction defects, and minimize out-diffusion (Chan, ¶ 0052).
Claims 9-11, 15 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (PG Pub. No. US 2023/0065715 A1, hereinafter ‘Xie-715’) in view of Agrawal and Lindsay (PG Pub. No. US 2010/0117159 A1).
Regarding claim 9, Xie-715 teaches a method comprising:
forming a fin extending from a substrate (fig. 6: at least one fin of a nanosheet stack extends from substrate 110/120), wherein the fin comprises a lower nanostructure (fig. 1B, 6: nanosheet 130 in bottom portion of fin) and an upper nanostructure over the lower nanostructure (nanosheet 130 in upper portion of fin structure);
forming lower epitaxial source/drain regions (¶ 0060: 710) on opposite sides of the lower nanostructure (fig. 7: 710 formed on opposing sides of lower 130);
forming an isolation region (¶ 0065: 1110) on the lower epitaxial source/drain regions (fig. 11: 1110 formed on 710);
forming upper epitaxial source/drain regions (¶ 0066: 1210) on the isolation region and on opposite sides of the upper nanostructure (fig. 12: 1210 formed on 1110 and opposing sides of lower 130).
Xie-715 does not teach the method further comprises:
amorphizing upper regions of the upper epitaxial source/drain regions;
performing a first rapid anneal process to recrystallize first amorphous portions of the upper regions of the upper epitaxial source/drain regions; and
after performing the first rapid anneal process, performing a second rapid anneal process to recrystallize remaining amorphous portions of the upper regions of the upper epitaxial source/drain regions.
Agrawal teaches a method including
forming first and second epitaxial source/drain regions (¶¶ 0044-0045: PMOS source/drain 230, NMOS source drain 220, similar to 710 and 1210 of Xie-715),
amorphizing upper regions of the second epitaxial source/drain regions (¶ 0046: ion implantation 240 amorphizes source/drain 220); and
performing a first rapid anneal process to recrystallize first amorphous portions of the upper regions of the upper epitaxial source/drain regions (¶ 0047: thermal cycle anneal recrystallizes at least upper portions of 220; since the term ‘rapid’ is relative, it is not given patentable weight).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Xie-715 with the amorphization and anneal of Agrawal, as a means to provide lattice mismatch sufficient to strain the channel regions (Agrawal, ¶ 0047), improving carrier nobility and device performance.
Xie-715 in view of Agrawal does not teach the method further comprises, after performing the first rapid anneal process, performing a second rapid anneal process to recrystallize remaining amorphous portions of the upper regions of the upper epitaxial source/drain regions.
Lindsay teaches a method including after performing a first anneal process to recrystallize amorphous portions epitaxial source/drain regions (¶ 0042: regrowth anneal), performing a second rapid anneal process to recrystallize remaining amorphous portions of the epitaxial source/drain regions (¶ 0042: additional rapid thermal anneal).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Xie-715 in view of Agrawal with the second rapid anneal of Lindsay, as a means to optimize the recrystallization and/or the semiconductor material stress (Lindsay, ¶ 0043).
Regarding claim 10, Xie-715 in view of Agrawal and Lindsay teaches the method of claim 9, wherein amorphizing upper regions of the upper epitaxial source/drain regions comprises implanting dopants into the upper epitaxial source/drain regions (Agrawal, ¶ 0046: ions implanted into upper regions of 220 and/or 230, corresponding to 1210 of Xie-715).
Regarding claim 11, Xie-715 in view of Agrawal and Lindsay teaches the method of claim 10, comprising dopants, wherein the dopants comprise n-type dopants (Xie-715: ¶ 0061: in at least one embodiment, upper source/drain region 1210 includes n-type dopant material).
Regarding claim 15, Xie-715 in view of Agrawal and Lindsay teaches the method of claim 9, wherein the first rapid anneal process and the second rapid anneal process each comprises a rapid thermal anneal (RTA) (Lindsay, ¶ 0042: regrowth anneal and additional anneal both comprise RTA).
Regarding claim 21, Xie-715 in view of Agrawal and Lindsay teaches the method of claim 9, wherein a height of the amorphized upper regions of the upper epitaxial source/drain regions is greater than half of the full height of the upper epitaxial source/drain regions (Agrawal, ¶ 0046: source/drain structure amorphized; Agrawal does not limit the relative volume of source/drain region is amorphized, such that the limitation of “greater than half of the full height of the upper epitaxial source/drain regions” is met).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Xie-715 in view of Agrawal and Lindsay as applied to claim 10 above, and further in view of Fenouillet-Beranger et al. (PG Pub. No. US 2015/0084095 A1).
Regarding claim 12, Xie-715 in view of Agrawal and Lindsay teaches the method of claim 10, including forming a first anneal on amorphous portions of doped source/drain regions (Agrawal, ¶¶ 0042, 0047: anneal performed on upper regions of amorphized n-type source/drain region 220, corresponding to 1210 of Xie-715).
Xie-715 in view of Agrawal and Lindsay is silent to wherein the first rapid anneal process activates dopants within the first amorphous portions of the upper regions of the upper epitaxial source/drain regions.
Fenouillet-Beranger teaches a method including a rapid anneal process to activate dopants within a first amorphous portion of epitaxial source/drain regions (¶ 0105: SPER type annealing activates the dopants in an epitaxial source/drain region).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first rapid anneal process of Xie-715 in view of Agrawal and Lindsay to include at least partially activating dopants within upper regions of amorphous epitaxial source/drain regions, as a means to make the resulting regrowth layer conductive (Fenouillet-Beranger, ¶ 0104).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie-715 in view of Kim et al. (PG Pub. No. US 2023/0215919 A1) and Tu et al. (PG Pub. No. US 2021/0119047 A1).
Regarding claim 16, Xie-715 teaches a method comprising:
forming a multi-layer stack (130/140) over a substrate (fig. 1B: 130/140 formed over 110/120);
patterning the multi-layer stack (¶ 0057: 130/140 patterned) to form a plurality of first channel regions and a plurality of second channel regions over the plurality of first channel regions (¶¶ 0057-0060 & fig. 6: patterning forms top nanosheet channels 130 over bottom nanosheet channels 130), wherein the first channel regions and the second channel regions comprise nanostructures (¶ 0060: nanosheets);
epitaxially growing first source/drain regions (¶ 0060: 710) over the substrate (fig. 7: 710 formed over 110/120), wherein the first channel regions extend between the first source/drain regions (fig. 7: bottom channels 130 extend between 710), wherein the first source/drain regions exerts stress in the first channel regions;
forming a dielectric layer (¶ 0065: 1110) over the first source/drain regions (fig. 11: 1110 formed over 710);
forming second source/drain regions (¶ 0066: 12010) over the dielectric layer (fig. 12: 1210 formed over 1110), wherein the second channel regions extend between the second source/drain regions (fig. 12: top channels 130 extend between 1210), wherein forming the second source/drain regions comprises:
epitaxially growing a crystalline semiconductor material over the dielectric layer (¶¶ 0044, 0066: 1210 formed by epitaxial growth, such that 1210 has a crystalline characteristic); and
forming a first gate structure around the first channel regions (¶ 0069 & fig. 14: bottom portion of high-k metal gate 1410 formed around bottom channels 130) and a second gate structure around the second channel regions (¶ 0069 & fig. 14: top portion of high-k metal gate 1410 formed around top channels 130).
Xie-715 does not teach wherein the first source/drain regions exerts stress in the first channel regions, or forming the second source/drain regions further comprises:
performing an implantation process that amorphizes a portion of the crystalline semiconductor material to form an amorphous semiconductor material over the crystalline semiconductor material; and
performing a plurality of rapid thermal processes that recrystallize the amorphous semiconductor material.
Kim teaches a method including forming a first source/drain region (¶ 0061: 170) configured to exert stress in first channel regions (¶¶ 0092, 0094: 170 configured to exert stress in active pattern 120).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first source/drain region of Xie-715 to exert stress in the first channel regions, as a means to improve carrier mobility of the channel region (Kim, ¶¶ 0092, 0094), enhancing device performance.
Xie-715 in view of Kim does not teach forming the second source/drain regions further comprises:
performing an implantation process that amorphizes a portion of the crystalline semiconductor material to form an amorphous semiconductor material over the crystalline semiconductor material; and
performing a plurality of rapid thermal processes that recrystallize the amorphous semiconductor material.
Tu teaches a method including
forming epitaxial source/drain regions (¶ 0025: 230),
performing an implantation process that amorphizes a portion of the epitaxial source/drain regions (¶ 0032: upper portion 230A formed with pre-amorphization implant); and
performing a plurality of rapid thermal processes (¶ 0034: plurality of laser anneal pulses) that recrystallize the amorphous semiconductor material (¶ 0039 & fig. 4: laser anneal recrystallizes at least a portion of 230A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second source/drain formation of Xie-715 in view of Kim with the implantation and thermal processes of Tu, as a means to optimize strain (¶ 0040), enhancing device performance.
Regarding claim 17, Xie-715 in view of Kim and Tu teaches the method of claim 16, wherein the first source/drain regions exert stress in the first channel regions after performing the plurality of rapid thermal processes (Tu, ¶ 0040: recrystallized epitaxial region 400 includes compressive or tensile strain).
Regarding claim 18, Xie-715 in view of Kim and Tu teaches the method of claim 16, wherein the first source/drain regions comprise boron-doped silicon germanium (Xie-715, ¶ 0060: 710 comprises SiGe:B).
Regarding claim 19, Xie-715 in view of Kim and Tu teaches the method of claim 16, wherein the second source/drain regions comprise phosphorus-doped silicon (Xie-715, ¶ 0066: 1210 comprises Si:P).
Regarding claim 20, Xie-715 in view of Kim and Tu teaches the method of claim 16, wherein the implantation process comprises a process temperature in the range of -100 °C to 28 °C (Tu, ¶¶ 0032-0033: Tu is silent to providing heating or cooling, such that the implant process is performed at room temperature, which is understood to be the range of 23 °C to 25 °C).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations stating:
“performing a third rapid anneal process to recrystallize second amorphous portions of the upper regions of the upper epitaxial source/drain regions, wherein the second amorphous portions are above the first amorphous portions” as recited in claim 13.
Xie-715 teaches upper (second) epitaxial source/drain regions (1210). Agrawal teaches performing a first anneal process to recrystallize first amorphous portions of second epitaxial source/drain regions (¶ 0047: thermal cycle anneal recrystallizes at least portions of 220; Examiner’s note: since ‘rapid’ is a relative term, and the duration of the claimed anneal is not particularly limited, the anneal of Agrawal meets the broadest reasonable interpretation of a ‘rapid anneal’). Lindsay teaches performing first and second anneals, including rapid anneals, on amorphous portions of epitaxial source/drain regions (¶ 0042: regrowth anneal and additional anneal).
However, none of Xie-715, Agrawal nor Lindsay teaches a third rapid anneal process to recrystallize second amorphous portions of upper regions above first amorphous portions of the upper epitaxial source/drain regions, as required by claim 13.
In light of these limitations in the claims (see Applicant’s fig. 9B & page 14 lines 11-24), the previously applied references do not anticipate or obviate the claimed method as in the context of the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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