Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response Election/Restriction filed on 05/18/26.
Summary of claims
Claims 1-26 are pending.
Claims 1-5, 10-14 and 21-26 are rejected.
Claims 6-9 are objected.
Claims 15-20 are cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10-14 and 21-26 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hills et al. (US Pub. 2020/0082032).
As to claims 1 the prior art teaches a method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells, the method comprising:
generating a netlist which represents the subset, the generating a netlist including: for each TWEI cell represented in the netlist, and for a given transistor in a given well in a given cell, expanding the netlist to include one or more proximity-effect- inducer (PEI) parameters, each PEI parameter being related to an intra-cell physical proximity of the given transistor to an edge of the given well (given well-edge) (see fig 1-4 paragraph 0122-0132 and 0202-0204).
As to claim 2 the prior art teaches wherein:
for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell, the one or more PEI parameters include: a local PEI parameter; and a global PEI parameter (see fig 2-5 and 27-30 paragraph 0132-0138);
the local PEI parameter represents a distance between the given transistor and the given well-edge (see fig 2-5 and 27-30 paragraph 0130-0134);
the local PEI parameter is based on the global PEI parameter (see fig 2-5 and 27-30 paragraph 0148-0151);
and the global PEI is a variable common to the given cell and one or more additional cells represented in the netlist (see fig 2-5 and 27-30 paragraph 0202-0210).
As to claim 3 the prior art teaches wherein: the given transistor includes one or more fins; and the distance between the given transistor and the given well-edge is a distance between a nearest fin and the given well-edge, the nearest fin being one amongst the one or more fins that is nearest to the given well-edge (see fig 2-5 and 27-30 paragraph 0140-0145).
As to claim 4, the prior art teaches wherein: the local PEI parameter is based at least in part on an integral of an expected value of a first order distribution for scattered well dopants (see fig 2-7 and 26-30 paragraph 0144-0150).
As to claims 5 the prior art teaches wherein: the local PEI parameter is also based at least in part on an integral of an expected value of a second order distribution for scattered well dopants (see fig 2-7 and 25-30 paragraph 0148-0153).
As to claim 10 the prior art teaches further comprising:
performing a simulation of the semiconductor device, the simulation being based on the netlist (see fig 2-4 and 22-30 paragraph 0202-0208);
and revising the layout diagram based on results of the simulation resulting in a revised layout diagram (see fig 2-4 and 22-30 paragraph 0217-0220).
As to claim 11 the prior art teaches further comprising: based on the revised layout diagram, at least one of: (A) making one or more photolithographic exposure; (B) fabricating one or more semiconductor masks; or (C) fabricating at least one component in a layer of a semiconductor integrated circuit (see fig 2-4 and 22-30 paragraph 0170-0178).
As to claim 12, the prior art teaches wherein: for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell, the one or more PEI parameters include: a global PEI parameter, the global PEI being a variable common to the given cell and one or more additional cells represented in the netlist (see fig 2-4 and 24-30 paragraph 0216-0221).
As to claims 13 the prior art teaches wherein:
for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell, the one or more PEI parameters include: a local PEI parameter (see fig 2-4 and 24-30 paragraph 0218-0224);
the local PEI parameter represents a proximity relationship between the given transistor and the given well-edge; and the local PEI parameter is a function of the global PEI parameter (see fig 2-4 and 22-30 paragraph 0221-0228).
As to claim 14 the prior art teaches wherein:
relative to a first direction, a first neighbor-specific PEI (NSPE) parameter represents a first distance from a first side of a subject cell to a first structure in a first neighbor cell that has a proximity effect upon the subject cell (see fig 2-4 and 22-30 paragraph 216-0223);
and relative to the first direction, a second NSPE parameter represents a second distance from a second side of the subject cell to a second structure in a second neighbor cell that has a proximity effect upon the subject cell (see fig 2-4 and 22-30 paragraph 0222-0228).
As to claim 21 the prior art teaches a method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells, the method comprising:
generating a netlist which represents the subset, the generating a netlist including: for each TWEI cell represented in the netlist, and for a given transistor in a given well in a given cell, expanding the netlist to include one or more proximity-effect- inducer (PEI) parameters, each PEI parameter being related to an intra-cell physical proximity of the given transistor to an edge of the given well (given well-edge) (see fig 1-4 paragraph 0122-0132 and 0202-0204);
and wherein the one or more PEI parameters include first and second neighbor-specific PEIs (NSPEs) (see fig 2-4 and 27-30 paragraph 0148-0153);
wherein, relative to a first direction, the first NSPE parameter represents a first distance from a first side of a subject cell to a first structure in a first neighbor cell that has a proximity effect upon the subject cell (see fig 2-4 and 26-30 paragraph 0151-0163);
and wherein, relative to the first direction, the second NSPE parameter represents a second distance from a second side of the subject cell to a second structure in a second neighbor cell that has a proximity effect upon the subject cell (see fig 2-4 and 26-30 paragraph 0207-0213).
As to claim 22, the prior art teaches wherein: for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell, the one or more PEI parameters further include: a global PEI parameter, the global PEI being a variable common to the given cell and one or more additional cells represented in the netlist (see fig 2-4 and 22-30 paragraph 0232-0238).
As to claims 23 the prior art teaches wherein: for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell, the one or more PEI parameters further include: a local PEI parameter; the local PEI parameter represents a proximity relationship between the given transistor and the given well-edge; and the local PEI parameter is a function of the global PEI parameter (see fig 2-4 and 22-30 paragraph 0236-0243).
As to claim 24 the prior art teaches a method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells, the method comprising:
generating a netlist which represents the subset, the generating a netlist including: for each TWEI cell represented in the netlist, and for a given transistor in a given well in a given cell, expanding the netlist to include one or more proximity-effect- inducer (PEI) parameters, each PEI parameter being related to an intra-cell physical proximity of the given transistor to an edge of the given well (given well-edge) (see fig 1-4 paragraph 0122-0132 and 0202-0204);
and for each TWEI cell represented in the netlist, and for the given transistor in given well in the given cell, the one or more PEI parameters include: a local PEI parameter (see fig 2-4 and 27-30 paragraph 0148-0155);
and a global PEI parameter (see fig 2-4 and 22-30 paragraph 0153-0158);
the local PEI parameter represents a distance between the given transistor and the given well-edge; the local PEI parameter is based on the global PEI parameter (see fig 2-4 and 22-30 paragraph 0209-0218);
and the global PEI is a variable common to the given cell and one or more additional cells represented in the netlist (see fig 2-4 and 22-30 paragraph 0217-0226).
As to claim 25 the prior art teaches wherein: the given transistor includes one or more fins; and the distance between the given transistor and the given well-edge is a distance between a nearest fin and the given well-edge, the nearest fin being one amongst the one or more fins that is nearest to the given well-edge (see fig 1-4 paragraph 0162-0168).
As to claim 26, the prior art teaches wherein: the local PEI parameter is based at least in part on an integral of an expected value of a first order distribution for scattered well dopants (see fig 1-4 paragraph 0182-0192).
Allowable Subject Matter
Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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