DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 2. Applicant amended claims 1 and 17; and cancelled claims 4, 5, 9-16 on 11/29/2023.. 3. Applicant added claims 21-30 on 11/29/2023. Election/Restrictions Restriction to one of the following inventions is required under 35 U.S.C. 121: I. Group 1, claim(s) 1-3, 6-8, 21, and 22-29, drawn to a power gating cell, classified in H10D89/10 . II. Group 2, claim(s) 17-20 and 30, drawn to a method of fabricating a power gating cell, classified in H01L21/56. In accordance with 37 CFR 1.499, applicant is required, in reply to this action, to elect a single invention to which the claims must be restricted. The inventions are distinct, each from the other because of the following reasons: Inventions I and II are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the product as claimed can be made by another and materially different process or (2) that the process as claimed can be used to make another and materially different product (MPEP § 806.05(f)). In the instant case, the product of claims 1-3, 6-8, 21, and 22-29 can be made by a different process from the process of claims 17-20 and 30 such as a power gating cell can be formed in the following steps: providing a substrate, wherein there is a first active region and a plurality of second active regions on the substrate, the first active region located in a central area of the power gating cell and having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, the plurality of second active regions located in a peripheral area of the power gating cell adjacent the central area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction; forming fin structures over the first active region and the plurality of second active regions; growing dop ed source regions and drain regions of the fin structures; and forming gate structures over the fin structures in the first active region and the plurality of second active regions. Instead of, providing a substrate, wherein there is a first active region and a plurality of second active regions on the substrate, the first active region located in a central area of the power gating cell and having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction, the plurality of second active regions located in a peripheral area of the power gating cell adjacent the central area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction; forming fin structures over the first active region and the plurality of second active regions; doping source regions and drain regions of the fin structures; and forming gate structures over the fin structures in the first active region and the plurality of second active regions. Restriction for examination purposes as indicated is proper because all these inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because at least the following reason(s) apply: Inventions I and II have acquired a separate status in the art as shown by their different classification. During a telephone conversation with Kevin R. Swanson on 1 2 / 16 /20 25 a provisional election was made without traverse to prosecute the invention of Group 1, claim(s) 1-3, 6-8, 21, and 22-29 . Affirmation of this election must be made by applicant in replying to this Office action. Group 2, claim(s) 17-20 and 30 , is withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention. The election of an invention or species may be made with or without traverse. To preserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable on the elected invention or species. Applicant is reminded that upon the cancellation of claims to a non-elected invention, the inventorship must be amended in compliance with 37 CFR 1.48(b) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. Any amendment of inventorship must be accompanied by a request under 37 CFR 1.48(b) and by the fee required under 37 CFR 1.17( i ). The examiner has required restriction between product and process claims. Where applicant elects claims directed to the product, and all product claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product claim for that process invention to be rejoined. In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104. Thus, to be allowable, the rejoined claims must meet all criteria for patentability including the requirements of 35 U.S.C. 101, 102, 103 and 112. Until all claims to the elected product/apparatus are found allowable, an otherwise proper restriction requirement between product/apparatus claims and process claims may be maintained. Withdrawn process claims that are not commensurate in scope with an allowable product/apparatus claim will not be rejoined. See MPEP § 821.04. Additionally, in order for rejoinder to occur, applicant is advised that the process claims should be amended during prosecution to require the limitations of the product/apparatus claims. Failure to do so may result in no rejoinder. Further, note that the prohibition against double patenting rejections of 35 U.S.C. 121 does not apply where the restriction requirement is withdrawn by the examiner before the patent issues. See MPEP § 804.01. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 6-8 , 22-24, and 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Oh et al. (US 2019/0198496) (hereafter Oh) , in view of Fan et al. (US 2018/0145070 ) (hereafter Fan ). Regarding claim 1 , Oh discloses a power gating cell on an integrated circuit, comprising: a central area A2 (Fig. 27, paragraph 0173) ; a peripheral area (region of Fig. 27 excluding A2) adjacent surrounding the central area A2 (Fig. 27) ; a first active region A2 (Fig. 27) located in the central area A2 (Fig. 27) , the first active region having a first width (width of A2 in vertical direction in Fig. 27) in a first direction (vertical direction in Fig. 27) corresponding to at least four fin structures 111 (Fig. 27, paragraph 0174) extending in a second direction (horizontal direction in Fig. 27) perpendicular to the first direction (vertical direction in Fig. 27) ; and a plurality of second active regions 115d (Fig. 27, paragraph 0172) located in the peripheral area (region of Fig. 27 excluding A2) , each second active region 115d (Fig. 27) having a second width (width of 115d in vertical direction in Fig. 27) in the first direction (vertical direction in Fig. 27) corresponding to at least one and no more than three fin structures 110d (Fig. 27, paragraph 0172) extending in the second direction (horizontal direction in Fig. 27) , Oh does not disclose the power gating cell is a header cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal. Fan discloses the power gating cell 110 (Fig. 2, paragraph 0016) is a header cell 110 (Fig. 2) configured to cut off (see paragraph 0020, wherein “ Each of the transistors of the transistor units 230, 240, 270, 280 further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors.”) a power supply 220a (Fig. 2, paragraph 0021) to a standard logic cell 130 (Fig. 2, paragraph 0016) on the integrated circuit 100 (Fig. 2, paragraph 0016) in response to a control signal (“voltage signal” in paragraph 0022). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Oh to form the power gating cell is a header cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal, as taught by Fan, since each of the transistors of the transistor units 230, 240, 270, 280 (Fan, Fig. 2, paragraph 0020) further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors such that it enables the cell circuit 130 (Fan, Fig. 2, paragraph 0022) to perform the predetermined circuit function. Regarding claim 2 , Oh further discloses the power gating cell of claim 1, wherein the integrated circuit has a set of global fin grids 27’ (Fig. 10C, paragraph 0083) extending in the second direction (horizontal direction in Fig. 10C), and the at least four fin structures 111 (Fig. 27) corresponding to the first active region A2 (Fig. 27) are aligned with the set of global fin grids 27’ (Fig. 10C). Regarding claim 6 , Oh (utilized different element for a second width and at least one and no more than three fin structures as applied in claim 1 in the above) discloses a power gating cell on an integrated circuit, comprising: a central area A2 (Fig. 27, paragraph 0173); a peripheral area (region of Fig. 27 excluding A2) adjacent the central area A2 (Fig. 27); a first active region A2 (Fig. 27) located in the central area A2 (Fig. 27), the first active region A2 (Fig. 27) having a first width (width of A2 in vertical direction in Fig. 27) in a first direction (vertical direction in Fig. 27) corresponding to at least four fin structures 111 (Fig. 27, paragraph 0174) extending in a second direction (horizontal direction in Fig. 27) perpendicular to the first direction (vertical direction in Fig. 27); a plurality of second active regions (regions where 110d are formed in Fig. 27, paragraph 0172) located in the peripheral area (region of Fig. 27 excluding A2), each second active region (regions where 110d are formed in Fig. 27) having a second width (width of single 110d in vertical direction in Fig. 27) in the first direction (vertical direction in Fig. 27) corresponding to at least one and no more than three fin structures 110d (Fig. 27, paragraph 0172) extending in the second direction (horizontal direction in Fig. 27); and wherein the second width (width of single 110d in vertical direction in Fig. 27) corresponds to one fin structure 110d (Fig. 27). Oh does not disclose the power gating cell is a header cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal. Fan discloses the power gating cell 110 (Fig. 2, paragraph 0016) is a header cell 110 (Fig. 2) configured to cut off (see paragraph 0020, wherein “Each of the transistors of the transistor units 230, 240, 270, 280 further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors.”) a power supply 220a (Fig. 2, paragraph 0021) to a standard logic cell 130 (Fig. 2, paragraph 0016) on the integrated circuit 100 (Fig. 2, paragraph 0016) in response to a control signal (“voltage signal” in paragraph 0022). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Oh to form the power gating cell is a header cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal, as taught by Fan, since each of the transistors of the transistor units 230, 240, 270, 280 (Fan, Fig. 2, paragraph 0020) further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors such that it enables the cell circuit 130 (Fan, Fig. 2, paragraph 0022) to perform the predetermined circuit function. Regarding claim 7 , Oh (utilized different element for a second width and at least one and no more than three fin structures as applied in claim 1 in the above) discloses a power gating cell on an integrated circuit, comprising: a central area A2 (Fig. 27, paragraph 0173); a peripheral area (region of Fig. 27 excluding A2) adjacent the central area A2 (Fig. 27); a first active region A2 (Fig. 27) located in the central area A2 (Fig. 27), the first active region A2 (Fig. 27) having a first width (width of A2 in vertical direction in Fig. 27) in a first direction (vertical direction in Fig. 27) corresponding to at least four fin structures 111 (Fig. 27, paragraph 0174) extending in a second direction (horizontal direction in Fig. 27) perpendicular to the first direction (vertical direction in Fig. 27); a plurality of second active regions (regions where 110d are formed in Fig. 27, paragraph 0172) located in the peripheral area (region of Fig. 27 excluding A2), each second active region (regions where 110d are formed in Fig. 27) having a second width (width of two 110d in vertical direction in Fig. 27) in the first direction (vertical direction in Fig. 27) corresponding to at least one and no more than three fin structures 110d (Fig. 27, paragraph 0172) extending in the second direction (horizontal direction in Fig. 27); and wherein the second width (width of two 110d in vertical direction in Fig. 27) corresponds to two fin structures 110d (Fig. 27). Oh does not disclose the power gating cell is a header cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal. Fan discloses the power gating cell 110 (Fig. 2, paragraph 0016) is a header cell 110 (Fig. 2) configured to cut off (see paragraph 0020, wherein “Each of the transistors of the transistor units 230, 240, 270, 280 further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors.”) a power supply 220a (Fig. 2, paragraph 0021) to a standard logic cell 130 (Fig. 2, paragraph 0016) on the integrated circuit 100 (Fig. 2, paragraph 0016) in response to a control signal (“voltage signal” in paragraph 0022). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Oh to form the power gating cell is a header cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal, as taught by Fan, since each of the transistors of the transistor units 230, 240, 270, 280 (Fan, Fig. 2, paragraph 0020) further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors such that it enables the cell circuit 130 (Fan, Fig. 2, paragraph 0022) to perform the predetermined circuit function. Regarding claim 8 , Oh further discloses the power gating cell of claim 1, wherein the second width (width of 115d in vertical direction in Fig. 27) corresponds to three fin structures 110d (Fig. 27) . Regarding claim 22 , Oh further discloses the power gating cell of claim 1, wherein the peripheral area (region of Fig. 27 excluding A2) surrounds the central area A2 (Fig. 27) . Regarding claim 23 , Chen discloses a power gating cell on an integrated circuit, comprising: a central area A2 (Fig. 27, paragraph 0173) ; a peripheral area (region of Fig. 27 excluding A2) adjacent the central area A2 (Fig. 27) ; a first active region A2 (Fig. 27) located in the central area A2 (Fig. 27) , the first active region A2 (Fig. 27) having a first width (width of A2 in vertical direction in Fig. 27) in a first direction (vertical direction in Fig. 27) corresponding to at least four fin structures 111 (Fig. 27, paragraph 0174) extending in a second direction (horizontal direction in Fig. 27) perpendicular to the first direction (vertical direction in Fig. 27) ; and a plurality of second active regions 115d (Fig. 27, paragraph 0172) located in the peripheral area (region of Fig. 27 excluding A2) , each second active region 115d (Fig. 27) having a second width (width of 115d in vertical direction in Fig. 27) in the first direction (vertical direction in Fig. 27) corresponding to at least one and no more than three fin structures 110d (Fig. 27, paragraph 0172) extending in the second direction (horizontal direction in Fig. 27) . Oh does not disclose the power gating cell is a footer cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal. Fan discloses the power gating cell 120 (Fig. 2, paragraph 0016) is a footer cell 120 (Fig. 2) configured to cut off (see paragraph 0020, wherein “Each of the transistors of the transistor units 230, 240, 270, 280 further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors.”) a power supply 260a (Fig. 2, paragraph 0021) to a standard logic cell 130 (Fig. 2, paragraph 0016) on the integrated circuit 100 (Fig. 2, paragraph 0016) in response to a control signal (“voltage signal” in paragraph 0022). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Oh to form the power gating cell is a footer cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal, as taught by Fan, since each of the transistors of the transistor units 230, 240, 270, 280 (Fan, Fig. 2, paragraph 0020) further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors such that it enables the cell circuit 130 (Fan, Fig. 2, paragraph 0022) to perform the predetermined circuit function. Regarding claim 24 , Oh further discloses the power gating cell of claim 23, wherein the integrated circuit has a set of global fin grids 27’ (Fig. 10C, paragraph 0083) extending in the second direction (horizontal direction in Fig. 10C), and the at least four fin structures 111 (Fig. 27) corresponding to the first active region A2 (Fig. 27) are aligned with the set of global fin grids 27’ (Fig. 10C). Regarding claim 26 , Oh (utilized different element for a second width and at least one and no more than three fin structures as applied in claim 1 in the above) discloses a power gating cell on an integrated circuit, comprising: a central area A2 (Fig. 27, paragraph 0173); a peripheral area (region of Fig. 27 excluding A2) adjacent the central area A2 (Fig. 27); a first active region A2 (Fig. 27) located in the central area A2 (Fig. 27), the first active region A2 (Fig. 27) having a first width (width of A2 in vertical direction in Fig. 27) in a first direction (vertical direction in Fig. 27) corresponding to at least four fin structures 111 (Fig. 27, paragraph 0174) extending in a second direction (horizontal direction in Fig. 27) perpendicular to the first direction (vertical direction in Fig. 27); a plurality of second active regions (regions where 110d are formed in Fig. 27, paragraph 0172) located in the peripheral area (region of Fig. 27 excluding A2), each second active region (regions where 110d are formed in Fig. 27) having a second width (width of single 110d in vertical direction in Fig. 27) in the first direction (vertical direction in Fig. 27) corresponding to at least one and no more than three fin structures 110d (Fig. 27, paragraph 0172) extending in the second direction (horizontal direction in Fig. 27); and wherein the second width (width of single 110d in vertical direction in Fig. 27) corresponds to one fin structure 110d (Fig. 27). Oh does not disclose the power gating cell is a footer cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal. Fan discloses the power gating cell 120 (Fig. 2, paragraph 0016) is a footer cell 120 (Fig. 2) configured to cut off (see paragraph 0020, wherein “Each of the transistors of the transistor units 230, 240, 270, 280 further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors.”) a power supply 260a (Fig. 2, paragraph 0021) to a standard logic cell 130 (Fig. 2, paragraph 0016) on the integrated circuit 100 (Fig. 2, paragraph 0016) in response to a control signal (“voltage signal” in paragraph 0022). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Oh to form the power gating cell is a footer cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal, as taught by Fan, since each of the transistors of the transistor units 230, 240, 270, 280 (Fan, Fig. 2, paragraph 0020) further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors such that it enables the cell circuit 130 (Fan, Fig. 2, paragraph 0022) to perform the predetermined circuit function. Regarding claim 27 , Oh (utilized different element for a second width and at least one and no more than three fin structures as applied in claim 1 in the above) discloses a power gating cell on an integrated circuit, comprising: a central area A2 (Fig. 27, paragraph 0173); a peripheral area (region of Fig. 27 excluding A2) adjacent the central area A2 (Fig. 27); a first active region A2 (Fig. 27) located in the central area A2 (Fig. 27), the first active region A2 (Fig. 27) having a first width (width of A2 in vertical direction in Fig. 27) in a first direction (vertical direction in Fig. 27) corresponding to at least four fin structures 111 (Fig. 27, paragraph 0174) extending in a second direction (horizontal direction in Fig. 27) perpendicular to the first direction (vertical direction in Fig. 27); a plurality of second active regions (regions where 110d are formed in Fig. 27, paragraph 0172) located in the peripheral area (region of Fig. 27 excluding A2), each second active region (regions where 110d are formed in Fig. 27) having a second width (width of two 110d in vertical direction in Fig. 27) in the first direction (vertical direction in Fig. 27) corresponding to at least one and no more than three fin structures 110d (Fig. 27, paragraph 0172) extending in the second direction (horizontal direction in Fig. 27); and wherein the second width (width of two 110d in vertical direction in Fig. 27) corresponds to two fin structures 110d (Fig. 27). Oh does not disclose the power gating cell is a footer cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal. Fan discloses the power gating cell 120 (Fig. 2, paragraph 0016) is a footer cell 120 (Fig. 2) configured to cut off (see paragraph 0020, wherein “Each of the transistors of the transistor units 230, 240, 270, 280 further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors.”) a power supply 260a (Fig. 2, paragraph 0021) to a standard logic cell 130 (Fig. 2, paragraph 0016) on the integrated circuit 100 (Fig. 2, paragraph 0016) in response to a control signal (“voltage signal” in paragraph 0022). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Oh to form the power gating cell is a footer cell configured to cut off a power supply to a standard logic cell on the integrated circuit in response to a control signal, as taught by Fan, since each of the transistors of the transistor units 230, 240, 270, 280 (Fan, Fig. 2, paragraph 0020) further has a gate terminal connected to a sleep control node (SLP CTRL), at which a voltage signal is applied to turn on/off the transistors such that it enables the cell circuit 130 (Fan, Fig. 2, paragraph 0022) to perform the predetermined circuit function. Regarding claim 28 , Oh further discloses the power gating cell of claim 23, wherein the second width (width of 115d in vertical direction in Fig. 27) corresponds to three fin structures 111 (Fig. 27). Allowable Subject Matter 1. Claims 3 , 21, 25, and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: 2. Claim 3 would be allowable because a closest prior art, Oh et al. (US 2019/0198496), discloses at least one and no more than three fin structures 110d (Fig. 27, paragraph 0172) extending in the second direction (horizontal direction in Fig. 27) are aligned with the set of global fin grids 27’ (Fig. 10C, paragraph 0083) but fails to disclose the at least one and no more than three fin structures corresponding to each of the plurality of second active regions are not aligned with the set of global fin grids . Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a power gating cell on an integrated circuit, comprising: the at least one and no more than three fin structures corresponding to each of the plurality of second active regions are not aligned with the set of global fin grids in combination with other elements of the base claim 1. In addition , claim 21 would be allowable because a closest prior art, Oh et al. (US 2019/0198496), discloses a first active region A2 (Fig. 27) located in the central area A2 (Fig. 27) , the first active region having a first width (width of A2 in vertical direction in Fig. 27) in a first direction (vertical direction in Fig. 27) corresponding to at least four fin structures 111 (Fig. 27, paragraph 0174) extending in a second direction (horizontal direction in Fig. 27) perpendicular to the first direction (vertical direction in Fig. 27) but fails to disclose a third active region located in the central area, the third active region separated from the first active region and having a third width in the first direction corresponding to at least four fin structures extending in the second direction perpendicular to the first direction. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a power gating cell on an integrated circuit, comprising: a third active region located in the central area, the third active region separated from the first active region and having a third width in the first direction corresponding to at least four fin structures extending in the second direction perpendicular to the first direction in combination with other elements of the base claim 1. Moreover , claim 25 would be allowable because a closest prior art, Oh et al. (US 2019/0198496), discloses at least one and no more than three fin structures 110d (Fig. 27, paragraph 0172) extending in the second direction (horizontal direction in Fig. 27) are aligned with the set of global fin grids 27’ (Fig. 10C, paragraph 0083) but fails to disclose the at least one and no more than three fin structures corresponding to each of the plurality of second active regions are not aligned with the set of global fin grids . Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a power gating cell on an integrated circuit, comprising: the at least one and no more than three fin structures corresponding to each of the plurality of second active regions are not aligned with the set of global fin grids in combination with other elements of the base claim 23. Furthermore, claim 29 would be allowable because a closest prior art, Oh et al. (US 2019/0198496), discloses a first active region A2 (Fig. 27) located in the central area A2 (Fig. 27) , the first active region having a first width (width of A2 in vertical direction in Fig. 27) in a first direction (vertical direction in Fig. 27) corresponding to at least four fin structures 111 (Fig. 27, paragraph 0174) extending in a second direction (horizontal direction in Fig. 27) perpendicular to the first direction (vertical direction in Fig. 27) but fails to disclose a third active region located in the central area, the third active region separated from the first active region and having a third width in the first direction corresponding to at least four fin structures extending in the second direction perpendicular to the first direction. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a power gating cell on an integrated circuit, comprising: a third active region located in the central area, the third active region separated from the first active region and having a third width in the first direction corresponding to at least four fin structures extending in the second direction perpendicular to the first direction in combination with other elements of the base claim 23. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT LAMONT B KOO whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-0984 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 7:00 AM - 3:30 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier FILLIN "SPE Name?" \* MERGEFORMAT can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /L.B.K/ Examiner, Art Unit 2813 /SHAHED AHMED/ Primary Examiner, Art Unit 2813