DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2017/0292993) by Yoon et al (“Yoon”) in view of (US-2020/0266169) by Kang et al (“Kang”).
Regarding claim 1, Yoon discloses in FIGs. 4-22 and related text, e.g., a method of fabricating an integrated circuit, the method comprising:
fabricating a first set of transistors in a front-side of a wafer thereby forming a first flip- flop (FIG. 4, FF1a; is a flip-flop; it has “first set of transistors” forming it, as shown by FIG. 6A, 130/150,170, and similar other figures in the reference; as far as “front-side of a wafer” [Wingdings font/0xE0] the side of a wafer on which one forms transistors, by definition);
depositing a first set of conductive structures over the first set of transistors, the first set of conductive structures extending in a first direction (X direction; the connections that go left-to-right, for example, in FIG. 6A, when it is properly oriented), and being located on a first level (these features are notoriously well-known; “first level” is the default, lowest level metal interconnect, notoriously well-known in any semiconductor process, used for producing standard cells, such as flip-flops; typically (not always) called “metal1”; as evidence of Examiner’s assertion, see US-2009/0065813; see pars. 7-9 as far as discussion of basic metal and via arrangements, including running certain metal layers horizontally (X-direction) and certain vertically (Y-direction); see FIGs. 6A-C of ‘813 reference for visualization of the layers; also, see FIG. 7 of ‘813 reference for detailed visualization of the layers);
Yoon does not disclose “performing wafer thinning on a back-side of the wafer opposite from the front-side of the wafer; fabricating a first set of vias on the back-side of the wafer; and depositing a set of power rails on at least the back-side of the wafer, the set of power rails extending in the first direction, each power rail being separated from an adjacent power rail in a second direction different from the first direction; wherein the first set of conductive structures is separated from a center of a first power rail of the set of power rails in the second direction.”
Kang discloses in FIGs. 1-4C and related text, e.g., “performing wafer thinning on a back-side of the wafer opposite from the front-side of the wafer (FIG. 2, step S230; also, FIG. 3B and FIG. 4B demonstrate the process);
fabricating a first set of vias (see FIG. 1, “Power” label that goes from VDD/VSS/VDD to the SC1-SC6 above it; these connections are the vias that go in Z-direction; also see FIGs. 4A-D for a different visualization of features; specifically, the features 431 (“dummy power rails”) function as vias in the future, for the power rails that are deposited later (see FIG. 4D)) on the back-side of the wafer; and
depositing a set of power rails (FIG. 1, VDD/VSS/VDD) on at least the back-side of the wafer, the set of power rails extending in the first direction (same direction as Yoon shows [Wingdings font/0xE0] X-direction, from left-to-right, in a properly oriented drawing), each power rail being separated from an adjacent power rail in a second direction different from the first direction (see FIG. 1; they are spaced apart in Y-direction from each other);
wherein the first set of conductive structures is separated from a center of a first power rail of the set of power rails in the second direction (this feature is best seen in FIG. 4D, and similar; “power rails” are 430 in FIG. 4D, sitting on top of vias 431 (unmarked in 4D; marked in 4C); take the right most 430 as the “first power rail”; the “first set of conductive structures” is located inside 420, as one of the layers there; take the left most portion of one of the layers inside 420 as the “first set”; hence, by defining the “rail” and “first set”, in such a way, we can see that they are separated “from a center of a first power rail of the set of power rails in the second direction”, just as claim requires; the 2nd direction being left-to-right in a properly oriented FIG. 4D, which is the same as Y-direction in FIG. 1 (spacing between the power rails being the “2nd direction” in both drawings).”
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Yoon
with “performing wafer thinning on a back-side of the wafer opposite from the front-side of the wafer; fabricating a first set of vias on the back-side of the wafer; and depositing a set of power rails on at least the back-side of the wafer, the set of power rails extending in the first direction, each power rail being separated from an adjacent power rail in a second direction different from the first direction; wherein the first set of conductive structures is separated from a center of a first power rail of the set of power rails in the second direction” as taught by Kang, and
with “various structures (“first set”) are being located on the first metal layer”
in order to allow for cell area reduction (par. 6 of Kang), and
in order to access the transistor inputs, since transistors are located below metal layers; therefore, using the lowest available metal (first metal layer/“metal1”) is necessary in order to access transistors below it (for visualization purposes, see US-6583045, FIG. 7; it shows output connection being marked as “OUT”; then, see FIG. 6 of ‘045 for actual “metal1” 88/92/96 connections; also see the already cited above US-2009/0065813 and its various pars. and FIGs., for a different visualization of the concepts for higher level metals (“metal2”, etc.), respectively.
Regarding claim 2, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., fabricating a second set of vias on the front-side of the wafer, and being over the first set of conductive structures (first of all, it is notoriously well-known to use vias as connection between first metal and second metal (the metal layer directly above “first metal”); hence, “second set of vias” would naturally be used to make connections to layers above “first metal”; second of all, transistor connections have to be done on first metal (as was illustrated in FIGs. 6-7 of ‘045 reference and was discussed regarding claim 1, and as was also illustrated by the ‘813 reference); hence, such limitations are met).
Regarding claim 3, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., further comprising:
depositing a second set of conductive structures over at least the first set of conductive structures or the second set of vias (these are notoriously well-known features; such as the ones shown running vertically, in Y-direction in FIG. 6A of Yoon; the vertical connections sometimes cross over the underlying horizontal connections, without connecting to them (look down from node marked “bCK” for example, to the left of circuit 120); hence, it is on the next level up (typically referred to as “metal2”); hence, “second set of conductive structures over … “first set of conductive structures” and corresponding vias, to connect metal layers), the second set of conductive structures extending in the second direction (Y-direction, as was mentioned above), and being located on a second level different from the first level (“metal2”); again, see the previously cited ‘045 and ‘813 references for evidence and visualization of various standard practices, that are recited in this claim).
Regarding claim 4, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., wherein fabricating the first set of transistors in the front-side of the wafer comprises:
fabricating a set of gates of the first set of transistors on the front-side of the wafer (by definition; these are notoriously well-known features; “gates” are notoriously well-known parts of transistor; the circuits shown in FIG. 6A are formed of such transistors that contain gates; so, by definition, formation of transistors like the ones shown in FIG. 6A, requires formation of gates; as visual representation, see ‘045, FIG. 6, which shows gate (64), drain (68) and source (69) of normal transistor and their connections).
Regarding claim 11, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., a method of fabricating an integrated circuit, the method comprising:
fabricating a first set of transistors in a front-side of a wafer thereby forming a first flip- flop (see claim 1) and a second flip-flop (below the first one, contains 140/160/180), the second flip-flop abutting the first flip-flop at a first boundary (see FIG. 6A; the two flip-flops are abutting each other);
depositing a first set of conductive structures over the first set of transistors, the first set of conductive structures extending in a first direction, and being located on a first level (see claim 1);
fabricating a first set of vias on a back-side of the wafer opposite from the front-side of the wafer (see claim 1); and
depositing a second set of conductive structures on at least the back-side of the wafer thereby forming a set of power rails, the set of power rails extending in the first direction, each power rail being separated from an adjacent power rail in a second direction different from the first direction (see claim 1; slightly differently worded, but the same logic applies);
wherein the first set of conductive structures is separated from a center of a first power rail of the set of power rails in the second direction (see claim 1).
Regarding claim 12, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., further comprising:
fabricating a second set of vias on the front-side of the wafer, and being over the first set of conductive structures (see claim 2).
Regarding claim 13, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., further comprising:
depositing a third set of conductive structures over at least the first set of conductive structures or the second set of vias, the third set of conductive structures extending in the second direction, and being located on a second level different from the first level (see claim 3; this “third set” is virtually identical to “second set” in claim 3).
Regarding claim 14, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., wherein the first set of conductive structures comprises:
a first sub-set of conductive structures offset from the first boundary (horizontal boundary (X-direction) between two flip-flops in FIG. 6A) in the second direction (Y-direction), the first sub-set of conductive structures being over the first flip-flop, and a second sub-set of conductive structures offset from the first boundary in the second direction, the second sub-set of conductive structures being over the second flip-flop (hence, “first sub-set” is “metal1” over top flip-flop (130/150/170) and “second sub-set” is “metal1” over the second flip-flop (140/160/180) in FIG. 6A of Yoon).
Regarding claim 15, the combined method of Yoon and Kang disclose substantially the entire claimed structure as recited in above claims, but do not explicitly state “wherein at least a first conductive structure of the first sub-set of conductive structures has a first width in the second direction; and at least a first conductive structure of the second sub-set of conductive structures has a second width in the second direction different from the first width”.
In other words, the above limitations require that at least some wirings in “metal1” are to be of non-identical width. This is a normal feature, but Yoon and Kang are silent about it.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Yoon and Kang with “wherein at least a first conductive structure of the first sub-set of conductive structures has a first width in the second direction; and at least a first conductive structure of the second sub-set of conductive structures has a second width in the second direction different from the first width”, since it is notoriously well-known that the wider the metal, the more current it can safely carry; hence, it would be obvious to make wiring wider in specific locations where higher current capacity is necessary, and to make wiring narrower in specific locations where higher current capacity is not necessary (to elaborate briefly on the above, from Examiner’s personal experience: this logic/teaching/knowledge (use wider metal for more current) is taught in second year of undergraduate program of electrical engineering; in other words, this is “learner in the art” level knowledge, way below “skilled in the art”; hence, the usage of such knowledge (to use metals of differing widths, depending on the requirements of current, for any specific design application, is trivial and notoriously well-known).
Regarding claim 16, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., wherein at least a first conductive structure of the first sub-set of conductive structures has a first width in the second direction; and at least a first conductive structure of the second sub-set of conductive structures has the first width in the second direction (the claim requires at least two wirings to have identical width; this is a notoriously well-known feature; the wirings, unless otherwise required – like in claim 15, to carry more current – are normally made in a minimum width that is required by a particular design rules of specific manufacturing process; hence, having the same width between different wirings on the same layer is extremely normal [Wingdings font/0xE0] it minimizes the space used).
Regarding claim 17, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., a method of fabricating an integrated circuit, the method comprising:
fabricating a first flip-flop in a front-side of a wafer (claims 1 & 11);
fabricating a second flip-flop in the front-side of the wafer, the second flip-flop abutting the first flip-flop at a first boundary (claim 11);
fabricating a third flip-flop in the front-side of the wafer, the third flip-flop abutting the second flip-flop at a second boundary (not taught in embodiment of FIG. 6A of Yoon; however, such an embodiment is taught in par. 65; a “5-or-more-bit” flip-flop is specifically taught in par. 65; hence, these limitations are at the very least obvious in light of Yoon’s explicit teachings);
depositing a first set of conductive structures over the first flip-flop, the first set of conductive structures extending in a first direction, and being located on a first metal level (see claims 1 & 11, including references to “metal1”);
depositing a second set of conductive structures over the second flip-flop, the second set of conductive structures extending in the first direction, being located on the first metal level, and being separated from the first set of conductive structures in a second direction different from the first direction (similar to claim 14; the only difference in the naming [Wingdings font/0xE0] “first set” and “second set” here, instead of “first sub-set” and “second sub-set” in claim 14);
depositing a third set of conductive structures over the third flip-flop, the third set of conductive structures extending in the first direction, being located on the first metal level, and being separated from the first and second set of conductive structures in the second direction (same as limitations above, referring to claim 14; each of the flip-flops has its own set of “conductive structures” by definition, to interconnect its own transistors);
fabricating a first set of vias on a back-side of the wafer opposite from the front-side of the wafer (see claims 1 & 11); and
depositing a set of power rails on at least the back-side of the wafer, the set of power rails extending in the first direction (see claims 1 & 11), and being electrically coupled to the first flip-flop, the second flip-flop and the third flip-flop by at least the first set of vias (by definition; that is what Kang’s vias do - they connect transistors to underlying power rails; this is the whole point of Kang’s invention [Wingdings font/0xE0] delivery of power from back-side power rails), each power rail being separated from an adjacent power rail in the second direction (see claims 1 & 11);
wherein a center of each conductive structure of the first, second or third set of conductive structures is separated from a center of each power rail of the set of power rails in the second direction (see claim 1; same logic applies for each additional flip-flop).
Regarding claim 18, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., further comprising:
fabricating a second set of vias on the front-side of the wafer, and being over at least one of the first set of conductive structures, the second set of conductive structures or the third set of conductive structures (same logic applies as in claims 2 & 12; just for more flip-flops); and
depositing a fourth set of conductive structures over at least the second set of vias, the fourth set of conductive structures extending in the second direction, and being located on a second metal level different from the first metal level (see claims 3 & 13; same logic applies, just for more flip-flops).
Regarding claim 19, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., wherein the first set of conductive structures is offset from the first boundary in the second direction;
the second set of conductive structures is offset from the first boundary and the second boundary in the second direction;
the third set of conductive structures is offset from the second boundary in the second direction (see claim 14; same logic applies, just for more flip-flops).
Regarding claim 20, the combined method of Yoon and Kang disclose in cited figures and related text, e.g., wherein the first set of conductive structures includes a first input pin and a first output pin for the first flip-flop (as is notoriously well-known and by definition; as was discussed numerous times above, transistor connections have to go to at least “metal1”/”first level”; that, by definition, includes all input and output pins; this is entirely standard);
the second set of conductive structures includes a second input pin and a second output pin for the second flip-flop (same as for “first set” above);
the third set of conductive structures includes a third input pin and a third output pin for the third flip-flop (same as for “first set” above);
the first input pin has a first width in the second direction (this is notoriously well-known; see claims 15 & 16; same logic applies);
the second input pin has the first width in the second direction (same as for “first input pin” above);
the third input pin has the first width in the second direction (same as for “first input pin” above);
at least a first conductive structure of the first set of conductive structures has a second width in the second direction different from the first width (see claims 15 & 16; having wider width to be able to transfer more current, is notoriously well-known, and an obvious thing to do, as was discussed regarding claims 15 & 16 above);
at least a first conductive structure of the second set of conductive structures has a third width in the second direction different from the first width (same as for “first set” above); and
at least a first conductive structure of the third set of conductive structures has a fourth width in the second direction different from the first width and the second width (same logic applies; choosing specific differing widths for specific differing current requirements, is a notoriously well-known feature; to elaborate briefly on the above, from Examiner’s personal experience: this logic/teaching/knowledge (use wider metal for more current) is taught in second year of undergraduate program of electrical engineering; in other words, this is “learner in the art” level knowledge, way below “skilled in the art”; hence, the usage of such knowledge (to use metals of differing widths, depending on the requirements of current, for any specific design application, is trivial and notoriously well-known).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2017/0292993) by Yoon et al (“Yoon”) in view of (US-2020/0266169) by Kang et al (“Kang”) as applied to claim(s) above, and further in view of (US-2019/0096809) by Lin et al (“Lin”).
Regarding claim 5, Yoon and Kang disclose substantially the entire claimed structure as recited in above claims, except “further comprising: fabricating a set of contacts of the first set of transistors on the front-side of the wafer”.
Lin discloses in FIGs. 8A-C and related text, e.g., “further comprising: fabricating a set of contacts (810.1/810.2; par. 42: S/D metal contacts) of the first set of transistors (the structure is repeatable for all transistors that have Source and Drain; hence, “first set of transistors”) on the front-side of the wafer (the default side for forming of transistors).”
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Yoon and Kang with “further comprising: fabricating a set of contacts of the first set of transistors on the front-side of the wafer” as taught by Lin, in order to reduce parasitic capacitance (par. 17).
Regarding claim 6, the combined method of Yoon, Kang and Lin disclose in cited figures and related text, e.g., further comprising:
fabricating a second set of vias (FIGs. 8A-C of Lin, 840 and their equivalents, on all nodes as needed in FIG. 6A of Yoon; hence, “second set of vias”) on the front-side of the wafer over the set of gates (gates are at the lower elevation, than vias; vias are also are above contacts; for visualization, see FIG. 6 of ‘045 reference; gate 64 is below contact 80; the vias of Lin are above that, as was shown by Lin in FIGs. 8A-C), the second set of vias being between the set of gates and the first set of conductive structures (gate is below, as was already discussed, and the “conductive structures” 850 are above the “via” 820; hence, “between”).
Regarding claim 7, the combined method of Yoon, Kang and Lin disclose in cited figures and related text, e.g., further comprising:
fabricating a third set of vias on the front-side of the wafer over the set of contacts, the third set of vias being between the set of contacts and the first set of conductive structures (basically, the same limitations as in claim 6, but there is now “third set of vias”; if one set is 2 vias, and another set is also 2 vias, then as long as there are 4 vias, the limitations are met; see FIG. 6A of Yoon; it shows A LOT of transistors; each transistor will have at least at least 2 vias associated with it (one for Source and one for Drain, per Lin’s teaching); hence, one transistor is already a set; and there are a lot of transistors in FIG. 6A of Yoon; hence, there is any number of such sets, including the “third set” that meets the same limitations as claim 6).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2017/0292993) by Yoon et al (“Yoon”) in view of (US-2020/0266169) by Kang et al (“Kang”) as applied to claim(s) above, and further in view of (US-2014/0259658) by Hsu et al (“Hsu”).
Regarding claim 8, Yoon and Kang disclose substantially the entire claimed structure as recited in above claims, except “further comprising: performing a cut metal process to remove at least one portion of one or more conductive structures of the first set of conductive structures”.
Hsu discloses in FIGs. 1A-B and related text, e.g., “further comprising: performing a cut metal process to remove at least one portion of one or more conductive structures of the first set of conductive structures (as shown in FIGs. 1A-B; the patterns are clearly marked as “A”, “B” and “Cut”)”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Yoon and Kang with “further comprising: performing a cut metal process to remove at least one portion of one or more conductive structures of the first set of conductive structures” as taught by Hsu, in order to fix the photoresist mask issue that occurs at smaller sizes, known as “native conflict” (par. 6).
Regarding claim 9, the combined method of Yoon, Kang and Hsu disclose in cited figures and related text, e.g., wherein performing the cut metal process to remove at least one portion of one or more conductive structures of the first set of conductive structures comprises:
etching the at least one portion of one or more conductive structures of the first set of conductive structures (see pars. 28, 37, 45, etc.; etching is inherent part of the process).
Regarding claim 10, the combined method of Yoon, Kang and Hsu disclose in cited figures and related text, e.g., disclose substantially the entire claimed structure as recited in above claims, but does not explicitly state “wherein the etching includes at least one of: plasma etching, reactive ion etching, chemical etching, dry etching or wet etching”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Yoon, Kang and Hsu with “further comprising: performing a cut metal process to remove at least one portion of one or more conductive structures of the first set of conductive structures”, since Hsu’s method is not limited to a particular type of etching of metal (Hsu simply says “etching” in every description), thus all of the above methods are considered to be compatible with Hsu’s method of “cut metal process” etching.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/23/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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