DETAILED ACTION
Election/Restrictions
Applicant’s election of Species 1d (figure 2C) and 2a (figure 7A), alleged to rad upon claims 1-20, in the reply filed on 1/2/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
However, claim 1, and its dependent claims 2-8, recite the limitation: “the second plurality of diagonal grid lines is free from including a via structure of the plurality of via structures”, which is not recited in elected figure 2C. In elected figure 2C the first and second diagonal grid lines intersect with via structures 200V. Therefore none of the grid liens are “free from including a via structure of the plurality of via structures”.
Consequently, the examined claim set is claims 9-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9, 12, and 13 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Igarashi et al., US 6,262,487.
Regarding claim 9, Igarashi (figures 3-5) teaches an integrated circuit (IC) structure comprising:
a plurality of first metal segments 1 in a first metal layer 1 of a semiconductor substrate (column 8, lines 25-28), the plurality of first metal segments 1 corresponding to first tracks 1;
a plurality of second metal segments 2 in a second metal layer 2 of the semiconductor substrate (column 8, lines 25-28) adjacent to the first metal layer 1, the plurality of second metal segments 2 corresponding to second tracks 2 perpendicular to the first tracks 1; and
a plurality of via structures 12/13/14 configured to electrically connect the plurality of first metal segments 1 to the plurality of second metal segments 2,
wherein locations of intersections of the first 1 and second 2 tracks define a grid comprising a first plurality of diagonal grid lines 3 alternating with a second plurality of diagonal grid lines 3, and the first plurality of diagonal grid lines 3 comprises:
an entirety of the intersection locations at which the via structures 12/13/14 of the plurality of via structures 12/13/14 are positioned; and
at least three via structures 12/13/14 of the plurality of via structures 12/13/14 positioned at contiguous intersection locations (figures 3 & 4-intersection 1 & 2 with 3).
With respect to claim 12, Igarashi (figures 3-5) teaches the contiguous intersection locations (figures 3 & 4-intersection 1 & 2 with 3) are adjacent locations along a single grid line 3 of the first plurality of diagonal grid lines 3 or among locations of adjacent grid lines 3 of the first plurality of diagonal grid lines 3.
As to claim 13, Igarashi (figures 3-5) teaches each of the first plurality of diagonal grid lines 3 and the second plurality of diagonal grid lines 3 has a positive slope with respect to one of the first 1 or second tracks 2, the grid comprises a third plurality of diagonal grid lines 4 intersecting with the first plurality of diagonal grid lines 3 and having a negative slope with respect to the one of the first 1 or second 2 tracks, and each intersection location at which a via structure 12/13/14 of the plurality of via structures 12/13/14 is positioned is separated from another intersection location at which another via structure 12/13/14 of the plurality of via structures 12/13/14 is positioned along one of a grid line 3 of the first plurality of diagonal grid lines 3 or a grid line 4 of the third 4 plurality of diagonal grid lines 4 by a distance equal to a multiple of a via pitch.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10, 11, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Igarashi et al., US 6,262,487, as applied to claim 9 above, in view of Bloom et al., 7,786,512.
In re claim 10, Igarashi (figure 3) teaches the first tracks 1 have a first pitch λ, the second tracks 2 have a second pitch λ, but Igarashi fails to teach the first pitch is greater than the second pitch, and a ratio of the first pitch to the second pitch is less than √3.
Bloom (figure 2) teaches the first pitch is greater than the second pitch (column 3, lines 6-14), and a ratio of the first pitch to the second pitch is less than √3.
Bloom (column 2, lines 6-14) teaches the first pitch 23 and second 19 can be adjusted in order to meet different requirements, as long as the total of 22+23=1F and Wcell+19=1F. so an embodiment exists wherein the first pitch is greater than the second pitch, and a ratio of the first pitch to the second pitch is less than √3. For example the first pitch could be .3F and the second pitch could be .2F, resulting in a ratio of 1.5F. Note the square root of 3 is about 1.7.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the pitch ratio of Bloom in the invention of Igarashi because Bloom teaches it puts more features into the same real estate (column 2, lines 33-37).
Concerning claim 11, Igarashi (figures 4-5) teaches the first metal layer 1 overlies the second metal layer 2.
Pertaining to claim 14, though Igarashi fails to teach the via pitch has a value ranging from 20 nanometers (nm) to 50 nm, It would have been obvious to one ordinary skill in the art at the time of the invention to optimize the via pitch through routine experimentation (MPEP 2144.05).
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Igarashi et al., US 6,262,487, in view of Bloom et al., 7,786,512.
In claim 15, Igarashi (figures 3-5) teaches an integrated circuit (IC) structure comprising:
a plurality of first metal segments 1 in a first metal layer 1 of a semiconductor substrate (column 8, lines 25-28), the plurality of first metal segments 1 corresponding to first tracks 1 having a first pitch λ;
a plurality of second metal segments 2 in a second metal layer 2 of the semiconductor substrate (column 8, lines 25-28) adjacent to the first metal layer 1, the plurality of second metal segments 2 corresponding to second tracks 2 perpendicular to the first tracks 1 and having a second pitch λ; and
a plurality of via structures 12/13/14 configured to electrically connect the plurality of first metal segments 1 to the plurality of second metal segments 2,
wherein a grid comprising a first plurality of diagonal grid lines 3 alternating with a second plurality of diagonal grid lines 3, and the first plurality of diagonal grid lines 3 comprises:
an entirety of the intersection locations (figures 3 & 4-intersection 1 & 2 with 3) at which the via structures 12/13/14 of the plurality of via structures 12/13/14 are positioned; and
at least three via structures 12/13/14 of the plurality of via structures 12/13/14 positioned at contiguous intersection locations (figures 3 & 4-intersection 1 & 2 with 3).
Igarashi fails to teach a ratio of the first pitch to the second pitch is less than locations of intersections of the first and second tracks, wherein a ratio of the first pitch to the second pitch is less than √3.
Bloom (figure 2) teaches the first pitch is greater than the second pitch (column 3, lines 6-14), and a ratio of the first pitch to the second pitch is less than √3.
Bloom (column 2, lines 6-14) teaches the first pitch 23 and second 19 can be adjusted in order to meet different requirements, as long as the total of 22+23=1F and Wcell+19=1F. so an embodiment exists wherein the first pitch is greater than the second pitch, and a ratio of the first pitch to the second pitch is less than √3. For example the first pitch could be .3F and the second pitch could be .2F, resulting in a ratio of 1.5F. Note the square root of 3 is about 1.7.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the pitch ratio of Bloom in the invention of Igarashi because Bloom teaches it puts more features into the same real estate (column 2, lines 33-37).
Regarding claim 16, Igarhashi (figures 4-5) teaches the plurality of first metal segments 1 in the first metal layer 1 overlies the plurality of second metal segments 2 in the second metal layer 2.
With respect to claim 17, Bloom (column 2, lines 6-14) teaches the ratio of the first pitch to the second pitch is greater than one. See the details noted above.
As to claim 18, Igarashi (figures 3-5) teaches each of the first plurality of diagonal grid lines 3 and the second plurality of diagonal grid lines 3 has a positive slope with respect to one of the first 1 or second tracks 2, the grid comprises a third plurality of diagonal grid lines 4 intersecting with the first plurality of diagonal grid lines 3 and having a negative slope with respect to the one of the first 1 or second 2 tracks, and each intersection location at which a via structure 12/13/14 of the plurality of via structures 12/13/14 is positioned is separated from another intersection location at which another via structure 12/13/14 of the plurality of via structures 12/13/14 is positioned along one of a grid line 3 of the first plurality of diagonal grid lines 3 or a grid line 4 of the third 4 plurality of diagonal grid lines 4 by a distance equal to a multiple of a via pitch.
In re claim 19, though Igarashi fails to teach the via pitch has a value ranging from 20 nanometers (nm) to 50 nm, It would have been obvious to one ordinary skill in the art at the time of the invention to optimize the via pitch through routine experimentation (MPEP 2144.05).
Concerning claim 20, Igarashi (figures 3-5) teaches the contiguous intersection locations (figures 3 & 4-intersection 1 & 2 with 3) are adjacent locations along a single grid line 3 of the first plurality of diagonal grid lines 3 or among locations of adjacent grid lines 3 of the first plurality of diagonal grid lines 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
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/DAVID A ZARNEKE/ Primary Examiner, Art Unit 2891 3/9/26
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