Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 11, 2023 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of device embodiment 1 (Fig. 1.2, claims 1-5, 7-12, 14-17, and 19-20) in the reply filed on March 2, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shu (US 2021/0005601). Claim 1, Shu discloses (see annotated Fig. 11 below) a structure comprising: a semiconductor fin (410, semiconductor fin, Para [0034]) extending (410 extends from 401) from a semiconductor substrate (401, bulk semiconductor substrate, Para [0032]) and having opposing sidewalls (left and right sidewalls of 410 in 415/417 sections, hereinafter “opposing”), wherein a lower portion (415, first fin portion, Para [0060]) of the semiconductor fin proximal to the semiconductor substrate has divots (divot are curved section of 415 of 410) within the opposing sidewalls (divot is within opposing); and an isolation region (region of 405/427/403, isolation regions/second isolation portion/sacrificial sidewall spaces, Para [0043]), hereinafter “isolation” on the semiconductor substrate (isolation is on 401) positioned laterally adjacent to the opposing sidewalls (isolation is laterally adjacent to opposing), wherein an upper portion (492, top sections of second find 417, Para [0043]) of the semiconductor fin extends above the isolation region (492 extends above isolation).
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Claim 3, Shu discloses (see annotated Fig. 11 above) the structure of claim 1, wherein the isolation region (isolation) includes at least one (isolation includes multiple 425) isolation layer (425, first isolation portion, Para [0043]). Claim 4, Shu discloses (see annotated Fig. 11 above) the structure of claim 3, wherein the isolation region (isolation) further includes sidewall spacers (403) positioned laterally immediately adjacent to the opposing sidewalls of the semiconductor fin (403 are laterally immediately adjacent opposing) on a middle portion of the semiconductor fin between the divots and the upper portion (403 is on a middle portion of 410 between divot and 417). Claim 5, Shu discloses (see annotated Fig. 11 above) the structure of claim 4, wherein the sidewall spacers (403 can be titanium oxide, Para [0039]) and the at least one isolation layer (425 is formed of 404 which can be silicon oxide, Para [0041]) include different isolation materials (425 can be titanium oxide, 425 can be titanium oxide). Claim 7, Shu discloses (see annotated Fig. 11 above) the structure of claim 1, wherein the semiconductor fin (410) has an end (bottom base of 410 is considered end, hereinafter “end”), and wherein the divots are within the opposing sidewalls and the end (divot is within opposing and end).
Claim(s) 1, 8-9, 11, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao (US 2016/0133624).
Claim 1, Liao discloses (Fig. 6) a structure comprising: a semiconductor fin (101, fins formed from silicon substrate 100, Para [0023] –[0024]) extending from (101 extends from 100) a semiconductor substrate (100, silicon substrate, Para [0023]) and having opposing sidewalls (left and right sidewalls of 101, hereinafter “opp”), wherein a lower portion (101b, lower portion, Para [0027]) of the semiconductor fin proximal to the semiconductor substrate (101b is proximal to 100) has divots (concave portions of opp, hereinafter “divot”) within the opposing sidewalls (divot is within opp); and an isolation region (105, insulator used a trench isolation, Para [0025]) on the semiconductor substrate (105 is on 100) positioned laterally adjacent to the opposing sidewalls (105 is positioned laterally adjacent to opp), wherein an upper portion (101a, upper portion, Para [0028]) of the semiconductor fin extends above the isolation region (101a extends above 105). Claim 8, Liao discloses (Fig. 6) the structure of claim 1, further comprising a fin-type field effect transistor having an active device region including the upper portion of the semiconductor fin (111can be gate of selection transistor formed on 101a, Para [0029]) and a gate structure (111, conductive layer may be gate electrode, Para [0029]) on the isolation region and positioned laterally adjacent to the opposing sidewalls (111 is on 105 and positioned laterally adjacent to opp). Claim 9, Liao discloses (Fig. 6) a structure comprising: a semiconductor substrate (100, silicon substrate, Para [0023]); semiconductor fins (101, fins formed from silicon substrate 100, Para [0023] –[0024]) extending from the semiconductor substrate (101 extends from 100), wherein the semiconductor fins have opposing sidewalls (left and right sidewalls of 101, hereinafter “opp”) and wherein lower portions (101b, lower portion, Para [0027]) of the semiconductor fins proximal to the semiconductor substrate (101b is proximal to 100) have divots (concave portions of opp, hereinafter “divot”) within the opposing sidewalls (divot is within opp); an isolation region (105, insulator used a trench isolation, Para [0025]) on the semiconductor substrate (105 is on 100) positioned laterally adjacent to the opposing sidewalls of the semiconductor fins (105 is positioned laterally adjacent to opp), wherein upper portions (101a, upper portion, Para [0028]) of the semiconductor fins extend above the isolation region (101a extends above 105); and a memory cell including multiple fin-type field effect transistors (DRAM can be formed of the fin structure of Fig. 6, Para [0029]), wherein each fin-type field effect transistor includes an upper portion of at least one of the semiconductor fins (111 is formed on 101a, where 111 can be used as gate electrode of a selection transistor of DRAM, Para [0029]). Claim 11, Liao discloses (Fig. 6) the structure of claim 9, wherein the isolation region (105) includes at least one isolation layer (there are multiple 105s as shown in Fig. 6).
Claim 14, Liao discloses (Fig. 6) the structure of claim 9, wherein the semiconductor fins (101) have ends (bottom end of 101), and wherein the divots are within the opposing sidewalls and the ends (divot are within bottom end of 101 and within opp).
Claim(s) 1-2 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2021/0305375). Claim 1, Kim discloses (Fig. 15) a structure comprising: a semiconductor fin (110, fin formed from semiconductor substrate 100, Para [0020]) extending from (110 extends from 100) a semiconductor substrate (100, semiconductor substrate, Para [0020]) and having opposing sidewalls (left and right sidewalls of 110, hereinafter “opp”), wherein a lower portion (113, middle section is considered lower portion) of the semiconductor fin (110) proximal to the semiconductor substrate (under broadest reasonable interpretation (BRI) 113 is proximal to 100) has divots (concave portions of 113, hereinafter “divot”) within the opposing sidewalls (divot is within opp); and an isolation region (120, isolation layer, Para [0035]) on the semiconductor substrate positioned laterally adjacent to the opposing sidewalls (120 is on 100 laterally adjacent to opp), wherein an upper portion (115, upper section, Para [0035]) of the semiconductor fin extends above the isolation region (115 extends above 120). Claim 2, Kim discloses (see annotated Fig. 15 below) the structure of claim 1, wherein, due to the divots, the lower portion (115) of the semiconductor fin has a base (base) that is narrower than at least a middle portion (mid) of the semiconductor fin between the divots and the upper portion (as can be seen in figure below base is narrower than mid which between divot and 115).
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Claim 15, Kim discloses (Fig. 15) a method comprising: forming semiconductor fins (110, fin formed from semiconductor substrate 100, Para [0020]) extending from (110 extends from 100) a semiconductor substrate (100, semiconductor substrate, Para [0020]), wherein the semiconductor fins have opposing sidewalls (left and right sidewalls of 110, hereinafter “opp”) and wherein lower portions (113, middle section is considered lower portion) of the semiconductor fins proximal to the semiconductor substrate (under broadest reasonable interpretation (BRI) 113 is proximal to 100) have divots (concave portions of 113, hereinafter “divot”) within the opposing sidewalls (divot is within opp); and forming an isolation region (120, isolation layer, Para [0035]) on the semiconductor substrate positioned laterally adjacent to the opposing sidewalls of the semiconductor fins (120 is on 100 laterally adjacent to opp), wherein upper portions (115, upper section, Para [0035]) of the semiconductor fins extend above the isolation region (115 extends above 120).
Allowable Subject Matter
Claims 10, 12, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Shu (US 2021/0005601), Liao (US 2016/0133624), Kim (US 2021/0305375), Li (US 2021/0151557), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 10, the lower portions of the semiconductor fins have bases that are narrower than at least middle portions of the semiconductor fins between the divots and the upper portions.
Regarding Claim 12, the isolation region further includes sidewall spacers positioned laterally immediately adjacent to the opposing sidewalls of the semiconductor fins on middle portions of the semiconductor fins between the divots and the upper portions
Regarding Claim 16 (from which claims 17-20 depend), forming of the sidewall spacers exposes horizontal surfaces of the semiconductor substrate; etching the exposed horizontal surfaces of the semiconductor substrate, wherein the etching increases a height of the semiconductor fins and causes the divots,
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li (US 2021/0151557) discloses (Figs. 1-12) a method of forming a FinFET structure using a dielectric layer 11 and etching the layer to form divots 7. Li does not disclose etching the exposed horizontal surfaces of a semiconductor substrate to form divots.
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/G.G.R/Examiner, Art Unit 2812