Prosecution Insights
Last updated: April 19, 2026
Application No. 18/448,515

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Aug 11, 2023
Examiner
RAMALLO, GUSTAVO G
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siliconware Precision Industries Co. Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
97%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
514 granted / 541 resolved
+27.0% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
36 currently pending
Career history
577
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 541 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on October 2, 2023. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Electronic Package With Improved Heat Dissipating and Manufacturing Method Thereof. Election/Restrictions Applicant's election with traverse of device embodiment 1 (Fig. 3A, claims 3 and 13) in the reply filed on December 30, 2025 is acknowledged. The traversal is on the ground(s) that the species I and II fall under a similar field of search and would not impose undue burden due to this assertion. This is not found persuasive because as stated in the restriction requirement of November 18, 2025, as Fig. 3A and 3B/3C have mutually exclusive characteristics (i.e. a continuous annular shape vs a discontinuous annular shape) and a search for one does not account for the other. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Murayama (US 2011/0291258). Claim 1, Murayama discloses (Fig. 3) an electronic package, comprising: a carrier structure (20, board, Para [0025]); an electronic element (40, semiconductor device, Para [0025]) disposed on the carrier structure (40 is disposed on 20); a heat conduction layer (60, thermal interface material, Para [0028]) formed on the electronic element (60 is formed on 40); and a heat dissipation member (72 of 70, second layer of heat radiation component, Para [0031]) having a recess portion (72 has a recess portion under it, hereinafter “recess”) and disposed on the heat conduction layer (72 is on 60), and the heat dissipation member covering the electronic element (72 covers 40), wherein an opening (lateral opening of recess, hereinafter “opening”) of the recess portion faces the electronic element (opening faces 40), the heat dissipation member is bonded to the heat conduction layer via (72 is bonded to 60 via 71) a heat dissipation layer (71 of 70, first layer of heat radiation component, Para [0031]), and the heat dissipation layer extends onto a wall surface of the recess portion (71 extends onto walls of recess). Claim 11, Murayama discloses (Fig. 3) a method of manufacturing an electronic package, comprising: disposing an electronic element (40, semiconductor device, Para [0025]) on a carrier structure (20, board, Para [0025]); forming a heat conduction layer (60, thermal interface material, Para [0028]) on the electronic element (60 is formed on 40); and disposing a heat dissipation member (72 of 70, second layer of heat radiation component, Para [0031]) having a recess portion (72 has a recess portion under it, hereinafter “recess”) on the heat conduction layer (72 is on 60) to cover the electronic element (72 covers 40), wherein an opening (lateral opening of recess, hereinafter “opening”) of the recess portion faces the electronic element (opening faces 40), the heat dissipation member (72) is bonded to the heat conduction layer (60) via a heat dissipation layer (72 is bonded to 60 via 71, first layer of heat radiation component, Para [0031]) , and the heat dissipation layer (71) extends onto a wall surface of the recess portion (71 extends onto walls of recess). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murayama (US 2011/0291258) as applied to claim 1 above, and further in view of Sreeram (US 2002/0175403). Claim 9, Murayama discloses the electronic package of claim 1. Murayama does not explicitly disclose wherein the heat conduction layer is made of a liquid metal. However, Sreeram discloses a thermal interface material of a package includes solder (abstract). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the solder material of Sreeram to the thermal interface of Murayama as solder can prevent damage during thermal cycling (Sreeram, abstract). Claim 19, Murayama discloses the method of claim 11. Murayama does not explicitly disclose wherein the heat conduction layer is made of a liquid metal. However, Sreeram discloses a thermal interface material of a package includes solder (abstract). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the solder material of Sreeram to the thermal interface of Murayama as solder can prevent damage during thermal cycling (Sreeram, abstract). Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murayama (US 2011/0291258) as applied to claim 1 above, and further in view of Cesulka (US Pat. No. 6,930,386). Claim 10, Murayama discloses the electronic package of claim 1. Murayama does not explicitly disclose wherein the heat dissipation layer is a gold layer. However, Cesulka discloses (Fig. 1) that a heat sink element 100 may be formed of gold (Col. 4, lines: 7-20). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Cesulka, including the specific material of the heat sink to the teachings of Murayama. The motivation to do so is that the combination yields the predictable results of allowing for the selection of a known material based on its suitability for the intended use as a heat radiator since gold is known to have good electrical and thermal conductivity (Cesulka, Col. 4, lines: 7-20). Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07. Claim 20, Murayama discloses the method of claim 11. Murayama does not explicitly disclose wherein the heat dissipation layer is a gold layer. However, Cesulka discloses (Fig. 1) that a heat sink element 100 may be formed of gold (Col. 4, lines: 7-20). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Cesulka, including the specific material of the heat sink to the teachings of Murayama. The motivation to do so is that the combination yields the predictable results of allowing for the selection of a known material based on its suitability for the intended use as a heat radiator since gold is known to have good electrical and thermal conductivity (Cesulka, Col. 4, lines: 7-20). Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07. Allowable Subject Matter Claims 2-3, 5-8, 12-13, and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Regarding Claim 2 (from which claims 3 and 5-8 depend), wherein the recess portion has an annular shape and surrounds the heat conduction layer. Regarding Claim 12 (from which claims 13 and 15-18 depend), wherein the recess portion has an annular shape and surrounds the heat conduction layer. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen (US 2005/0056926) discloses (Figs. 1A/2A) a heat dissipating structure 14 with a recess underlying it and where the overall structure has a ring shaped in Fig. 2A. However, Chen does not disclose that the recess has this ring shaped structure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /G.G.R/Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Aug 11, 2023
Application Filed
Jan 27, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12596093
ORGANIC SEMICONDUCTOR DEVICE WITH PROTECTIVE SPINEL OXIDE LAYER
2y 5m to grant Granted Apr 07, 2026
Patent 12598745
DOUBLE PATTERNING METHOD OF MANUFACTURING SELECT GATES AND WORD LINES
2y 5m to grant Granted Apr 07, 2026
Patent 12593449
VERTICAL NONVOLATILE MEMORY DEVICE INCLUDING GATE ELECTRODES WITH METAL-DOPED GRAPHENE
2y 5m to grant Granted Mar 31, 2026
Patent 12593450
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12588201
MEMORY DEVICE WITH INCREASED DENSITY AND METHOD OF FABRICATING THE SAME
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
97%
With Interview (+2.3%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 541 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month