Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Currently, claims 1-5 and 7-20 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Doornbos et al. (Pub. No. US 2021/0375874 A1, herein Doornbos).
Regarding claim 1, Doornbos discloses a semiconductor device, comprising: a substrate; a source region 23 disposed on the substrate; a drain region 27 disposed on the source region (Doornbos: Fig. 14 and paragraph [0057]); a floating main body region 25 disposed between the source region and the drain region, wherein the floating main body region vertically separates the source region from the drain region (Doornbos: Fig. 14 and paragraph [0058]); a gate region 26L laterally wrapped around the floating main body region, wherein the gate region wraps around a portion of the source region and a portion of the drain region (Doornbos: Figs. 14-16D, 25 and paragraph [0064]); and a gate dielectric 24 located between the floating main body region and the gate region, and insulated the floating main body region from the gate region, wherein a material of the gate dielectric has a negative capacitance (NC) feature (Doornbos: Figs. 14, 25 and paragraph [0063]).
Regarding claim 12, Doornbos discloses a method of forming a semiconductor device, comprising: providing a substrate; sequentially forming a source region 23, a floating main body region 25, and a drain region 27 on the substrate (Doornbos: Figs. 2-7 and paragraphs [0057]-[0058]); forming a gate region 26L wrapping around the floating main body region, wherein the gate region wraps around a portion of the source region and a portion of the drain region (Doornbos: Figs. 8-14, 25 and paragraphs [0064]-[0065]); and forming a gate dielectric 24 wrapping around the floating main body region before forming the gate region, wherein a material of the gate dielectric has a negative capacitance feature (Doornbos: Figs. 8-14, 25 and paragraphs [0063]-[0064]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 7-9 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (Pub. No. US 2022/0085043 A1, herein Zhu) in view of Verhulst (Pub. No. US 2008/0067495 A1).
Regarding claim 1, Zhu discloses a semiconductor device, comprising: a substrate 1001; a source region 1002 disposed on the substrate; a drain region 1004 disposed on the source region; a floating main body region 1003 disposed between the source region and the drain region, wherein the floating main body region vertically separates the source region from the drain region; a gate region 1005 laterally wrapped around the floating main body region (Zhu: Figs. 1a, 14a-14b and paragraphs [0044]-[0048]); and a gate dielectric 1005-1 located between the floating main body region and the gate region 1005-2, and insulated the floating main body region from the gate region (Zhu: Figs. 1a, 14a-14b and paragraph [0049]), wherein a material of the gate dielectric has a negative capacitance (NC) feature (Zhu: Figs. 1a, 14a-14b and paragraphs [0053]-[0055], [0101]-[0103]).
Zhu does not specifically show the gate region wraps around a portion of the source region and a portion of the drain region.
However, in the same field of endeavor, Verhulst teaches a semiconductor device, wherein the gate region 7-8 wraps around a portion of the source region 3 and a portion of the drain region 5 with an improved architecture having low power consumption (Verhulst: Fig. 2 and paragraphs [0009], [0089], [0095]).
Therefore, given the teachings of Verhulst, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Zhu in view of Verhulst by employing the gate wrapping portions of the S/D.
Regarding claim 2, Zhu in view of Verhulst teaches the semiconductor device of claim 1, further comprising a source line 1009 disposed on the substrate, wherein the source line is electrically connected to the source region (Zhu: Figs. 1a, 14a-14b and paragraph [0047]).
Regarding claim 3, Zhu in view of Verhulst teaches the semiconductor device of claim 2, further comprising a word line 1008-1012 extended outward from the gate region, wherein an extending direction of the word line is perpendicular to an extending direction of the source line (Zhu: Figs. 1a, 14a-14b and paragraph [0047]).
Regarding claim 4, Zhu in view of Verhulst teaches the semiconductor device of claim 2, further comprising an inter-layer dielectric (ILD) “Oxide” covering the source line (Zhu: Figs. 1a, 14a-14b and paragraphs [0045]-[0047]).
Regarding claim 5, Zhu in view of Verhulst teaches the semiconductor device of claim 4, wherein a top surface of the inter-layer dielectric is lower than an interface between the source region and the floating main body region (Zhu: Figs. 1a, 14a-14b and paragraphs [0045]-[0047]).
Regarding claim 7, Zhu in view of Verhulst teaches the semiconductor device of claim 1, further comprising an inter-layer dielectric 1010/1007 covering the gate region (Zhu: Figs. 1a, 14a-14b and paragraphs [0045]-[0050]).
Regarding claim 8, Zhu in view of Verhulst teaches the semiconductor device of claim 7, further comprising a bit line 1014 disposed on the inter-layer dielectric, wherein the bit line is electrically connected to the drain region (Zhu: Figs. 1a, 14a-14b and paragraph [0064]).
Regarding claim 9, Zhu in view of Verhulst teaches the semiconductor device of claim 8, further comprising an inter-metal dielectric (IMD) disposed on the bit line (Zhu: Fig. 1a and paragraphs [0052]-[0053]).
Regarding claim 12, Zhu in view of Verhulst teaches a method of forming a semiconductor device, comprising: providing a substrate 1001; sequentially forming a source region 1002, a floating main body region 1003, and a drain region 1004 on the substrate; forming a gate region 1005 wrapping around the floating main body region (Zhu: Figs. 1a-14b and paragraphs [0044]-[0048]); and forming a gate dielectric 1005-1 wrapping around the floating main body region before forming the gate region 1005-2 (Zhu: Figs. 1a-14b and paragraph [0049]), wherein a material of the gate dielectric has a negative capacitance feature (Zhu: Figs. 1a-14b and paragraphs [0053]-[0055], [0101]-[0103]).
Regarding claim 13, Zhu in view of Verhulst teaches the method of claim 12, wherein forming the source region, the floating main body region, and the drain region comprising sequentially depositing a source layer, a floating main body layer, and a drain layer on the substrate, followed by patterning the drain layer, the floating main body layer, and a portion of the source layer (Zhu: Figs. 1a-7c and paragraphs [0044]-[0048]).
Regarding claim 14, Zhu in view of Verhulst teaches the method of claim 13, wherein a portion of the source layer not patterned becomes a source line electrically connected to the source region (Zhu: Figs. 1a-7c and paragraphs [0044]-[0048]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Verhulst, as applied above, and further in view of Tsai et al. (Pub. No. US 2015/0295040 A1, herein Tsai).
Regarding claim 11, the previous combination does not specifically show an interfacial layer located between the floating main body region and the gate dielectric, and separates the floating main body region from the gate dielectric.
However, in the same field of endeavor, Tsai teaches a semiconductor device, wherein an interfacial layer is located between the floating main body region and the gate dielectric, and separates the floating main body region from the gate dielectric (Tsai: Figs. 19(b), 23(e) and paragraph [0057]; “A gate dielectric material 1902 including an interfacial layer and a high-k dielectric material is formed on the wafer, and a p-type-work-function metal material 1904 is formed on the gate dielectric material 1902, as shown in FIG. 19(b).”) to reduce interface defects, to improve carrier mobility, to control effective work function and to enhance reliability as the interfacial layer acts as a barrier.
Therefore, given the teachings of Tsai, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Tsai by employing the interfacial layer.
Response to Arguments
Applicant’s arguments with respect to claims 1-5 and 7-20 have been fully considered, but are found to be moot:
In response to applicant's argument, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Verhulst discloses a structure in which the gate dialectic layer 8 extends between the gate 7 and the S/D 3-5 in regions where the gate overlaps the S/D. Thus, Verhulst demonstrates that device structures may intentionally permit such overlap while maintaining the dielectric between the conductive regions. Accordingly, Verhulst evidences that designers recognize the gate-to-S/D overlap separated by a dielectric is an acceptable and known structural configuration, even though such structures inherently include some capacitive coupling. The disclosure of Verhulst therefore shows that avoiding overlap is not the only design approach pursued in the art. DRAM architectures involves balancing multiple competing considerations, including layout constraints, channel control, scalability, and capacitance. Where Zhu suggests minimizing overlap to reduce parasitic capacitance, and Verhulst shows configuration where overlap with an intervening dielectric is employed, the combined teachings merely reflect different known design options within the same technological field. Therefore, differences between the references do not teach away from the proposed modification but instead provide a clear reason for a skilled artisan to explore and implement known alternatives.
Furthermore, Doornbos is cited to provide additional support for the above understanding in the art, showing that a gate region 26L laterally wrapped around the floating main body region 25, wherein the gate region wraps around a portion of the source region 23 and a portion of the drain region 27.
Allowable Subject Matter
Claims 10 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
With respect to claim 10, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the gate dielectric further comprising an air gap in contact with the drain region, wherein a portion of the gate dielectric close to the source region and a portion of the gate dielectric close to the drain region appear to be an asymmetrical configuration.
With respect to claim 15, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein forming the gate dielectric and the gate region comprising conformally depositing a gate dielectric layer and a gate layer on an exposed surface of the source line, on sidewalls of the source region and the floating main body region, and on a sidewall and a top surface of the drain region, followed by etching back the gate dielectric layer and the gate layer. Claims 16-20 are included likewise as they depend from claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
March 12, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813