DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-13) in the reply filed on 3/11/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7, 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent No. 10,249,587 (Chen).
Chen discloses (at least Figs. 8 and 10)
7. (Original) A semiconductor device, comprising:
an electrical component 106 including a plurality of bump structures 156 / 108 formed over a surface of the electrical component 106;
a conductive layer 110 / 114 formed over the surface of the electrical component 106 with a first segment 110 of the conductive layer 110 / 114 electrically coupled between a first bump structure 156 / 108a and a second bump structure 156 / 108b of the plurality of bump structures 156 / 108;
a first electrical connection 114 coupled to the first bump structure 156 / 108a; and
a second electrical connection 154 coupled to the second bump structure 156 / 108b.
Chen discloses
12. (Original) The semiconductor device of claim 7, wherein the first bump structure 156 / 108a includes a bump.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over 2022/0005782 (Rodriguez) in view of Chen.
Rodriguez discloses (at least Figs. 1 and 2)
1. (Original) A semiconductor device, comprising:
an electrical component 14 including a first bump structure 32 and a second bump structure 36 formed over a surface of the electrical component 14;
a conductive layer 23 formed over the surface of the electrical component 14;
a lead frame interposer ([0023]), wherein the electrical component 14 is disposed on a paddle 20 of the lead frame interposer ([0023]);
a first bond wire 30 coupled between a first lead 18 of the lead frame interposer ([0023]) and the first bump structure 32; and
a second bond wire 30 coupled between a second lead 18 of the lead frame interposer ([0023) and the second bump structure 36.
Rodriguez fails to disclose
a conductive layer formed over the surface of the electrical component 14 with a first segment of the conductive layer electrically coupled between the first bump structure and second bump structure.
Chen teaches
A semiconductor device comprising:
a conductive layer 110 / 114 formed over the surface of the electrical component 106 with a first segment 110 of the conductive layer 110 / 114 electrically coupled between the first bump structure 156 / 108a and second bump structure 156 / 108b.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a segment of the conductive layer for coupling between bump structures in Rodriguez. The motivation would be to provide bump structures that share the same voltage state and to provide redundant bump structures as taught by Chen (column 6, line 60 to column 7, line 65).
Rodriguez discloses
5. (Original) The semiconductor device of claim 1, wherein the first bump structure 32 includes a bump.
Claim(s) 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Chen as applied to claim 1 above, and further in view of U.S. Patent Application Pub. No. 2014/0146506 (Miwa).
Rodriguez discloses (multiple wires, leads, and bump structures)
2. (Original) The semiconductor device of claim 1, further including:
a third bond wire 30 coupled between a third lead 18 of the lead frame interposer ([0023]) and a third bump structure 32 of the electrical component 14;
a fourth bond wire 30 coupled between a fourth lead 18 of the lead frame interposer ([0023]) and a fourth bump structure 36 of the electrical component 14;
Chen teaches (more than two die bond pads may be made redundant with each other)
wherein a second segment 110 of the conductive layer 110 / 114 is coupled between the third bump structure 156 / 108a and fourth bump structure 156 / 108b.
The combination of references fails to teach
a fifth bond wire coupled between the second lead and third lead.
Miwa teaches
A semiconductor device comprising:
a fifth bond wire 46a coupled between the second lead 16 and third lead 14.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a bond wire coupled between leads in the modified device of Rodriguez. The motivation would be so the leads are at equal potentials taught by Miwa ([0061]).
The combination of references teaches a daisy chain loop. The recited purpose to test continuity is of no patentable weight. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant. See, e.g., In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006) (motivation question arises in the context of the general problem confronting the inventor rather than the specific problem solved by the invention); Cross Med. Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424 F.3d 1293, 1323, 76 USPQ2d 1662, 1685 (Fed. Cir. 2005) ("One of ordinary skill in the art need not see the identical problem addressed in a prior art reference to be motivated to apply its teachings."); In re Lintner, 458 F.2d 1013, 173 USPQ 560 (CCPA 1972) (discussed below); In re Dillon, 919 F.2d 688, 16 USPQ2d 1897 (Fed. Cir. 1990), cert. denied, 500 U.S. 904 (1991) (discussed below).
3. (Original) The semiconductor device of claim 2, wherein a serial combination of the first lead, first bond wire, first bump structure, first segment of the conductive layer, second bump structure, second bond wire, second lead, fifth bond wire, third lead, third bond wire, third bump structure, second segment of the conductive layer, fourth bump structure, fourth bond wire, and fourth lead constitute a daisy chain loop to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Chen and Miwa as applied to claim 3 above, and further in view of U.S. Patent Application Pub. No. 2024/0030123 (Lee).
The combination of references fails to teach
4. (Original) The semiconductor device of claim 3, further including:
a voltage source coupled to the first lead; and
a current measuring device coupled to the fourth lead to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure.
Lee teaches
A semiconductor device comprising:
a voltage source coupled to the first lead ([0132]); and
a current measuring device coupled to the fourth lead ([0133]) to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure ([0134]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a voltage source and a current measuring device in the modified device of Rodriguez. The motivation would be to provide a connection resistance measurement method for detecting a connection failure where the area occupied by the components is reduced and the degree of freedom in arrangement of the components is increased as taught by Lee ([0096], [0131], [0143]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Chen as applied to claim 1 above, and further in view of U.S. Patent Application Pub. No. 2021/0217703 (Chuang).
The combination of references fails to teach
6. (Original) The semiconductor device of claim 1, wherein the first bump structure includes:
a conductive pillar; and
a bump formed over the conductive pillar.
Chuang teaches (at least Fig. 1)
A semiconductor device comprising:
wherein the first bump structure 105 / 106 / 107 includes:
a conductive pillar 105; and
a bump 107 formed over the conductive pillar 105.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a bump over a conductive pillar in the modified device of Rodriguez. The motivation would be to provide a rigid, highly conductive vertical connection between a semiconductor die and a package substrate or another chip with superior electrical performance and anti-electromigration capability as taught by Chuang ([0003]-[0008]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 7 above, and further in view of Rodriguez.
Chen fails to disclose
8. (Original) The semiconductor device of claim 7, further including a lead frame interposer, wherein the electrical component is disposed on a paddle of the lead frame interposer, and the first electrical connection comprises a first bond wire coupled between a first lead of the lead frame interposer and the first bump structure, and the second electrical connection comprises a second bond wire coupled between a second lead of the lead frame interposer and the second bump structure.
Rodriguez teaches
A semiconductor device comprising:
a lead frame interposer ([0023]), wherein the electrical component 14 is disposed on a paddle 20 of the lead frame interposer ([0023]), and
the first electrical connection comprises a first bond wire 30 coupled between a first lead 18 of the lead frame interposer ([0023]) and the first bump structure 32, and
the second electrical connection comprises a second bond wire 30 coupled between a second lead 18 of the lead frame interposer ([0023]) and the second bump structure 36.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a lead frame interposer in Chen. The motivation would be they are well-known in the package art as taught by Rodriguez ([0018]-[0029]). See MPEP 2144.03.
Claim(s) 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Rodriguez as applied to claim 8 above, and further in view of Miwa.
Rodriguez teaches (multiple bond wires, leads and bump structures)
9. (Original) The semiconductor device of claim 8, further including:
a third bond wire 30 coupled between a third lead 18 of the lead frame interposer ([0023]) and a third bump structure 32 of the plurality of bump structures 32 / 36;
a fourth bond wire 30 coupled between a fourth lead 18 of the lead frame interposer ([0023]) and a fourth bump structure 36 of the plurality of bump structures 32 / 36.
Chen discloses (more than two die bond pads may be made redundant with each other)
wherein a second segment 110 of the conductive layer 110 / 114 is coupled between the third bump structure 156 / 108a and fourth bump structure 156 / 108b.
The combination of references fails to teach
a fifth bond wire coupled between the second lead and third lead.
Miwa teaches
A semiconductor device comprising:
a fifth bond wire 46a coupled between the second lead 16 and third lead 14.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a bond wire coupled between leads in the modified device of Chen. The motivation would be so the leads are at equal potentials taught by Miwa ([0061]).
The combination of references teaches a daisy chain loop. The recited purpose to test continuity is of no patentable weight. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant. See, e.g., In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006) (motivation question arises in the context of the general problem confronting the inventor rather than the specific problem solved by the invention); Cross Med. Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424 F.3d 1293, 1323, 76 USPQ2d 1662, 1685 (Fed. Cir. 2005) ("One of ordinary skill in the art need not see the identical problem addressed in a prior art reference to be motivated to apply its teachings."); In re Lintner, 458 F.2d 1013, 173 USPQ 560 (CCPA 1972) (discussed below); In re Dillon, 919 F.2d 688, 16 USPQ2d 1897 (Fed. Cir. 1990), cert. denied, 500 U.S. 904 (1991) (discussed below).
10. (Original) The semiconductor device of claim 9, wherein a serial combination of the first lead, first bond wire, first bump structure, first segment of the conductive layer, second bump structure, second bond wire, second lead, fifth bond wire, third lead, third bond wire, third bump structure, second segment of the conductive layer, fourth bump structure, fourth bond wire, and fourth lead constitute a daisy chain loop to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over in Chen view of Rodriguez and Miwa as applied to claim 10 above, and further in view of Lee.
The combination of references fails to teach
11. (Original) The semiconductor device of claim 10, further including:
a voltage source coupled to the first lead; and
a current measuring device coupled to the fourth lead to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure.
Lee teaches
A semiconductor device comprising:
a voltage source coupled to the first lead ([0132]); and
a current measuring device coupled to the fourth lead ([0133]) to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure ([0134]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a voltage source and a current measuring device in the modified device of Chen. The motivation would be to provide a connection resistance measurement method for detecting a connection failure where the area occupied by the components is reduced and the degree of freedom in arrangement of the components is increased as taught by Lee ([0096], [0131], [0143]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 7 above, and further in view of Chuang.
The combination of references fails to teach
13. (Original) The semiconductor device of claim 7, wherein the first bump structure includes:
a conductive pillar; and
a bump formed over the conductive pillar.
Chuang teaches (at least Fig. 1)
A semiconductor device comprising:
wherein the first bump structure 105 / 106 / 107 includes:
a conductive pillar 105; and
a bump 107 formed over the conductive pillar 105.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a bump over a conductive pillar in Chen. The motivation would be to provide a rigid, highly conductive vertical connection between a semiconductor die and a package substrate or another chip with superior electrical performance and anti-electromigration capability as taught by Chuang ([0003]-[0008]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Pub. Nos. 2008/0242076 (Takiar), 2022/0344296 (Lo), U.S. Patent No. 5,554,940 (Hubacher), KR Pub. No. 100594229 (강인구) teach redundant bump structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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