DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/29/26 has been entered.
Response to Arguments
Applicant's arguments filed 7/29/26 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues Matsubara forms its pillar by ball bonding using gold and does not itself disclose forming that pillar from solder. In response, the rejection does not require bodily incorporating Matsubara’s complete fabrication process into Rodriguez. Rodriguez supplies the solder / bump teaching; Matsubara is being relied upon for the know pillar-under-bump configuration. The published application itself implies that a conductive pillar with a bump formed over the pillar is a “conventional” bump structure, including solder-type bump material over conductive pillar 120 ([0019]-[0025]). Applicant’s arguments against Matsubara are largely in isolation rather than the proposed combination.
Applicant’s arguments with respect to claim(s) 7 have been considered but are moot because the new ground of rejection does relies on a new reference for any teaching or matter specifically challenged in the argument.
Election/Restrictions
Claims 14-17, 20, 22, 23, 25 (and new claims 26-29) is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/11/26.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0005782 (Rodriguez) in view of U.S. Patent Application Publication No. 2025/0070076 (Matsubara) and U.S. Patent No. 10,249,587 (Chen).
Rodriguez discloses (at least Figs. 1 and 2)
1. (Previously Presented) A semiconductor device, comprising:
an electrical component 14 including a first bump structure 32 and a second bump structure 36 formed over a surface of the electrical component 14, wherein the first bump structure 32 includes a first solder bump, and wherein the second bump structure 36 includes a second solder bump ([0040]);
a conductive layer 23 formed over the surface of the electrical component 14;
a lead frame interposer ([0023]), wherein the electrical component 14 is disposed on a paddle 20 of the lead frame interposer ([0023]);
a first bond wire 30 coupled between a first lead 18 of the lead frame interposer ([0023]) and the first bump structure 32, wherein the first bond wire 20 is electrically and mechanically connected to a top surface of the first solder bump 21; and
a second bond wire 30 coupled between a second lead 18 of the lead frame interposer ([0023) and the second bump structure 36, wherein the second bond wire 30 is electrically and mechanically connected to a top surface of the second solder bump 36.
Rodriguez discloses solder and gold are substitutes ([0040]), but fails to disclose
wherein the solder bump formed on a first conductive pillar, and wherein the second solder bump formed on a second conductive pillar;
a conductive layer formed over the surface of the electrical component with a first segment of the conductive layer electrically coupled between the first bump structure and second bump structure.
Matsubara teaches
A semiconductor device, comprising:
wherein the bump structure 60 includes a bump 622 formed on a first conductive pillar 621 ([0087]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a pillar under the bump structures in Rodriguez. The motivation would be to proving a suitable bonding portions for a wire bond while improving the reliability and quality of the interconnection as taught by Matsubara ([0087]-[0089]). The proposed modification retains the disclosed solder as the bump material in Rodriguez and uses the conductive pillar of Matsubara as the underlying support. It does not require forming the conductive pillar of Matsubara from solder.
Chen teaches (at least Figs. 8 and 10)
A semiconductor device comprising:
a conductive layer 110 / 114 formed over the surface of the electrical component 106 with a first segment 110 of the conductive layer 110 / 114 electrically coupled between the first bump structure 156 / 108a and second bump structure 156 / 108b.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a segment of the conductive layer for coupling between bump structures in Rodriguez. The motivation would be to provide bump structures that share the same voltage state and to provide redundant bump structures as taught by Chen (column 6, line 60 to column 7, line 65).
Claim(s) 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Matsubara and Chen as applied to claim 1 above, and further in view of U.S. Patent Application Pub. No. 2014/0146506 (Miwa).
Rodriguez discloses (multiple wires, leads, and bump structures)
2. (Original) The semiconductor device of claim 1, further including:
a third bond wire 30 coupled between a third lead 18 of the lead frame interposer ([0023]) and a third bump structure 32 of the electrical component 14;
a fourth bond wire 30 coupled between a fourth lead 18 of the lead frame interposer ([0023]) and a fourth bump structure 36 of the electrical component 14;
Chen teaches (more than two die bond pads may be made redundant with each other)
wherein a second segment 110 of the conductive layer 110 / 114 is coupled between the third bump structure 156 / 108a and fourth bump structure 156 / 108b.
The combination of references fails to teach
a fifth bond wire coupled between the second lead and third lead.
Miwa teaches
A semiconductor device comprising:
a fifth bond wire 46a coupled between the second lead 16 and third lead 14.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a bond wire coupled between leads in the modified device of Rodriguez. The motivation would be so the leads are at equal potentials taught by Miwa ([0061]).
The combination of references teaches a daisy chain loop. The recited purpose to test continuity is of no patentable weight. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant. See, e.g., In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006) (motivation question arises in the context of the general problem confronting the inventor rather than the specific problem solved by the invention); Cross Med. Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424 F.3d 1293, 1323, 76 USPQ2d 1662, 1685 (Fed. Cir. 2005) ("One of ordinary skill in the art need not see the identical problem addressed in a prior art reference to be motivated to apply its teachings."); In re Lintner, 458 F.2d 1013, 173 USPQ 560 (CCPA 1972) (discussed below); In re Dillon, 919 F.2d 688, 16 USPQ2d 1897 (Fed. Cir. 1990), cert. denied, 500 U.S. 904 (1991) (discussed below).
3. (Original) The semiconductor device of claim 2, wherein a serial combination of the first lead, first bond wire, first bump structure, first segment of the conductive layer, second bump structure, second bond wire, second lead, fifth bond wire, third lead, third bond wire, third bump structure, second segment of the conductive layer, fourth bump structure, fourth bond wire, and fourth lead constitute a daisy chain loop to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Matsubara, Chen, and Miwa as applied to claim 3 above, and further in view of U.S. Patent Application Pub. No. 2024/0030123 (Lee).
The combination of references fails to teach
4. (Original) The semiconductor device of claim 3, further including:
a voltage source coupled to the first lead; and
a current measuring device coupled to the fourth lead to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure.
Lee teaches
A semiconductor device comprising:
a voltage source coupled to the first lead ([0132]); and
a current measuring device coupled to the fourth lead ([0133]) to test continuity of the first bump structure, second bump structure, third bump structure, and fourth bump structure ([0134]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a voltage source and a current measuring device in the modified device of Rodriguez. The motivation would be to provide a connection resistance measurement method for detecting a connection failure where the area occupied by the components is reduced and the degree of freedom in arrangement of the components is increased as taught by Lee ([0096], [0131], [0143]).
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Matsubara, Chen, Miwa, and Lee as applied to claim 4 above, and further in view of U.S. Patent Application Publication No. 2022/0208672 (Sharma).
The combination of references fails to teach
31. (New) The semiconductor device of claim 4, wherein the second lead is disposed on a first side of the lead frame interposer and the third lead is disposed on a second side of the lead frame interposer different from the first side.
Sharma teaches
A semiconductor device comprising:
wherein the second lead 410 is disposed on a first side of the lead frame interposer ([0025]) and the third lead 410 is disposed on a second side of the lead frame interposer ([0025]) different from the first side (Fig. 4, [0036]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to dispose a second lead on a first side and a third lead on a second side of the lead frame interposer in the modified device of Rodriguez. The motivation would be to extend the bond wire conductive path around the periphery of the package and implement a shield to reduce noise as taught by Sharma ([0035], [0036], [0041]).
Claim(s) 7, 9, 10, 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Chen and Sharma.
Rodriguez discloses (at least Figs. 1 and 2)
7. (Currently amended) A semiconductor device, comprising:
an electrical component 14 including a plurality of bump structures 32, 36 formed over a surface of the electrical component 14;
a conductive layer 23 formed over the surface of the electrical component 14;
a lead frame interposer ([0023]), wherein the electrical component 14 is disposed on a paddle 20 of the lead frame interposer ([0023]);
a plurality of first bond wires 30, wherein each of the first bond wires 30 is coupled between one of the plurality of leads 18 and one of the plurality of bump structures 32, 36.
Rodriguez fails to disclose
wherein the conductive layer includes a plurality of segments, and wherein each segment of the conductive layer is electrically coupled between a respective pair of the plurality of bump structures;
wherein the lead frame interposer includes a plurality of leads disposed along each of four sides of the lead frame interposer;
a plurality of second bond wires, each second bond wire coupled directly between two of the plurality of leads, wherein the plurality of first bond wires, the plurality of segments, and the plurality of second bond wires together form a continuous electrical path that includes at least one of the plurality of leads on each of the four sides of the lead frame interposer.
Chen teaches (at least Figs. 8 and 10)
A semiconductor device comprising:
a conductive layer 110 / 114 formed over the surface of the electrical component 106, wherein the conductive layer 110 / 114 includes a plurality of segments 110, 114, and wherein each segment of the conductive layer 110 / 114 is electrically coupled between a respective pair of the plurality of bump structures 156 / 106a, 156 / 106b.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of conductive layer segments for coupling between pairs of bump structures in Rodriguez. The motivation would be to provide bump structures that share a common voltage state and redundant electrical connections as taught by Chen (column 6, line 60 to column 7, line 65).
Sharma teaches (Figs. 2B, 4)
A semiconductor device, comprising:
wherein the lead frame interposer ([0025]) includes a plurality of leads 220 / 245, 410 disposed along each of four sides ([0027]) of the lead frame interposer ([0025], [0036]);
a plurality of second bond wires 240, 430, each second bond wire 240, 430 coupled directly between two of the plurality of leads 245, 410 ([0031]), wherein the plurality of first bond wires 222 / 230 (also in Fig. 5, landing points 525 on leads 520 are used to couple a bond wire between leads, [0037]), and the plurality of second bond wires 240, 430 together form a continuous electrical path ([0043], [0048], [0051]) that includes at least one of the plurality of leads 245, 410 on each of the four sides of the lead frame interposer ([0025]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the lead frame interposer in Rodriguez to include leads disposed along each of four sides and to directly couple selected leads by bond wires in a daisy-chain arrangement. The motivation would be to provide a continuous electrical path and an additional electrical path, to reduce equivalent resistance, IR drop, and electrical interference as taught by Sharma ([0035], [0036], [0041]). In addition, a shield is implemented to reduce noise effects.
Rodriguez discloses
9. (Currently amended) The semiconductor device of claim 7, wherein:
a first bond wire 30 of the plurality of first bond wires is coupled between a first lead of the plurality of leads 18 and a first bump structure of the plurality of bump structures 32;
a second bond wire 30 of the plurality of first bond wires is coupled between a second lead of the plurality of leads 18 and a second bump structure of the plurality of bump structures 36;
a third bond wire 30 of the plurality of first bond wires is coupled between a third lead of the plurality of leads 18 and a third bump structure of the plurality of bump structures 32;
a fourth bond wire 30 of the plurality of first bond wires is coupled between a fourth lead of the plurality of leads 18 and a fourth bump structure of the plurality of bump structures 36.
Chen teaches
a first segment of the plurality of segments 110 / 114 is coupled between the first bump structure 156 / 106a and the second bump structure 156 / 160b;
wherein a second segment of the plurality of segments 110 / 114 is coupled between the third bump structure 156 / 106a and fourth bump structure 156 / 106b.
Sharma teaches
a fifth bond wire 430 of the plurality of second bond wires is coupled between the second lead 410 and third lead 410 (or 520).
Rodriguez discloses first lead 18, first wire 30, first bump 32, second lead 18, second wire 30, second bump 36, third wire 30, third bump 32, fourth lead 18, fourth bump 36, fourth wire 30
Chen teaches
first segment and second segments 110 / 114
Sharma teaches
fifth wire 430, third lead 410, daisy chain loop 430
10. (Currently amended) The semiconductor device of claim 9, wherein a serial combination of the first lead, first bond wire, first bump structure, first segment, second bump structure, second bond wire, second lead, fifth bond wire, third lead, third bond wire, third bump structure, second segment, fourth bump structure, fourth bond wire, and fourth lead constitute a daisy chain loop.
Sharma teaches
30. (New) The semiconductor device of claim 7, wherein one of the plurality of second bond wires 430 is coupled between a first lead 410 disposed on a first side of the four sides of the lead frame interposer and a second lead 410 disposed on a second side of the four sides of the lead frame interposer, different from the first side (Fig. 4, [0036], [0037]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Chen and Sharma as applied to claim 10 above, and further in view of Lee.
The combination of references fails to teach
11. (Previously Presented) The semiconductor device of claim 10, further including:
a voltage source coupled to the first lead; and
a current measuring device coupled to the fourth lead.
Lee teaches
A semiconductor device comprising:
a voltage source coupled to the first lead ([0132]); and
a current measuring device coupled to the fourth lead ([0133], [0134]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a voltage source and a current measuring device in the modified device of Rodriguez. The motivation would be to provide a connection resistance measurement method for detecting a connection failure where the area occupied by the components is reduced and the degree of freedom in arrangement of the components is increased as taught by Lee ([0096], [0131], [0143]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez in view of Chen and Sharma as applied to claim 7 above, and further in view of Matsubara.
Rodriguez discloses solder bump structures 32, 36, and gold is a substitute ([0040]), but fails to disclose
13. (Currently amended) The semiconductor device of claim 7, wherein each of the plurality of bump structures includes a conductive pillar with a solder bump formed over the conductive pillar.
Matsubara teaches
A semiconductor device, comprising:
wherein the bump structure 60 includes a conductive pillar 621 with the bump 622 formed over the pillar 621 ([0087]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a pillar under the bump structures in the modified device of Rodriguez. The motivation would be to proving a suitable bonding portions for a wire bond while improving the reliability and quality of the interconnection as taught by Matsubara ([0087]-[0089]). The substation merely changes the known structure of the bump while preserving the interconnection in Rodriguez, yielding a predictable device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Pub. Nos. 2004/0130014 (Nakamura), 2012/0068338 (Haba), 2012/0181689 (Chua) teach bump on pillar and daisy chain structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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