DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-11 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication No. 2021/0066137) in view of Jung et al (US Publication No. 2007/0023842) and Chu et al (US Publication No 2020/0058558).
Regarding claim 1, Hsu discloses a method comprising: forming a first gate stack for a first transistor, wherein the first transistor has a first threshold voltage ¶0012-0013, and wherein the forming the first gate stack comprises: forming a first interfacial layer Fig 9A, 242 ¶0033 over a first semiconductor region Fig 9A, 210B, wherein the first interfacial layer has a first thickness Fig 9A, T4; and forming a first high-k dielectric layer Fig 14A, 244 over the first interfacial layer Fig 14A, 242, wherein the first high-k dielectric layer has a second thickness Fig 10A, T5; and forming a second gate stack for a second transistor, wherein the second transistor has a second threshold voltage different from the first threshold voltage¶0012-0013, and wherein the forming the second gate stack comprises: forming a second interfacial layer Fig 9B, 236 ¶0033 over a second semiconductor region Fig 9B, 210B’, wherein the second interfacial layer has a third thickness Fig 9B, T3; and forming a second high-k dielectric layer Fig 14B, 250 over the second interfacial layer Fig 14B, 236, wherein the second high-k dielectric layer has a fourth thickness Fig 14B, and wherein the first transistor differs from the second transistor by a difference selected from the group consisting of a first difference between the first thickness and the second thickness Fig 9A-9B ¶0049, a fourth difference between second dopants of the first high-k dielectric layer and the second high-k dielectric layer, and combinations thereof ¶0037-0039.Hsu discloses all the limitations but silent on the high k dielectric thickness and the dopants in the interfacial layer. Whereas Jung discloses a different in thickness between the high k layer Fig 1K, 120 in the first gate stack Fig 1K, 152 and the high k layer Fig 1K, 120/130 in the second gate stack Fig 1K, 154. While Chu discloses the difference in dopant concentration of the first interfacial layer and the second interfacial layer ¶0030, 0037-0039. Hsu, Jung and Chu are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the thickness and doping concentration of the dielectric layers to adjust the specific device threshold voltage.
Regarding claim 4, Hsu discloses wherein the first transistor differs from the second transistor by the first difference between the first thickness of the first interfacial layer and the third thickness of the second interfacial layer Fig 9A-9B, and wherein the method further comprises: forming p-type work function layers over the first high-k dielectric layer and the second high-k dielectric layer ¶0044-0046.
Regarding claim 5, Jung discloses wherein the first transistor differs from the second transistor by the second difference between the third thickness of the first high-k dielectric layer and the fourth thickness of the second high-k dielectric layer Fig 1K While Hsu discloses forming n-type work function layers over the first high-k dielectric layer and the second high-k dielectric layer Fig 20A-20B ¶0044-0046.
Regarding claim 6, Chu discloses wherein the first transistor differs from the second transistor by the third difference between first dopants of the first interfacial layer and the second interfacial layer¶0030, 0037-0039.
Regarding claim 7, Chu discloses doping the first interfacial layer with a first dipole dopant having a first dipole dopant concentration, and doping the second interfacial layer with a second dipole dopant having a second dipole dopant concentration different from the first dipole dopant concentration¶0030, 0037-0039.
Regarding claim 8, Chu discloses doping the first interfacial layer with a first dipole dopant having a first dipole dopant type, and doping the second interfacial layer with a second dipole dopant having a second dipole dopant type opposite the first dipole dopant type¶0030, 0037-0039.
Regarding claim 9, Chu discloses wherein the first transistor differs from the second transistor by the fourth difference between second dopants of the first high-k dielectric layer and the second high-k dielectric layer ¶0030, 0037-0039.
Regarding claim 10, Hsu and Chu discloses doping the first high-k dielectric layer with a first dipole dopant having a first dipole dopant concentration, and doping the second high-k dielectric layer with a second dipole dopant having a second dipole dopant concentration different from the first dipole dopant concentration Hsu ¶0037-0039 and Chu ¶0030, 0037-0039.
Regarding claim 11, Chu discloses doping the first high-k dielectric layer with a first dipole dopant having a first dipole dopant type, and doping the second high-k dielectric layer with a second dipole dopant having a second dopant type opposite the first dipole dopant type¶0030, 0037-0039.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication No. 2021/0066137) in view of Jung et al (US Publication No. 2007/0023842) and Chu et al (US Publication No 2020/0058558) and in further view of Guo et al (US Publication No. 2012/0061772).
Regarding claim 2, Hsu discloses all the limitations but silent on the formation of the mask. Whereas Gou discloses wherein the first interfacial layer and the second interfacial layer layers are formed by processes comprising: forming a first mask layer Fig 2D, 220 covering the second semiconductor region; forming the first interfacial layer Fig 2D, 224 using the first mask layer for masking; forming a second mask layer Fig 2E, 226 covering the first semiconductor region; and forming the second interfacial layer Fig 2E, 228 using the second mask layer for masking. Hsu, and Gou are analogous art because they are directed to semiconductor devices having gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Hsu and incorporate the teachings of Gou to improve manufacturing process and reduce device breakdown.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication No. 2021/0066137) in view of Jung et al (US Publication No. 2007/0023842) and Chu et al (US Publication No 2020/0058558) and in further view of Chen (US Publication No. 2023/0019366).
Regarding claim 3, Hsu discloses all the limitations but silent on the thinning of the dielectric layer. Whereas Chen discloses wherein the first high-k dielectric layer and the second high-k dielectric layer are formed by processes comprising: depositing the first high-k dielectric layer and the second high-k dielectric layer in a common deposition process;forming a first mask layer covering the second high-k dielectric layer; thinning the first high-k dielectric layer using the first mask layer for masking; forming a second mask layer covering the first high-k dielectric layer; and thinning the second high-k dielectric layer using the second mask layer for masking Fig 2G-2H ¶0032-0037 Hsu, and Chen are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Hsu and incorporate the teachings of Chen to achieve the prescribed thickness avoiding active region damage.
Allowable Subject Matter
Claims 12, 14-21 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration of Applicant’s response, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest “the first interfacial layer comprises a first dipole dopant therein with a first dipole dopant concentration, and wherein the first dipole dopant has a first peak dopant concentration in middle of the first interfacial layer; and a first high-k dielectric layer over the first interfacial layer; and a second transistor having a second threshold voltage different from the first threshold voltage, the second transistor comprising a second gate stack comprising: a second interfacial layer over the second semiconductor region, wherein the second interfacial layer has a second thickness different from the first thickness, and the second interfacial layer comprises a second dipole dopant therein with a second dipole dopant concentration, wherein the second dipole dopant has a second peak dopant concentration in middle of the second interfacial layer, and wherein the first peak dopant concentration is different from the second peak dopant concentration”, as recited in independent claim 12 and “a first interfacial layer, wherein the first interfacial layer comprises a first dipole dopant, and a first peak concentration of the first dipole dopant is at a first intermediate level between a top surface and a bottom surface of the first interfacial layer; and a first high-k dielectric layer over the first interfacial layer, wherein the first high-k dielectric layer has a first thickness, and the first high-k dielectric layer comprises a second dipole dopant therein, wherein a second peak concentration of the second dipole dopant is at a second intermediate level between a top surface and a bottom surface of the first high-k dielectric layer” as recited in independent claim 18.
Claims 14-17, 19-21 are also allowed as being directly or indirectly dependent of the allowed independent base claims.
Response to Arguments
Applicant's arguments filed 12/30/2025 have been fully considered but they are not persuasive.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Jung discloses modify the thickness and doping concentration of the dielectric layers improve device performance as described in paragraph 0006-0008.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811