DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “… a first floating diffusion region are formed on a first substrate (SB1);…the transfer gate transistor (TG) and the first floating diffusion region are located on a longitudinal top side of the photo diode (PD); the first floating diffusion region (FD1) is located on lateral circumference of the transfer gate transistor (TG);…the first substrate (SB1) and the second substrate (SB2) are packaged separately;…the first floating diffusion region (FD1) and the second floating diffusion region (FD2) are connected together by means of a through silicon via (CT) to form a floating diffusion region (FD) of the pixel cell…the “area of the source follow transistor (SF) of the pixel cell is greater than twice the area of the reset transistor (RST) or the row select transistor (RS)” of claim 1, the “longitudinal projections of the first floating diffusion region (FD1) and the second floating diffusion region (FD1) have an overlap region” of claim 3, the “second floating diffusion region (FD2) is located on lateral circumference of the source follow transistor (SF) and the reset transistor (RST)” of claim 5, and the “a signal processing logic circuit (LC) of the image sensor is formed on the second substrate (SB2)” of claim 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FD1, FD2, CT, and LC. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because FIG. 4 shows previously unshown relative structural sizes (e.g. FD1, CT, LC) and connections on a circuit schematic showing electrical connections via schematic symbols (e.g. RST, RS, SF, PD). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amendment filed 1/21/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: replacement FIG. 4 introduces new matter for at least the following reasons:
Floating diffusion 1 is shown as comprising three parts of various sizes that were not originally disclosed.
Floating diffusion 2 is shown as comprising three parts of various sizes that were not originally disclosed.
The newly illustrated connections between the parts of floating diffusion 1 and the transfer gate were not originally disclosed.
The newly illustrated connections between the parts of floating diffusion 2 and the reset and transfer gates were not originally disclosed.
The part of floating diffusion 2 not connected to anything in SB2 was not originally disclosed.
The illustrations of floating diffusion 1, floating diffusion 2, and the through silicon via are shown on a circuit schematic diagram and was not originally disclosed.
The newly added labels (e.g. FD1, FD2, CT, LC) were not originally disclosed and are not found in the specification.
The signal processing logic circuit is shown to occupy a specific leftmost portion of SB2 which was not originally disclosed.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Objections
Claim 3 is objected to because of the following informalities: “…the second floating diffusion region (FD1)…” should be “…the second floating diffusion region (FD2)…” Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US Pub. No. 2023/0268372) in view of Takeuchi (US Pub. No. 2009/0219422).
Regarding claim 1, in FIGs. 1-2, 7-8, 15, and 16B, Hsu discloses a double-layer stacked CMOS image sensor, which is a 4T-structured CMOS image sensor (paragraph [0030]), comprising a pixel cell in which a photo diode (PD, 106), a transfer gate transistor (TG, 116), and a first floating diffusion region (FD and connected wiring) are formed on a first substrate (SB1, 104A); wherein the photo diode (PD) is located at a longitudinal bottom of the first substrate (SB1, see FIG. 2); the transfer gate transistor (TG) and the first floating diffusion region are located on a longitudinal top side of the photo diode (PD); the first floating diffusion region is located on lateral circumference of the transfer gate transistor (TG, see FIG. 15); a source follow transistor (SF, 120), a reset transistor (RST, 118), a row select transistor (RS, 122), and a second floating diffusion region (bottom pad 1532) of the pixel cell are formed on a second substrate (SB2, 104b); the first substrate (SB1) and the second substrate (SB2) are packaged separately (104a and 104b are distinct IC chips, paragraph [0030]); the second substrate (SB2) is stacked on a top side of the first substrate (SB1), and the first floating diffusion region and the second floating diffusion region are connected together (electrically) by means of a through silicon via (1604) to form a floating diffusion region (FD) of the pixel cell.
Hsu appears not to explicitly disclose that the area of the source follow transistor (SF) of the pixel cell is greater than twice the area of the reset transistor (RST) or the row select transistor (RS).
There is no evidence showing the criticality of the claimed SF transistor area.
The semiconductor art well recognized that SF transistor area controls parameters critical for device performance, including random noise reduction and signal to noise ratio improvement. See Takeuchi, paragraphs [0093]-[0094]. SF transistor area is therefore an art recognized result affecting parameter.
According to well established patent law precedents (see, for example, M.P.E.P. § 2144.05), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to determine (for example by routine experimentation) the optimum area of the source follow transistor (SF) of the pixel cell.
Regarding claim 2, in FIGs. 1-2, 15, and 16B, Hsu discloses that a bottom side of the second substrate (SB2) is bonded to the top side of the first substrate (SB1).
Regarding claim 3, in FIGs. 1-2, 15, and 16B, Hsu discloses that longitudinal projections of the first floating diffusion region and the second floating diffusion region have an overlap region (at least in region 1526).
Regarding claim 4, in FIG. 2, Hsu discloses that the source follow transistor (SF), the reset transistor (RST), and the row select transistor (RS) are laterally arranged and formed on the second substrate (SB2).
Regarding claim 5, in FIG. 2, Hsu discloses that the second floating diffusion region (FD2) is located on lateral circumference of the source follow transistor (SF) and the reset transistor (RST).
Regarding claim 8, in FIGs. 1-2, 7-8, 15, and 16B, Hsu discloses that a signal processing logic circuit (LC) (104c, paragraph [0055]) of the image sensor is formed on the second substrate (SB2, 104b).
Response to Arguments
Applicant's arguments filed 1/21/2026 have been fully considered but they are not persuasive.
Applicant contends that “[t]he image sensor disclosed by Hsu(U2023/0268372) has a floating diffusion region (FD) formed as a whole in the first IC chip (104a), and there is no floating diffusion region in the second IC chip (104b). The floating diffusion region (FD) is not composed of a portion formed in the first IC chip (104a)) and another portion formed in the second IC chip (104b).
This argument is not persuasive. The scope of the claimed “second floating diffusion region (FD2)” is broad enough to be interpreted as a conductive region formed on the second substrate that is capable of holding charges transferred from the transfer gate. In at least FIG. 16B Hsu discloses such a conductive region (1532) formed on the second substrate (104b) that is capable of holding charges transferred from the transfer gate (108; 1532 is electrically connected to floating diffusion FD). As such, Hsu is commensurate with the scope of the claim.
Applicant contends that “…the publication date of Hsu (U2023/0268372) (8/24/2023) is later than the priority date of this patent application (10/18/2022), and the technical solution disclosed by Hsu (U2023/0268372) cannot be used to evaluate the inventiveness of this patent application.”
This argument is not persuasive. 35 U.S.C. 102(a)(2) requires that the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Hsu is available as prior art under 35 U.S.C. 102(a)(2) because it is an application for patent published or deemed published under section 122(b), both the filing date (5/20/2022) and the priority date (2/21/2022) are before the priority date of the present application, and Hsu is not one of the named inventors of the present application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891