Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II claims 1-10, 16-24 in the reply filed on 12/12/2025 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Ngo et al. ("Selective Sublimation of GaN and Regrowth of AlGaN to Co-Integrate Enhancement Mode and Depletion Mode High Electron Mobility Transistors," Journal of Crystal Growth 593, June 25, 2022)
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CLAIM 1. Ngo et al. discloses a method of fabricating a semiconductor structure using sublimation (Ngo et al. Abstract)1, comprising:
forming an opening through a mask layer (SiO2) over a wafer, the wafer comprising a substrate [Si], a channel layer [GaN] over the substrate , a barrier layer [Al(Gan)]over the channel layer, and a cap layer [GaN:Mg] over the barrier layer (Fig. 1b Note: In the context of the claimed process, the term "opening" precisely describes the region where the protective SiO2 mask material has been selectively removed to expose the underlying cap layer (i.e. “forming an opening”). While the cross-sectional view of the Applicant’s figures might schematically depict an exposed area between mask structures rather than a continuous "hole," as depicted in the prior art, a POSITA would immediately recognize that this patterned exposed region is methodology, structurally and functionally analogous to a defined aperture or opening within the mask layer for subsequent processing steps.);
subliming away a region of the cap layer within the opening in the mask layer, to form an opening in the cap layer down to a top surface of the barrier layer (Fig. 1b-c, Abstract, & Fig. 1 description),; and
depositing a conductive material into the opening in the cap layer (Fig. 1d - AuNi / AlTi).
CLAIM 2. Ngo et al. discloses the method of claim 1, wherein the barrier layer comprises aluminum nitride and the cap layer comprises gallium nitride (pp. 1 Col. 1-2 – Discloses both materials are known and used for the claimed layers.).
CLAIM 4. Ngo et al. discloses the method of claim 1, wherein the barrier layer comprises a first material, the cap layer comprises a second material, and the second material sublimes away at a lower temperature than the first material (Ngo et al. - Fig. 1b-c – Ngo et al. (Fig. 1b–c) discloses the same sublimation process applied to identical materials. According to MPEP § 2112, where the prior art teaches the identical chemical structure or process, the properties disclosed in the claim are necessarily present. Because the claimed properties flow from the known process taught by Ngo et al., they do not patentably distinguish the invention.)
CLAIM 5. Ngo et al. discloses the method of claim 1, wherein the subliming is performed in a vacuum environment inside a processing chamber within a temperature range (Ngo, p. 2 col. 1 – Sublimation is generally understood to be carried out under vacuum.).
CLAIM 6. Ngo et al. discloses the method of claim 5, wherein the subliming is performed in a vacuum environment at a pressure of greater than or equal to 10-8 Torr and a temperature of greater than or equal to 7500 C and less than or equal to 1300° C inside the processing chamber (Ngo, p. 2 col. 1 – For sublimation of GaN “the desired temperature between 850 and 900 ◦C is reached. Evaporation proceeds at pressure below 10-7 Torr”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ngo et al. ("Selective Sublimation of GaN and Regrowth of AlGaN to Co-Integrate Enhancement Mode and Depletion Mode High Electron Mobility Transistors," Journal of Crystal Growth 593, June 25, 2022) in view of Saxler et al. (US 20060255364 A1)
CLAIM 3. Ngo et al. discloses the method of claim 1, wherein the barrier layer may comprise aluminum nitride and however may be silent upon wherein the cap layer may comprise aluminum gallium nitride alloy. The claimed material combination, specifically an AlN barrier layer and an AlGaN cap layer, was a well-known configuration in HEMT fabrication at the time of the invention. For evidence of this specific material stack in HEMT structures, see Saxler et al. (paragraph 137 and Fig. 21B).
A POSITA would have found it obvious to select these materials because it is well-established that selecting a known material based on its art-recognized suitability for an intended use is a matter of ordinary skill and routine design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). Given that Saxler et al. demonstrates the suitability of an AlN barrier and AlGaN cap for HEMT performance, applying this known combination to the present invention would have yielded entirely predictable results.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hurkx et al. (US 20170154988 A1) in view of Ngo et al. ("Selective Sublimation of GaN and Regrowth of AlGaN to Co-Integrate Enhancement Mode and Depletion Mode High Electron Mobility Transistors," Journal of Crystal Growth 593, June 25, 2022)
CLAIM 1. Hurkx et al. discloses a method of fabricating a semiconductor structure comprising:
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forming an opening[s] 15/16 through a mask layer 14 over a wafer, the wafer comprising a substrate 2, a channel layer 4 over the substrate , a barrier layer 8 over the channel layer, and a cap layer [¶61 “[A] GaN cap layer may be located on the AlGaN layer 8 (not shown in the Figures).”]2 over the barrier layer 8 (Fig. 3A-C); and
depositing a conductive material 18/40 into the opening in the cap layer (Fig. 3D & ¶67).
Hurkx teaches etching through a mask to expose the barrier layer 8 but is silent on the specific technique of sublimation for this step. However, Hurkx notes that a GaN cap layer may be present. Ngo et al. describes the use of sublimation as a known process for forming openings GaN cap layers (Ngo et al., Fig. 1b-c, Abstract, & Fig. 1 description).
A Person of Ordinary Skill in the Art (POSITA) is presumed to be aware of all pertinent prior art, including the sublimation technique described by Ngo et al.. Given the established knowledge of using sublimation to remove and pattern GaN layers, it would be an obvious design choice for a POSITA to apply the sublimation process from Ngo et al. to the method of Hurkx. The motivation would be to predictably remove a region of the cap layer within the mask opening, thereby forming an opening down to the top surface of the barrier layer, should a GaN cap layer be present in the Hurkx structure. The result would be predictable, leveraging a known technique for its known purpose.
CLAIM 2. Hurkx et al. in view of Ngo et al. disclose a method of claim 1, wherein the barrier layer comprises aluminum nitride and the cap layer comprises gallium nitride (Ngo et al. pp. 1 Col. 1-2 & Hurkx ¶65.).
Claim(s) 3- 10, 16-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hurkx et al. (US 20170154988 A1) in view of Ngo et al. ("Selective Sublimation of GaN and Regrowth of AlGaN to Co-Integrate Enhancement Mode and Depletion Mode High Electron Mobility Transistors," Journal of Crystal Growth 593, June 25, 2022) in view of Saxler et al. (US 20060255364 A1).
CLAIM 3. Hurkx et al. in view of Ngo et al. disclose a method of claim 1, wherein the barrier layer may comprise aluminum nitride and however may be silent upon wherein the cap layer may comprise aluminum gallium nitride alloy. The claimed material combination, specifically an AlN barrier layer and an AlGaN cap layer, was a well-known configuration in HEMT fabrication at the time of the invention. For evidence of this specific material stack in HEMT structures, see Saxler et al. (paragraph 137 and Fig. 21B).
A POSITA would have found it obvious to select these materials because it is well-established that selecting a known material based on its art-recognized suitability for an intended use is a matter of ordinary skill and routine design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). Given that Saxler et al. demonstrates the suitability of an AlN barrier and AlGaN cap for HEMT performance, applying this known combination to the present invention would have yielded entirely predictable results.
CLAIM 4. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 1, wherein the barrier layer comprises a first material, the cap layer comprises a second material, and the second material sublimes away at a lower temperature than the first material (Ngo et al. - Fig. 1b-c – Ngo et al. (Fig. 1b–c) discloses the same sublimation process applied to identical materials. According to MPEP § 2112, where the prior art teaches the identical chemical structure or process, the properties disclosed in the claim are necessarily present. Because the claimed properties flow from the known process taught by Ngo et al., they do not patentably distinguish the invention.)
CLAIM 5. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 1, wherein the subliming is performed in a vacuum environment inside a processing chamber within a temperature range (Ngo, p. 2 col. 1 – Sublimation is generally understood to be carried out under vacuum.).
CLAIM 6. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 5, wherein the subliming is performed in a vacuum environment at a pressure of greater than or equal to 10-8 Torr and a temperature of greater than or equal to 7500 C and less than or equal to 1300° C inside the processing chamber (Ngo, p. 2 col. 1 – For sublimation of GaN “the desired temperature between 850 and 900 ◦C is reached. Evaporation proceeds at pressure below 10-7 Torr”).
CLAIM 7. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 4, further comprising, before depositing the conductive material, forming an insulating layer over a top surface of the barrier layer within the opening in the cap layer Hurkx et al. ¶3.
While Hurkx et al. does not explicitly illustrate the step-by-step formation of an insulating layer within the cap opening, Hurkx expressly teaches that the gate electrode may be "isolated by a dielectric layer" to form a Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) (Hurkx et al., ¶ [0003]). A POSITA would have found it obvious to form an insulating layer over the top surface of the barrier layer before depositing conductive material, as this is a known structural requirement for the MISHEMT device explicitly contemplated by Hurkx.
Under MPEP § 2143 (Rationale A), this involves nothing more than combining prior art elements according to known methods to yield predictable results. Specifically, the isolation of the gate electrode as described in the reference. Furthermore, under guidance of MPEP § 2144.07, it is within the ordinary skill of a worker in the art to include an insulating layer based on its art-recognized suitability for gate isolation. Because Hurkx identifies the dielectric layer as the defining feature of its MISHEMT embodiment, a POSITA would recognize the formation of this layer as a necessary and routine prerequisite to depositing the conductive gate material when a MISHEMT is desired.
CLAIM 8. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 4, further comprising, before depositing the conductive material, forming a recap layer of semiconductor materials over a top surface of the barrier layer within the opening in the cap layer (Ngo et al. Fig. 1F – “(f) alternative process with regrowth of AlGaN after pGaN sublimation.”).
CLAIM 9. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 1, wherein: forming the opening comprises forming at least two openings through the mask layer; and subliming away the region comprises subliming away a respective region of the cap layer within each of the at least two openings in the mask layer, to form at least two openings in the cap layer down to a top surface of the barrier layer (Ngo et al. Fig. 1b-c & Hurkx Figs. 3A-C – openings 16 & 15).
CLAIM 10. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 9, wherein depositing the conductive material comprises depositing the conductive material into the at least two openings in the cap layer (Ngo et al. Fig. 1b-d & Hurkx Figs. 3A-D).
CLAIM 16. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of fabricating a transistor using sublimation, comprising: forming openings through a mask layer over a wafer (Ngo et al. Fig. 1b-c (i.e. region uncovered by mask) & Hurkx Figs. 3A-C – openings 16 & 15), the wafer comprising a channel layer, a barrier layer, and a cap layer over a substrate (Ngo et al. Fig. 1b-c (i.e. region uncovered by mask) & Hurkx Figs. 3A-C); subliming away a first region of the cap layer (Ngo et al. – Abstract and Fig. 1 description – See regarding claim 1 for modification/rationale combination.), within a first opening in the mask layer, to form a first opening through the cap layer (Ngo et al. Fig. 1b-c (i.e. region uncovered by mask) & Hurkx Figs. 3A-C – openings 16 & 15),
etching away a second region of the cap layer, within a second opening in the mask layer, to form a second opening 36 through the cap layer (Hurkx Figs. 3C – openings 36 - ¶36); and depositing a conductive material 50 into the first opening for a gate of the transistor and into the second opening for a drain or a source of the transistor (Ngo et al. Fig. 1b-c & Hurkx Figs. 3A-C).
CLAIM 17. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 16, wherein: the wafer comprises the channel layer over the substrate, the barrier layer over the channel layer, and the cap layer over the barrier layer (Ngo et al. Fig. 1b-c (i.e. region uncovered by mask) & Hurkx Figs. 3A-C); the barrier layer comprises aluminum nitride and the cap layer comprises an aluminum gallium nitride alloy; and the first opening is formed through the cap layer and down to the barrier layer (Ngo et al. Fig. 1b-c & Hurkx Figs. 3A-C & See regarding claims 2&3 regarding selection of material. Per Ngo, Hurkx and Saxler the recited materials and combinations were known materials selected in the art for the purpose of HEMT design.).
CLAIM 18. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 16, wherein: the wafer comprises the barrier layer over the substrate, the channel layer over the barrier layer, a stop layer over the channel layer (from the various embodiments disclosed and claimed, the stop layer is not understood to be distinct from the claimed barrier layer. The barrier layer functiona as a stop layer during sublimation, thus the barrier is may also be the stop layer.), and the cap layer over the stop layer (e.g. barrier layer); the stop layer (e.g. barrier layer) comprises aluminum nitride and the cap layer comprises an aluminum gallium nitride alloy; and the first opening is formed through the cap layer and down to the stop layer (Ngo et al. Fig. 1b-c & Hurkx Figs. 3A-C & See regarding claims 2&3 regarding selection of material. Per Ngo, Hurkx and Saxler the recited materials were known materials selected in the art for the purpose of HEMT design.).
CLAIM 19. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 16, further comprising, before depositing the conductive material, forming an insulating layer within the first opening in the cap layer (Hurkx ¶3 - See regarding claim 7 when forming a MISHEMT).
CLAIM 20. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 16, further comprising, before depositing the conductive material, depositing semiconductor materials within the first opening in the cap layer (Ngo et al. Fig. 1F – “(f) alternative process with regrowth of AlGaN after pGaN sublimation.”).
CLAIM 21. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of fabricating a semiconductor structure using sublimation, comprising: forming an opening through a mask layer over a wafer (Ngo et al. Fig. 1b-c (i.e. region uncovered by mask) & Hurkx Figs. 3A-C – openings 16 & 15), the wafer comprising a substrate, a channel layer over the substrate, a barrier layer over the channel layer, and a cap layer over the barrier layer; subliming away a region of the cap layer, within the opening in the mask layer, to form an opening in the cap layer down to a top surface of the barrier layer(Ngo et al. – Abstract and Fig. 1 description – See regarding claim 1 for modification/rationale combination.)
forming an insulating layer over a top surface of the barrier layer within the opening in the cap layer; and depositing a conductive material into the opening in the cap layer (Hurkx ¶3 - See regarding claim 7 when forming a MISHEMT).
CLAIM 22. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 21, wherein the barrier layer comprises aluminum nitride and the cap layer comprises gallium nitride (Ngo et al. Fig. 1b-c & Hurkx Figs. 3A-C & See regarding claims 2&3 regarding selection of material. Per Ngo, Hurkx and Saxler the recited materials were known materials selected in the art for the purpose.).
CLAIM 23. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 21, wherein the barrier layer comprises aluminum nitride and the cap layer comprises an aluminum gallium nitride alloy (Ngo et al. Fig. 1b-c & Hurkx Figs. 3A-C & See regarding claims 2&3 regarding selection of material. Per Ngo, Hurkx and Saxler the recited materials were known materials selected in the art for the purpose of HEMT design.).
CLAIM 24. Hurkx et al. in view of Ngo et al. in view of Saxler disclose a method of claim 21, wherein the barrier layer comprises a first material, the cap layer comprises a second material, and the second material sublimes away at a lower temperature than the first material (Ngo et al. - Fig. 1b-c – Ngo et al. (Fig. 1b–c) discloses the same sublimation process applied to identical materials. According to MPEP § 2112, where the prior art teaches the identical chemical structure or process, the properties disclosed in the claim are necessarily present. Because the claimed properties flow from the known process taught by Ngo et al., they do not patentably distinguish the invention.)
Conclusion
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
1/6/2025
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Ngo et al. – Abstract: In the present study, the selective sublimation of the p-GaN cap layer of Al(Ga)N/GaN HEMTs is developed to replace the commonly used dry etching with no risk of damage in the barrier layer in order to fabricate enhanced mode transistors. Thanks to this approach, enhancement-mode transistors are fabricated with a threshold voltage between 0 V and +1.5 V depending on the barrier layer aluminum molar fraction and thickness. Furthermore, we show the benefit of the combination of selective sublimation with the regrowth of AlGaN to reduce access resistance in these transistors which can be co-integrated with depletion-mode devices fabricated in the same process in areas where p-GaN has been totally evaporated.
2 Hurkx et al. ¶ [[0061] The substrate 2 may, for instance, be a silicon substrate, although it is also envisaged that the substrate 2 may comprise a ceramic or glass. The substrate 2 has an AlGaN layer 8 located on a GaN layer 6. A number of buffer layers 4 comprising GaN may be located between the GaN layer and the underlying part of the substrate 2. As noted previously, these buffer layers 4 may form a super lattice that matches the lattice of the GaN layer 6 to underlying part of the substrate 2. In some examples, a GaN cap layer may be located on the AlGaN layer 8 (not shown in the Figures). In the present example, isolation regions 12 (e.g. trenches filled with dielectric or implanted regions) are provided for isolating the HEMT from other electrical devices on the substrate 2.