DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Group II, Claims 1-15 and 21-25, in the reply filed on 10/27/2025 is acknowledged.
Claim Objections
Claim 8 is objected to because of the following informalities: In claim 8, line 13, the recitation of “growing semiconductor material” should be changed to “growing a semiconductor material”, for clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5 and 21-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 2019/0237559).
Regarding claim 1, Cheng et al. discloses, as shown in Figures, a method comprising:
etching a cavity (332) in a vertical direction into a fin structure (320A,320B) including at least one semiconductor nanosheet (308) overlying a sacrificial layer (306), wherein the cavity is formed with a sidewall ([0075], Figure 5);
recessing the sacrificial layer by a lateral distance to a recessed surface (340, [0082], Figure 11);
forming an inner spacer (344) laterally adjacent to the recessed surface of the sacrificial layer, wherein the inner spacer has a lateral width greater than the lateral distance ([0085], Figure 13); and
growing epitaxial material in the cavity to form a source/drain region (338, [0081], Figure 13) laterally adjacent to the inner spacer.
Regarding claim 3, Cheng et al. discloses the inner spacer is formed with an internal core filled with air or a low-K material [0085].
Regarding claim 5, Cheng et al. discloses the recessed surface is distanced from an end of the semiconductor nanosheet by the lateral distance;
the end of the semiconductor nanosheet defines a vertical plane; and
the vertical plane passes through the inner spacer (Figure 13].
Regarding claim 21, Cheng et al. discloses, as shown in Figures, a method comprising:
forming a fin structure (320A,320B, [0076]) including a semiconductor nanosheet ([0075]), wherein the semiconductor nanosheet (308) extends in a lateral Y-direction from a first end to a second end, wherein the first end defines a first vertical plane perpendicular to the lateral Y-direction (Figure 5);
forming a first source/drain region (338, [0081], Figure 13) adjacent the first end of the semiconductor nanosheet;
forming a second source/drain region (338, [0081], Figure 13) adjacent the second end of the semiconductor nanosheet, wherein the first source/drain region is distanced from the second source/drain region in the lateral Y-direction (Figure 12);
forming a portion of a gate structure (HKMG) under the semiconductor nanosheet, the portion of the gate structure extending from a first end to a second end ([0087], Figure 15); and
forming an inner spacer (344) under the semiconductor nanosheet and abutting the first end of the portion of the gate structure, wherein the first vertical plane passes through the inner spacer (Figure 15).
Regarding claim 22, Cheng et al. discloses the inner spacer comprises forming a dielectric material surrounding a core formed by air or a low-K material [0085].
Claim(s) 1, 3, 5, 8, 13 and 21-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeong et al. (US 2021/0202758).
Regarding claim 1, Yeong et al. discloses, as shown in Figures, a method comprising:
etching a cavity (110) in a vertical direction into a fin structure (91) including at least one semiconductor nanosheet (54) overlying a sacrificial layer (52), wherein the cavity is formed with a sidewall ([0016]-[0017], Figure 7);
recessing the sacrificial layer by a lateral distance to a recessed surface (52R) ([0034], Figure 8);
forming an inner spacer (55,56) laterally adjacent to the recessed surface of the sacrificial layer, wherein the inner spacer has a lateral width greater than the lateral distance ([0037]-[0040], Figure 11); and
growing epitaxial material in the cavity to form a source/drain region (112, [0040], Figure 13) laterally adjacent to the inner spacer.
Regarding claim 3, Yeong et al. discloses the inner spacer is formed with an internal core filled with air or a low-K material ([0036], since the claim does not state how low is low, silicon oxide is considered as a low-K material).
Regarding claim 5, Yeong et al. discloses the recessed surface is distanced from an end of the semiconductor nanosheet by the lateral distance;
the end of the semiconductor nanosheet defines a vertical plane; and
the vertical plane passes through the inner spacer (Figure 12 shows a part of spacer 56 extends passing through the first vertical plane of the nanosheet 54).
Regarding claim 8, Yeong et al. discloses, as shown in Figures, a method comprising:
etching a cavity (110) in a vertical direction into a fin structure including a semiconductor nanosheet (54) overlying a sacrificial layer (52) ([0016]-[0017], Figure 7);
performing a lateral recess process to etch the sacrificial layer in a lateral direction perpendicular to the vertical direction, wherein the sacrificial layer is formed with a recessed surface (52R) ([0034], Figure 8);
depositing a first inner spacer layer (55) in the cavity, wherein the first inner spacer layer is located adjacent to the semiconductor nanosheet and on the recessed surface of the sacrificial layer (Figure 9);
removing the first inner spacer layer from the semiconductor nanosheet, wherein a remaining portion of the first inner spacer layer remains on the recessed surface of the sacrificial layer ([0037], Figure 10);
growing semiconductor material (112) on the semiconductor nanosheet ([0040], Figure 12);
depositing a second inner spacer layer (56, [0038]) in the cavity, wherein the second inner spacer layer is located adjacent to the semiconductor material and to the remaining portion of the first inner spacer layer (Figure 11); and
removing the second inner spacer layer from the semiconductor material, wherein a remaining portion of the second inner spacer layer remains on the remaining portion of the first inner spacer layer ([0039], Figure 11).
Regarding claim 13, Yeong et al. discloses the remaining portion of the first inner spacer layer (55) and the remaining portion of the second inner spacer layer (56) form an inner spacer;
the semiconductor nanosheet (54) terminates at an end abutting the cavity; and
the inner spacer extends laterally past the end of the semiconductor nanosheet and into the cavity (Figure 12 shows a part of spacer 56 extends passing through the first vertical plane of the nanosheet 54).
Regarding claim 21, Yeong et al. discloses, as shown in Figures, a method comprising:
forming a fin structure (91, [0020]) including a semiconductor nanosheet ([0016]-[0017]), wherein the semiconductor nanosheet (54) extends in a lateral Y-direction from a first end to a second end, wherein the first end defines a first vertical plane perpendicular to the lateral Y-direction (Figure 3B);
forming a first source/drain region (112, [0039]) adjacent the first end of the semiconductor nanosheet;
forming a second source/drain region (112, [0039]) adjacent the second end of the semiconductor nanosheet, wherein the first source/drain region is distanced from the second source/drain region in the lateral Y-direction (Figure 12);
forming a portion of a gate structure (120/122) under the semiconductor nanosheet, the portion of the gate structure extending from a first end to a second end ([0054]-[0055], Figure 16); and
forming an inner spacer (131,133,56) under the semiconductor nanosheet and abutting the first end of the portion of the gate structure, wherein the first vertical plane passes through the inner spacer (Figures 16 and 18-19 show a part of spacer 133 extends passing through the first vertical plane).
Regarding claim 22, Yeong et al. discloses forming the inner spacer comprises forming a dielectric material surrounding a core formed by air (133) or by a low-K dielectric material ([0052]-[0053], [0058], Figures 16-17).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4, 6-7 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2019/0237559).
Regarding claim 2, Cheng et al. discloses the claimed invention including the method as explained in the above rejection. Cheng et al. does not disclose the lateral distance and the lateral width as claimed. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 4, Cheng et al. discloses the claimed invention including the method as explained in the above rejection. Cheng et al. does not disclose the internal core has a lateral width and a vertical height as claimed. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Regarding claim 6, Cheng et al. discloses the claimed invention including the method comprises:
the end of the semiconductor nanosheet defines a vertical plane;
the inner spacer extends laterally from the recessed surface to an outer end;
the outer end is distanced from the vertical plane by a maximum lateral distance.
Cheng et al. does not disclose the maximum lateral distance is from 0.5 to 3 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Regarding claim 7, Cheng et al. discloses the outer end of the inner spacer is formed with an outer portion and a central recess;
the maximum lateral distance is defined at a location on the outer portion;
a minimum lateral distance is defined between the vertical plane and the central recess.
Cheng et al. does not disclose the minimum lateral distance is from 0 to 2 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Regarding claim 24, Cheng et al. discloses the claimed invention including the method of forming the inner spacer (344, Figures 14-15) comprises:
forming the inner spacer extending from an inner end to an outer end;
wherein the inner end abuts the first end of the portion of the gate structure (HKMG);
wherein the outer end is located a maximum lateral distance from the first vertical plane.
Cheng et al. does not disclose the maximum lateral distance is from 0.5 to 3 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Claim(s) 2, 4, 6-7, 23-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (US 2021/0202758).
Regarding claim 2, Yeong et al. discloses the claimed invention including the method as explained in the above rejection. Yeong et al. does not disclose the lateral distance and the lateral width as claimed. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 4, Yeong et al. discloses the claimed invention including the method as explained in the above rejection. Yeong et al. does not disclose the internal core has a lateral width and a vertical height as claimed. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Regarding claim 6, Yeong et al. discloses the claimed invention including the method comprises:
the end of the semiconductor nanosheet defines a vertical plane;
the inner spacer extends laterally from the recessed surface to an outer end;
the outer end is distanced from the vertical plane by a maximum lateral distance.
Yeong et al. does not disclose the maximum lateral distance is from 0.5 to 3 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Regarding claim 7, Yeong et al. discloses the outer end of the inner spacer is formed with an outer portion and a central recess;
the maximum lateral distance is defined at a location on the outer portion;
a minimum lateral distance is defined between the vertical plane and the central recess.
Yeong et al. does not disclose the minimum lateral distance is from 0 to 2 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Regarding claim 23, Yeong et al. discloses the claimed invention including the method of forming the inner spacer comprises forming the dielectric material surrounding a core. Yeong et al. does not disclose the core has a lateral width and a vertical height as claimed. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Regarding claim 24, Yeong et al. discloses the claimed invention including the method of forming the inner spacer comprises:
forming the inner spacer extending from an inner end to an outer end;
wherein the inner end abuts the first end of the portion of the gate structure;
wherein the outer end is located a maximum lateral distance from the first vertical plane.
Yeong et al. does not disclose the maximum lateral distance is from 0.5 to 3 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Regarding claim 25, Yeong et al. discloses the claimed invention including the method of forming the inner spacer comprises:
forming the outer end of the inner spacer with an outer portion and a central recess;
wherein the maximum lateral distance is defined at a location on the outer portion;
wherein a minimum lateral distance is defined between the first vertical plane and the central recess.
Yeong et al. does not disclose the minimum lateral distance is from 0 to 2 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, width, height, distance, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, width, height, distance, etc., or in combination of the parameters would be an unpatentable modification.
Allowable Subject Matter
Claims 9-12 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant' s claims 9-12 and 14-15 are allowable over the references of record because none of these references disclose or can be combined to yield the claimed method comprising removing the semiconductor material from the semiconductor nanosheet, as recited in claim 9; none of these references disclose or can be combined to yield the claimed method comprising depositing the second inner spacer layer in the cavity comprises trapping an air pocket within the second inner spacer layer, as recited in claim 14.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897