Prosecution Insights
Last updated: August 17, 2026
Application No. 18/449,348

DEVICES AND METHODS FOR FORMING DEVICES WITH INNER SPACERS

Final Rejection §102
Filed
Aug 14, 2023
Examiner
VU, HUNG K
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
879 granted / 1004 resolved
+19.5% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
30 currently pending
Career history
1035
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
43.6%
+3.6% vs TC avg
§102
37.2%
-2.8% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1004 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 26 and 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tak et al. (US 2017/0110554). Regarding claim 26 Tak et al. discloses, as shown in Figures 2A-29D, a method comprising: etching a cavity (T1) into a fin structure (FA) including at least one semiconductor nanosheet (NS) overlying a sacrificial layer (106S) (Figs. 7B, 27); recessing the sacrificial layer to a recessed surface (106R) (Figs. 14, 28); depositing a first inner spacer material layer (142A) on the recessed surface of the sacrificial layer (Fig. 15B, 29B); depositing a second inner spacer material (144A) on the first inner spacer material layer, wherein depositing the second inner spacer material layer comprises trapping an air pocket (AS1) within the second inner spacer material layer (Figs. 15B, 29B); and growing epitaxial material (162A, [0084]) in the cavity to form a source/drain region (Figs. 1B, 31, etc.) Regarding claim 30, Tak et al. discloses the method further comprising removing the second inner spacer material layer (144A) from an end of the semiconductor nanosheet, wherein a remaining portion of the first inner spacer material layer and a remaining portion of the second inner spacer material layer together form the inner spacer, wherein the air pocket (AS1) is encapsulated by the remaining portion of the second inner spacer material layer [Figs. 16B, 30B]. Allowable Subject Matter Claims 27-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 1-15 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Applicant' s claims 1-15 and 27-29 are allowable over the references of record because none of these references disclose or can be combined to yield the claimed method comprising growing a semiconductor material on an end of the semiconductor nanosheet, depositing inner spacer material adjacent to the semiconductor material and on the recessed surface, removing the semiconductor material from the end of the semiconductor nanosheet, and growing epitaxial material in the cavity to form a source/drain region, in combination with the remaining claimed limitation of claim 1; method comprising growing semiconductor material on the semiconductor nanosheet, depositing a second inner spacer layer adjacent to the semiconductor material and to the remaining portion of the first inner spacer layer, removing the second inner spacer layer from the semiconductor material, wherein a remaining portion of the second inner spacer layer remains on the remaining portion of the first spacer layer, and removing the semiconductor material from the semiconductor nanosheet, in combination with the remaining claimed limitation of claim 8; growing a semiconductor material on an end of the semiconductor nanosheet prior to depositing the second inner spacer material layer, wherein the second inner spacer material layer is deposited adjacent to the semiconductor material, and removing the semiconductor material from the end of the semiconductor nanosheet, as recited in claim 27; growing a semiconductor material on an end of the semiconductor nanosheet, and prior to growing the semiconductor material, removing the first inner spacer material layer from the end of the semiconductor nanosheet, wherein a remaining portion of the first inner spacer material layer remains on the recessed surface, as recited in claim 29. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACOB CHOI can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUNG K VU/ Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Aug 14, 2023
Application Filed
Jan 21, 2026
Non-Final Rejection mailed — §102
Feb 10, 2026
Interview Requested
Mar 17, 2026
Applicant Interview (Telephonic)
Mar 17, 2026
Examiner Interview Summary
May 18, 2026
Response Filed
Aug 03, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707631
DAMASCENE DIGIT LINES
2y 9m to grant Granted Aug 11, 2026
Patent 12702064
POWER DISTRIBUTION FOR STACKED ELECTRONIC DEVICES
3y 9m to grant Granted Aug 04, 2026
Patent 12690483
Semiconductor Chip Package Having Internal I/O Structures With Modulated Thickness To Compensate For Die/Substrate Warpage
4y 10m to grant Granted Jul 21, 2026
Patent 12685171
SEMICONDUCTOR PACKAGE WITH EXTENDED STIFFENER
4y 0m to grant Granted Jul 14, 2026
Patent 12685203
BUMP INTEGRATION WITH REDISTRIBUTION LAYER
2y 0m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.4%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1004 resolved cases by this examiner. Grant probability derived from career allowance rate.

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