DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Drawings 3
III. Claim Rejections - 35 USC § 103 3
A. Claims 1, 4-6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0023958 (“Todorobaru”) in view of US 6,355,492 (“Tanaka”) and US 2002/0047153 (“Nakamura”). 3
B. Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Todorobaru in view of Tanaka and Nakamura, as applied to claims 1 and 6 above, and further in view of US 4,183,040 (“Rideout”). 9
IV. Response to Arguments 10
Conclusion 13
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Drawings
Examiner incorrectly indicated that reference character 145 was not shown in the drawings, and thanks Applicant for pointing out that it is in Fig. 2, as filed. As such, the originally filed drawings are acceptable.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1, 4-6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0023958 (“Todorobaru”) in view of US 6,355,492 (“Tanaka”) and US 2002/0047153 (“Nakamura”).
With regard to claim 1, Todorobaru discloses, generally in Fig. 1,
1. A semiconductor device comprising:
[1] a semiconductor substrate 1 [¶ 86];
[2] an oxide film 7 [¶ 88] formed on the semiconductor substrate 1;
[3] a gate poly 8B, 8C [¶ 89] formed on a portion of the oxide film 7;
[4] a spacer 12/13 [¶ 90] formed to surround the gate poly 8B, 8C;
[5] a dielectric film 14/22/23 [¶¶ 91, 94] formed on the spacer 12;
[6] a first barrier metal 32 [“about 35 nm” of Ti (¶ 122)] formed on side surfaces of the oxide film 7, the gate poly 8B, 8C, the spacer 12, and the dielectric film 14/22/23 which are stacked, a surface of the semiconductor substrate 1, and a top surface of the dielectric film 14/22/23;
[7] a second barrier metal 33 [“about 70 nm TiN” (¶ 122)] formed on the first barrier metal 32;
[8] a metal plug [portion of 34 in contact openings 28, 29 (¶¶ 122, 129)] formed in a cavity formed by the second barrier metal 33;
[9] a metal layer [portion of 34 in on top surface of dielectric 23 (¶ 129)] formed on the second barrier metal 33 and the metal plug; and
[10] a passivation layer 36 [¶¶ 100, 131] formed on the metal layer 34,
[11] wherein a thickness of the first barrier metal 32 formed on the top surface of the dielectric film 14/22/23 is in a range of …[“about 35 nm” of Ti (¶ 122)], and
[12] wherein portions of the first barrier metal in contact with the semiconductor substrate, the spacer, the oxide film, and portions of the side surfaces of the dielectric film are silicided.
With regard to feature [11] of claim 1,
[11] wherein a thickness of the first barrier metal formed on the top surface of the dielectric film is in a range of from 15 nm to 25 nm.
Todorobaru does not teach the claimed range of 15 nm to 25 nm of the Ti barrier layer 32, instead giving an example of “about 35 nm” (¶ 122).
Tanaka, like Todorobaru, teaches Ti/TiN/W contacts 16 to the source/drain regions 15 of MOSFETs (Tanaka: Figs. 7B, 8A, 8B, 9; col. 11, line 35 to col. 12, line 67—especially Table 8). Tanaka further teaches an actual example in which the Ti layer thickness is 20 nm and the TiN layer 100 nm (Tanaka: Table 8), which as close to the 35 nm Ti and 70 nm TiN disclosed in Todorobaru (supra).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a thickness of 20 nm as the thickness of the Ti layer 32 of Todorobaru formed on the top surface of the dielectric 14/22/23 and in the contact openings 28, 29 because Tanaka teaches that a Ti layer thickness of 20 nm is a known thickness of Ti suitable for the same purpose of forming a Ti/TiN/W contact to the source/drain regions of a MOSFETs. As such, it amount to the substitution of one known thickness (“about 35 nm”) for another known thickness (20 nm) suitable for the same purpose.
Although Tanaka does not indicate that titanium silicide would be formed, as is done Todorobaru, the silicide would necessarily inherently form because Tanaka performs at least subsequent heat step at temperatures and time sufficiently high to form titanium silicide, i.e. at 700 ℃ to 800 ℃ for 10 minutes to 1 hours (Tanaka: col. 13, lines 40-47), while Todorobaru used an anneal at 650 ℃ for 10 minutes to form titanium silicide layer 35A at the Ti layer 32/substrate 1 interface (Todorobaru: ¶ 124; Fig. 1).
With regard to feature [12] of claim 1,
[12] wherein portions of the first barrier metal in contact with the semiconductor substrate, the spacer, the oxide film, and portions of the side surfaces of the dielectric film are silicided.
Todorobaru further discloses in Fig. 1 that the titanium silicide layer 35A contacts each of (1) the substrate 1, which was the source of the Si (Todorobaru: ¶ 124, supra), (2) the gate oxide 7, and (3) the spacer 12/13 at least adjacent to gate electrode 8B. This is consistent with Fig. 29 of Todorobaru, which shows that the heat treatment forming the titanium silicide extends upward to almost the height of the initially-deposited Ti layer (Todorobaru: ¶ 146).
As such, Todorobaru only fails to teach that the titanium silicide layer 35A contacts the dielectric film 14/22/23.
Nakamura, like Todorobaru, teaches a DRAM having MOSFETs with having Ti/TiN/W contacts 18a/18b/18c to the source/drain regions 15 of the MOSFETs (Nakamura: Fig. 16; ¶¶ 181, 183), wherein the Ti layer 18a is annealed to form a titanium silicide layer 20 (Nakamura: ¶¶ 188-189). Nakamura also teaches an embodiment in Fig. 44 (¶¶ 306-312) in which the titanium silicide 52a can be formed in contact with each of the substrate, gate oxide 10, and spacer 16/13, as in Todorobaru, and, in addition, on the lower sidewall portion of the dielectric layer 17a over the spacer 16/13.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the titanium silicide layer 35A in Todorobaru, slightly higher to touch the lower sidewall portion of the dielectric 14/22/23 because Nakamura teaches that the titanium silicide can be formed to contact the sidewall of the dielectric layer as well. As such, it is merely a matter of design choice. (See MPEP 2143.)
This is all of the limitations of claim 1.
Claim 4 reads,
4. (Original) The semiconductor device of claim 1, wherein
[1] the first barrier metal is formed of titanium,
[2] the second barrier metal is formed of titanium nitride, and
[3] the metal layer includes aluminum or copper.
With regard to claim 4, Todorobaru further discloses,
4. (Original) The semiconductor device of claim 1, wherein
[1] the first barrier metal 32 is formed of titanium [¶ 122],
[2] the second barrier 33 metal is formed of titanium nitride [¶ 122], and
[3] … [not taught] …
With regard to feature [3] of claim 4, Todorobaru does not disclose Al or Cu as the metal layer 34, instead disclosing tungsten (¶ 129).
Tanaka further teaches that the metal fill for a source/drain contact 15 in an opening 26 can include Ti/TiN/Al alloy (Tanaka: ¶ 44; Figs. 7A-7B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to us aluminum instead of tungsten as the metal layer 34 in Todorobaru because it would be the substitution of one known metal for another known metal used for the same purpose of forming a metal fill on a Ti/TiN barrier layer for a contact to a source/drain region of a MOSFET. As such, the selection of aluminum amounts to obvious material choice. (See MPEP 2144.07.)
With regard to claim 5, Todorobaru further discloses,
5. The semiconductor device of claim 1, wherein a thickness of the second barrier metal formed on the first barrier metal is in a range of from 70 nm to 90 nm [Todorobaru: “about 70 nm TiN” (¶ 122)].
With regard to claim 6, Todorobaru modified to use the 20 nm thickness for the Ti barrier layer 32, as taught by Tanaka, and modified to further form the barrier layer 32 to contact “portions of the side surfaces of the dielectric film 14/22/23”, as taught by Nakamura, as explained under claim 1 above, teaches,
6. A semiconductor device comprising:
[1] a semiconductor substrate 1 [¶ 86];
[2] an oxide film 7 [¶ 88] formed on the semiconductor substrate 1;
[3] a gate poly 8B, 8C [¶ 89] formed on a portion of the oxide film 7;
[4] a spacer 12/13 [¶ 90] formed to surround the gate poly 8B, 8C;
[5] a dielectric film 14/22/23 [¶¶ 91, 94] formed on the spacer 12;
[6] a barrier metal 32 [“about 35 nm” of Ti (¶ 122)] formed on side surfaces of the oxide film 7, the gate poly 8B, 8C, the spacer 12, and the dielectric film 14/22/23 which are stacked, a surface of the semiconductor substrate 1, and a top surface of the dielectric film 14/22/23;
[7] a metal layer 34 [¶ 129] formed on the barrier metal 32 and the metal plug; and
[8] a passivation layer 36 [¶¶ 100, 131] formed on the metal layer 34,
[9] wherein a thickness of the barrier metal 32 formed on the top surface of the dielectric film 14/22/23 is in a range of 15 nm to 25 nm [i.e. 20 nm of Ti as taught by Tanaka (supra)], and
[10] wherein portions of the barrier metal 32 in contact with the semiconductor substrate 1, the spacer 12/13, the oxide film 7, and portions of the side surfaces of the dielectric film 14/22/23 are silicided [as taught by Nakamura (supra)].
Claim 9 reads,
9. The semiconductor device of claim 6, wherein
[1] the barrier metal is formed of titanium, and
[2] the metal layer includes aluminum or copper.
As explained above, Todorobaru teaches that the barrier metal 32 is titanium (¶ 122).
With regard to feature [2] of claim 9, Todorobaru does not disclose Al or Cu as the metal layer 34, instead disclosing tungsten (¶ 129).
Tanaka further teaches that the metal fill for a source/drain contact 15 in an opening 26 can include Ti/TiN/Al alloy (Tanaka: ¶ 44; Figs. 7A-7B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to us aluminum instead of tungsten as the metal layer 34 in Todorobaru because it would be the substitution of one known metal for another known metal used for the same purpose of forming a metal fill on a Ti/TiN barrier layer for a contact to a source/drain region of a MOSFET. As such, the selection of aluminum amounts to obvious material choice. (See MPEP 2144.07.)
B. Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Todorobaru in view of Tanaka and Nakamura, as applied to claims 1 and 6 above, and further in view of US 4,183,040 (“Rideout”).
Claims 2 and 7 read,
2. (Original) The semiconductor device of claim 1, further comprising: a back metal formed on a bottom of the semiconductor substrate.
7. (Original) The semiconductor device of claim 6, further comprising: a back metal formed on another surface of the semiconductor substrate.
The prior art of Todorobaru in view of Tanaka and Nakamura, as explained above, teaches each of the features of claims 1 and 6.
Todorobaru does not disclose a back metal.
Rideout, like each of Todorobaru, Tanaka, and Nakamura, teaches a semiconductor device including a MOSFET 7/13/24/25 (Rideout: col. 10, lines 32-37). Rideout further teach that “as known in the art, electrical connection to the semiconductive substrate may be provided by a metallic layer deposited by evaporation onto the lower or backside surface of semiconductive substrate 2.” (Rideout: col. 15, lines 17-21; emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a metallic layer on the back surface of the substrate 1 in Todorobaru, in order to form an electrical connection to the substrate 1, as taught to be known in the art in Rideout (id.).
This is all of the limitations of claims 2 and 7.
IV. Response to Arguments
Applicant’s arguments filed 04/20/2026 have been considered but they are not fully persuasive.
The amendment to each of claims 1 and 6 to include the features of claims 3 and 8, respectively (Remarks: p. 10, lines 5-8) overcomes the prior art rejections premised on each of Yamaha and Lee. However, the rejection of claims 3 and 8 over Todorobaru in view of Tanaka and Nakamura stands.
1. Applicant argues that the combination of references does not teach the features of claims 3 and 8 (now in claims 1 and 6, respectively) because the layer 52a in Nakamura is polysilicon. Examiner respectfully disagrees. First, the embodiment shown in Figs. 43 and 44 of Nakamura shows—in Fig. 43—the titanium 18a/polysilicon 52 stack before the anneal that reacts the titanium 18a with the polysilicon 52 (as well as the silicon of the source/drain regions 15b). Fig. 44 shows the structure after the anneal. The polysilicon layer 52 of Fig. 43 becomes 52a in Fig. 4, during the reaction of the titanium metal with each of the polysilicon layer 52 and the silicon surface of the source/drain regions. Notably, Fig. 44 shows that the entire titanium layer 18a has thinned because it reacted with the polysilicon layer 52 to form titanium silicide 52a leaving behind the excess thickness of titanium 18a on the top surface around the opening and the upper portion of the sidewall of the opening. However, as also shown in Fig. 44, the entire thickness of the titanium layer 18a on the lower portion of the sidewall of the opening is shown to be consumed in forming titanium silicide. What exactly does Applicant think has happened to the titanium layer 18a on the sidewall of the opening, when Nakamura explains that the remaining portion shown in Fig. 44 is that “part” of the titanium layer 18a that did not react with the polysilicon layer 52—due to its “excessive volume”—in forming the titanium silicide layer 52a. The excessive volume of titanium is precisely why the polysilicon is entirely consumed and excess titanium layer 18a thickness remains behind. In fact, Nakamura states:
[0310] Then, a polycrystal silicon film 52 is formed by deposition (FIG. 43). A polycrystal silicon film 52 reacts with a titanium film [18a] having an excessive volume in a heat treatment step as will be discussed below in order to eliminate any residual titanium.
[0311] Then, a heat treatment process is carried out as in the case of the embodiment 6. As a result of the heat treatment, the titanium film 18a on the bottom of the contact holes 21 partly reacts with silicon in the semiconductor substrate 1 (at the bottom), while the remain[ing] of the titanium film 18a reacts with the polycrystal silicon film 52 (at the top). Thus, the titanium film 18a is partly consumed by the reaction with the polycrystal silicon film 52 at the top thereof so that only the remaining titanium film 18a reacts with silicon in the semiconductor substrate 1. …
[0312] While part of the titanium film 18a that does not react with the polycrystal silicon film 52 will remain on the lateral walls of the contact holes 21 and the top surface of the TEOS oxide film 17d, …
(Nakamura: ¶¶ 310-312; emphasis added)
To the extent that there exists some portion of the layer denoted 52a shown in Fig. 44—directly contacting the sidewalls of the lower portion of the opening that is the reaction product of the entirety of the thickness of the titanium layer 18a and the polysilicon layer 52 shown in Fig. 43—retains any polysilicon, the rest of 52a directly contacting the sidewalls of the insulating layers making up the contact opening is—to be sure—titanium silicide, not polysilicon. Thus, Applicant’s assertion that 52a is polysilicon is contrary to the factual evidence disclosed in Nakamura.
2. Applicant further argues that Nakamura does not disclose the claimed contact points premised on the errant notion that 52a is not or does not contain titanium silicide (Remarks: p. 12). For the same reasons as explained above, Examiner respectfully disagrees. Fig. 44 of Nakamura unambiguously shows that the portion of the layer denoted 52a—which is or includes titanium silicide—directly contacts the sidewalls of the lower portion of the opening, thereby directly contacting the claimed elements forming the sidewalls of the opening at each of the claimed contact points, as explained in the rejection.
3. Applicant argues that combination of references and rationale for combining the references is improper for the following reason:
[1] The Examiner's assertion that forming silicide higher to touch the dielectric is a "matter of design choice" is unsupported. [2] In the present invention, the silicidation of the side surfaces of the dielectric film is a specific structural feature that stabilizes threshold voltage and minimizes dispersion after electron irradiation - a technical effect not suggested by the prior art.
(Remarks: p. 12)
Examiner respectfully disagrees. With regard to [1], the reason for combining the references is proper as evidenced by Nakamura. To repeat, Nakamura also teaches an embodiment in Fig. 44 (¶¶ 306-312) in which the titanium silicide 52a can be formed in contact with each of the substrate, gate oxide 10, and spacer 16/13, as in Todorobaru, and, in addition, on the lower sidewall portion of the dielectric layer 17a over the spacer 16/13.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the titanium silicide layer 35A in Todorobaru, slightly higher to touch the lower sidewall portion of the dielectric 14/22/23 because Nakamura teaches that the titanium silicide can be formed to contact the sidewall of the dielectric layer as well. As such, it is merely a matter of design choice. (See MPEP 2143.)
With regard to [2], the fact that the Instant Inventors have recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985). In other words, there is no requirement for the prior art to recognize the advantage that Applicant has, i.e. that “the silicidation of the side surfaces of the dielectric film is a specific structural feature that stabilizes threshold voltage and minimizes dispersion after electron irradiation - a technical effect not suggested by the prior art” (supra).
Based on the foregoing, Applicant’s arguments are not found persuasive.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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