DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Drawings 5
IV. Specification 6
V. Claim Objections 6
VI. Claim Rejections - 35 USC § 102 6
A. Claims 1, 4, 6, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,146,998 (“Yamaha”). 7
VII. Claim Rejections - 35 USC § 103 9
A. Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaha in view of US 4,183,040 (“Rideout”). 9
B. Claims 1, 6, and 9 are rejected under 35 U.S.C. 103 as being anticipated by US 5,801,096 (“Lee”) in view of Yamaha. 10
C. Claims 1, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0023958 (“Todorobaru”) in view of US 6,355,492 (“Tanaka”). 12
D. Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Todorobaru in view of Tanaka, as applied to claims 1 and 6, above, and further in view of US 2002/0047153 (“Nakamura”). 15
Conclusion 16
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant's election with traverse of invention group I in the reply filed on 01/14/2026 is acknowledged. The traversal is on the following ground(s) that are not found persuasive for the following reasons:
Applicant argues that the product and process claims are not distinct under MPEP § 806.05(f) because the “materially different process” must not be “speculative” (Remarks: section A.1, pp. 2-3). Examiner respectfully maintains the hydrogen implantation and splitting is an exceedingly old and well known means for thinning a substrate, rather than the “grinding” required by independent process claim 10, and is not speculative, as errantly asserted by Applicant. While there is no requirement for Examiner to provide evidence of the alternative process, as one of many example, US 2010/0164035 (“Kim”) manufactures a semiconductor imaging device by performing in sequence (1) a hydrogen implantation in a semiconductor substrate 100 to form a cleaving region 105 (Fig. 3a; ¶¶ 40-49)—notably pointing out the damage-preventing benefit of cleaving versus the instantly claimed grinding (¶ 49)—(2) forms isolated semiconductor pixels 120 in the semiconductor substrate portion 100b (Figs. 3b-3c; ¶ 51), (3) forms interconnect metallization levels M1, M2, M3 over the pixels (Fig. 4; ¶¶ 52-56), and (4) splits or cleaves the bulk substrate portion 100a from the substrate 100 (Figs. 5-6: ¶ 59). Kim performs subsequent processing on the thinned backside of the remaining substrate 100b (Figs. 7-9). As such, Applicant is unambiguously wrong to suggest the process is speculative or somehow not patentably distinct within the meaning of MPEP § 806.05(f).
Applicant further argues,
However, the Examiner identifies no evidence that the claimed structure (e.g., the specific first/second barrier metal structure, thickness constraints, Ti-silicide regions, metal plug formation) could be fabricated using such an alternative method. The restriction analysis must be claim-based, not speculative. A hypothetical fabrication method that is neither taught nor suggested in the present Specification cannot establish "distinct" inventions.
(Remarks: p. 3; emphasis omitted)
Based on Applicant’s errant reasoning, examiners would be required to examine the process before a requirement for restriction could be made. There simply is no requirement for an examiner to provide evidence that the claimed structure could be made by the alternative process as this would require to perform a search and examination in order to make a requirement for restriction. That alone would be burdensome.
Examiner respectfully disagrees that “[a] hypothetical fabrication method that is neither taught nor suggested in the present Specification cannot establish "distinct" inventions.” (Remarks: p. 3) Although evidence has been provided (Kim, supra), there is also no requirement in the MPEP, statue, rule that the alternative process examiner proposes as an alternative to the claimed process be discussed in the Instant Specification in order for distinctness to exist.
Applicant’s arguments in section A.2 at page 3 of the Remarks are not relevant since Examiner did not rely on the alternative means for showing distinctness addressed here.
Applicant’s argument in section A.3 at page 4 of the Remarks that Examiner invites Applicant to provide evidence anywhere in the MPEP, statue, or rule that “A process step that is not claim-critical cannot form the basis for a restriction between product and process”. Because there is no such requirement for demonstrating distinctness between a product and process, the argument is not found persuasive.
Applicant further alleges that there is “not serious search or examination burden” (Remarks: section B, p. 4). Examiner respectfully disagrees because Applicant failed to address any of the reasons establishing burden as explained in the Requirement for Restriction/Election.
Based on all of the foregoing reasons, the requirement is still deemed proper and is therefore made FINAL.
III. Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 145, in e.g. paragraphs [0047], [0048], and [0053]-[0056].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
IV. Specification
The disclosure is objected to because of the following informalities:
Paragraph [0004] states “When tungsten (Ti) and/or tungsten nitride (TiN) are used …” However the chemical symbol for tungsten and tungsten nitride are W and WN, respectively and the names of Ti and TiN are titanium and titanium nitride, respectively.
Appropriate correction is required.
V. Claim Objections
Claims 3 and 8 are objected to because of the following informalities:
In the last line of each of claims 3 and 8, replace “is” with “are” for correct subject-verb agreement.
Appropriate correction is required.
VI. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1, 4, 6, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,146,998 (“Yamaha”).
With regard to claim 1, Yamaha discloses, generally in Fig. 3B,
1. A semiconductor device comprising:
[1] a semiconductor substrate 1 [col. 3, line 66];
[2] an oxide film 3I [labeled in Fig. 1A; oxide because transistor is a metal-oxide-semiconductor field effect transistor (MOSFET)” (col. 3, lines 62-63)] formed on the semiconductor substrate 1;
[3] a gate poly 3G [labeled in Fig. 1A; col. 4, line 2; col. 6, line 62] formed on a portion of the oxide film 3I;
[4] a spacer 3W [labeled in Fig. 1A; col. 4, line 3] formed to surround the gate poly 3G;
[5] a dielectric film 4 [col. 4, lines 7-8] formed on the spacer 3W;
[6] a first barrier metal 6a [e.g. 20 nm Ti (col. 4, lines 18-19)] formed on side surfaces of the oxide film 3I, the gate poly 3G, the spacer 3W, and the dielectric film 4 which are stacked, a surface of the semiconductor substrate 1, and a top surface of the dielectric film 4;
[7] a second barrier metal [any one or more of 6b, 6c, and 6d (col. 4, lines 32-50)] formed on the first barrier metal 6a;
[8] a metal plug 7D [col. 5, line 25-32] formed in a cavity formed by the second barrier metal [any one or more of 6b, 6c, and 6d];
[9] a metal layer 8/9D [col. 5, lines 33-47] formed on the second barrier metal and the metal plug; and
[10] a passivation layer 10 [col. 5, lines 58-60] formed on the metal layer 8/9D,
[11] wherein a thickness of the first barrier metal 6a formed on the top surface of the dielectric film 4 is in a range of from 15 nm to 25 nm [e.g. 20 nm Ti (col. 4, lines 18-19)].
4. The semiconductor device of claim 1, wherein
[1] the first barrier metal 6a is formed of titanium [col. 4, lines 18-19],
[2] the second barrier metal 6b, 6d is formed of titanium nitride [col. 4, lines 31-33, 46-49], and
[3] the metal layer 8/9D includes aluminum or copper [col. 5, lines 38-43].
With regard to claim 6, Yamaha discloses,
6. A semiconductor device comprising:
[1] a semiconductor substrate 1;
[2] an oxide film 3I formed on a surface of the semiconductor substrate 1;
[3] a gate poly 3G formed on a portion of the oxide film 3I;
[4] a spacer 3W formed to surround the gate poly 3G;
[5] a dielectric film 4 formed on the spacer 3W;
[6] a barrier metal 6a formed on side surfaces of the oxide film 3I, the gate poly 3G, the spacer 3W, and the dielectric film 4 which are stacked, a surface of the semiconductor substrate 1, and a top surface of the dielectric film 4;
[7] a metal layer 8/9B formed on the barrier metal 6a; and
[8] a passivation layer 10 formed on the metal layer 8/9D,
[9] wherein a thickness of the barrier metal 6a formed on the top surface of the dielectric film 4 is in a range of from 15 nm to 25 nm.
9. The semiconductor device of claim 6, wherein
[1] the barrier metal 6a is formed of titanium, and
[2] the metal layer 8/9D includes aluminum or copper.
VII. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaha in view of US 4,183,040 (“Rideout”).
Claims 2 and 7 read,
2. The semiconductor device of claim 1, further comprising: a back metal formed on a bottom of the semiconductor substrate.
7. The semiconductor device of claim 6, further comprising: a back metal formed on another surface of the semiconductor substrate.
The prior art of Yamaha, as explained above, discloses each of the features of claims 1 and 6.
Yamaha does not disclose a back metal.
Rideout, like Nakamura, teaches a semiconductor device including a MOSFET 7/13/24/25 (Rideout: col. 10, lines 32-37). Rideout further teach that “as known in the art, electrical connection to the semiconductive substrate may be provided by a metallic layer deposited by evaporation onto the lower or backside surface of semiconductive substrate 2.” (Rideout: col. 15, lines 17-21; emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a metallic layer on the back surface of the substrate 1 in Yamaha, in order to form an electrical connection to the substrate 1, as taught to be known in the art in Rideout (id.).
This is all of the limitations of claims 2 and 7.
B. Claims 1, 6, and 9 are rejected under 35 U.S.C. 103 as being anticipated by US 5,801,096 (“Lee”) in view of Yamaha.
With regard to claim 1, Lee discloses, generally in Fig. 9,
1. A semiconductor device comprising:
[1] a semiconductor substrate 1 [col. 3, lines 26-28];
[2] an oxide film 3 [col. 3, lines 41-44] formed on the semiconductor substrate 1;
[3] a gate poly 4 [col. 3, line 59] formed on a portion of the oxide film 3;
[4] a spacer 6 [col. 4, lines 3-4] formed to surround the gate poly 4;
[5] a dielectric film 8 [col. 4, lines 9-10] formed on the spacer 6;
[6] a first barrier metal 14 [150 Å to 250 Å Ti, i.e. 15 nm to 25 nm Ti (col. 4, lines 59-61)] formed on side surfaces of the oxide film, the gate poly, the spacer, and the dielectric film which are stacked, a surface of the semiconductor substrate 1, and a top surface of the dielectric film;
[7] a second barrier metal 15 [col. 5, lines 2-7] formed on the first barrier metal 14;
[8] a metal plug [portion of 16 within contact opening in dielectric layer 8 (col. 5, lines 11-14)] formed in a cavity formed by the second barrier metal 15;
[9] a metal layer [portion of 16 within contact on top surface of dielectric layer 8] formed on the second barrier metal 15 and the metal plug; and
[10] … [not taught] …
[11] wherein a thickness of the first barrier metal formed on the top surface of the dielectric film is in a range of from 15 nm to 25 nm [150 Å to 250 Å Ti, i.e. 15 nm to 25 nm Ti (col. 4, lines 59-61)].
With regard to feature [10] of claim 1,
[10] a passivation layer formed on the metal layer,
Lee does not teach that there is a passivation layer formed over the metal layer 16
As explained above, Yamaha, like Lee, teaches a MOSFET having a contact to the source/drain regions including a Ti/TiN barrier layer and a tungsten plug. As also explained above, Yamaha teaches a passivation layer 10 formed on the metal layer 8/9D.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a passivation layer over the metal layer 16 of Lee in order to protect the metal layer and the rest of the MOSFET, as taught in Yamaha. As such, Yamaha may be seen as an improvement to Lee in this aspect. (see MPEP 2143.)
With regard to claim 6, Lee modified to include the passivation layer of Yamaha, as explained under claim 1, teaches,
6. A semiconductor device comprising:
[1] a semiconductor substrate 1 [of Lee];
[2] an oxide film 3 [of Lee] formed on a surface of the semiconductor substrate;
[3] a gate poly 4 [of Lee] formed on a portion of the oxide film;
[4] a spacer 6 [of Lee] formed to surround the gate poly;
[5] a dielectric film 8 [of Lee] formed on the spacer;
[6] a barrier metal 14 [of Lee] formed on side surfaces of the oxide film 3, the gate poly 4, the spacer 6, and the dielectric film 8 which are stacked, a surface of the semiconductor substrate 1, and a top surface of the dielectric film 8;
[7] a metal layer 16/18 [of Lee] formed on the barrier metal 14; and
[8] a passivation layer [10 of Yamaha used in Lee] formed on the metal layer 16/18,
[9] wherein a thickness of the barrier metal 14 [of Lee] formed on the top surface of the dielectric film is in a range of from 15 nm to 25 nm [Lee: 150 Å to 250 Å Ti, i.e. 15 nm to 25 nm Ti (col. 4, lines 59-61)].
With regard to claim 9, Lee further discloses,
9. The semiconductor device of claim 6, wherein
[1] the barrier metal 14 is formed of titanium [150 Å to 250 Å Ti, i.e. 15 nm to 25 nm Ti (col. 4, lines 59-61)], and
[2] the metal layer 16/18 includes aluminum or copper [i.e. 18 is aluminum/copper alloy (Lee: col. 5, lines 35-39)].
C. Claims 1, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2001/0023958 (“Todorobaru”) in view of US 6,355,492 (“Tanaka”).
With regard to claim 1, Todorobaru discloses, generally in Fig. 1,
1. A semiconductor device comprising:
[1] a semiconductor substrate 1 [¶ 86];
[2] an oxide film 7 [¶ 88] formed on the semiconductor substrate 1;
[3] a gate poly 8B, 8C [¶ 89] formed on a portion of the oxide film 7;
[4] a spacer 12/13 [¶ 90] formed to surround the gate poly 8B, 8C;
[5] a dielectric film 14/22/23 [¶¶ 91, 94] formed on the spacer 12;
[6] a first barrier metal 32 [“about 35 nm” of Ti (¶ 122)] formed on side surfaces of the oxide film 7, the gate poly 8B, 8C, the spacer 12, and the dielectric film 14/22/23 which are stacked, a surface of the semiconductor substrate 1, and a top surface of the dielectric film 14/22/23;
[7] a second barrier metal 33 [“about 70 nm TiN” (¶ 122)] formed on the first barrier metal 32;
[8] a metal plug [portion of 34 in contact openings 28, 29 (¶¶ 122, 129)] formed in a cavity formed by the second barrier metal 33;
[9] a metal layer [portion of 34 in on top surface of dielectric 23 (¶ 129)] formed on the second barrier metal 33 and the metal plug; and
[10] a passivation layer 36 [¶¶ 100, 131] formed on the metal layer 34,
[11] wherein a thickness of the first barrier metal 32 formed on the top surface of the dielectric film 14/22/23 is in a range of …[“about 35 nm” of Ti (¶ 122)].
With regard to feature [11] of claim 1,
[11] wherein a thickness of the first barrier metal formed on the top surface of the dielectric film is in a range of from 15 nm to 25 nm.
Todorobaru does not teach the claimed range of 15 nm to 25 nm of the Ti barrier layer 32, instead giving an example of “about 35 nm” (¶ 122).
Tanaka, like Todorobaru, teaches Ti/TiN/W contacts 16 to the source/drain regions 15 of MOSFETs (Tanaka: Figs. 7B, 8A, 8B, 9; col. 11, line 35 to col. 12, line 67—especially Table 8). Tanaka further teaches an actual example in which the Ti layer thickness is 20 nm and the TiN layer 100 nm (Tanaka: Table 8), which as close to the 35 nm Ti and 70 nm TiN disclosed in Todorobaru (supra).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a thickness of 20 nm as the thickness of the Ti layer 32 of Todorobaru formed on the top surface of the dielectric 14/22/23 and in the contact openings 28, 29 because Tanaka teaches that a Ti layer thickness of 20 nm is a known thickness of Ti suitable for the same purpose of forming a Ti/TiN/W contact to the source/drain regions of a MOSFETs. As such, it amount to the substitution of one known thickness (“about 35 nm”) for another known thickness (20 nm) suitable for the same purpose.
Although Tanaka does not indicate that titanium silicide would be formed, as is done Todorobaru, the silicide would necessarily inherently form because Tanaka performs at least subsequent heat step at temperatures and time sufficiently high to form titanium silicide, i.e. at 700 ℃ to 800 ℃ for 10 minutes to 1 hours (Tanaka: col. 13, lines 40-47), while Todorobaru used an anneal at 650 ℃ for 10 minutes to form titanium silicide layer 35A at the Ti layer 32/substrate 1 interface (Todorobaru: ¶ 124; Fig. 1).
With regard to claim 5, Todorobaru further discloses,
5. The semiconductor device of claim 1, wherein a thickness of the second barrier metal formed on the first barrier metal is in a range of from 70 nm to 90 nm [Todorobaru: “about 70 nm TiN” (¶ 122)].
With regard to claim 6, Todorobaru modified to use the 20 nm thickness for the Ti barrier layer 32 as explained under claim 1 above, teaches,
6. A semiconductor device comprising:
1. A semiconductor device comprising:
[1] a semiconductor substrate 1 [¶ 86];
[2] an oxide film 7 [¶ 88] formed on the semiconductor substrate 1;
[3] a gate poly 8B, 8C [¶ 89] formed on a portion of the oxide film 7;
[4] a spacer 12/13 [¶ 90] formed to surround the gate poly 8B, 8C;
[5] a dielectric film 14/22/23 [¶¶ 91, 94] formed on the spacer 12;
[6] a barrier metal 32 [“about 35 nm” of Ti (¶ 122)] formed on side surfaces of the oxide film 7, the gate poly 8B, 8C, the spacer 12, and the dielectric film 14/22/23 which are stacked, a surface of the semiconductor substrate 1, and a top surface of the dielectric film 14/22/23;
[7] a metal layer 34 [¶ 129] formed on the barrier metal 32 and the metal plug; and
[8] a passivation layer 36 [¶¶ 100, 131] formed on the metal layer 34,
[9] wherein a thickness of the barrier metal 32 formed on the top surface of the dielectric film 14/22/23 is in a range of 15 nm to 25 nm [i.e. 20 nm of Ti as taught by Tanaka (supra)].
D. Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Todorobaru in view of Tanaka, as applied to claims 1 and 6, above, and further in view of US 2002/0047153 (“Nakamura”).
Claims 3 and 8 read,
3. The semiconductor device of claim 1, wherein portions of the first barrier metal in contact with the semiconductor substrate, the spacer, the oxide film, and portions of the side surfaces of the dielectric film is silicided.
8. The semiconductor device of claim 6, wherein portions of the barrier metal in contact with the semiconductor substrate, the spacer, the oxide film, and portions of the side surfaces of the dielectric film is silicided.
The prior art of Todorobaru in view of Tanaka, as explained above, teaches each of the features of claims 1 and 6.
With regard to claims 3 and 8, Todorobaru further discloses in Fig. 1 that the titanium silicide layer 35A contacts each of (1) the substrate 1, which was the source of the Si (Todorobaru: ¶ 124, supra), (2) the gate oxide 7, and (3) the spacer 12/13 at least adjacent to gate electrode 8B. This is consistent with Fig. 29 of Todorobaru, which shows that the heat treatment forming the titanium silicide extends upward to almost the height of the initially-deposited Ti layer (Todorobaru: ¶ 146).
As such, Todorobaru only fails to teach that the titanium silicide layer 35A contacts the dielectric film 14/22/23.
Nakamura, like Todorobaru, teaches a DRAM having MOSFETs with having Ti/TiN/W contacts 18a/18b/18c to the source/drain regions 15 of the MOSFETs (Nakamura: Fig. 16; ¶¶ 181, 183), wherein the Ti layer 18a is annealed to form a titanium silicide layer 20 (Nakamura: ¶¶ 188-189). Nakamura also teaches an embodiment in Fig. 44 (¶¶ 306-312) in which the titanium silicide 52a can be formed in contact with each of the substrate, gate oxide 10, and spacer 16/13, as in Todorobaru, and, in addition, on the lower sidewall portion of the dielectric layer 17a over the spacer 16/13.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the titanium silicide layer 35A in Todorobaru, slightly higher to touch the lower sidewall portion of the dielectric 14/22/23 because Nakamura teaches that the titanium silicide can be formed to contact the sidewall of the dielectric layer as well. As such, it is merely a matter of design choice. (See MPEP 2143.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814