DETAILED ACTION
This office action is in response to amendment filed 4/9/2026.
Claims 1-4, 6-10, 12-13, 15, 17, 19, 22-24, 26 and 61 are pending. Claims 5, 11, 14, 16, 18, 20, 21, 25, 27-60 have been canceled. Claims 1, 9, 15, and 26 have been amended.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-9, 13, 15, 17, 22-24, 26, and 61 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakagawa et al. US 2020/0243641 A1 (Nakagawa).
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In re claim 1, Nakagawa discloses (e.g. FIGs. 18 & 70) a semiconductor device, comprising:
a wide bandgap semiconductor structure 102,402 (¶ 419,971), the wide bandgap semiconductor structure comprising a drift region 115,425 of a first conductivity (n) type and a well region 116,426 of a second conductivity (p) type;
a gate trench 121,431 in the wide bandgap semiconductor structure, the gate trench 121,431 extending through the well region 116,426 into the drift region 115,425;
a spacer layer 172,434d (bulging portion) in the gate trench and between a dielectric layer 153,491 and a sidewall of the gate trench (there exist a straight line that intersect the spacer layer 172,434d, the dielectric layer 153,491 and the sidewall of the gate trench, such that the spacer layer 172,434d is between the dielectric layer 153,491 and the sidewall of the gate trench along the straight line); and
a buried gate structure 132+134,435+632 in the gate trench, the buried gate structure comprising a gate polysilicon layer 132,435 and a gate silicide layer 134,632 (¶ 509,1629);
wherein the spacer layer 172,434d comprises a dielectric material (of gate insulating material, ¶ 611,1046) and defines an opening (region surrounded by spacer layer 172,434d, see FIG. 65O), and the dielectric layer 153,491 is disposed within (at least partially within) the opening defined by the spacer layer 172,434d (see FIG. 74D-74E, showing dielectric layer 491 including a lower portion disposed within the opening defined by spacer layer 434d).
In re claim 2, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein an upper surface 134b,632b of the gate silicide layer 134,632 is below an upper surface 103,403 of the wide bandgap semiconductor structure 102,402 (¶ 495,1615).
In re claim 3, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein the buried gate structure 132+134,435+632 is covered within the gate trench 121,431 (¶ 495,1615).
In re claim 4, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein the gate silicide layer 134,632 comprises TaySix or WySix, wherein x is in a range of about 2.0 to about 3.0 (WSi2, ¶ 510,1631).
In re claim 6, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein the gate polysilicon layer 132,435 has a different width (width at lower portion of gate electrode layer 132,435) relative to a width of the gate silicide layer 134,632 (narrower due to presence of bulging portion 172,434d).
In re claim 7, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein the gate polysilicon layer 132,435 is between the gate silicide layer 134,632 and a bottom surface of the gate trench 121,431.
In re claim 8, Nakagawa disclose (e.g. FIGs. 18 & 70) wherein the gate silicide layer 134,632 is closer to an upper surface 103,403, of the wide bandgap semiconductor structure 102,402 relative to the gate polysilicon layer 132,435 .
In re claim 9, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein the dielectric layer 153,491 is in the gate trench 121,431 on the buried gate structure 132+134,435+632 (dielectric layer 153,491 having a lower portion on surface 134b,632b of 134,632 that is below the top surface 103,403 and thus in the gate trench, ¶ 495,1615).
In re claim 13, Nakagawa discloses (e.g. FIG. 70) wherein the dielectric layer 491 is a silicate glass (¶ 1195).
In re claim 15, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein the spacer layer 172,434d (of gate insulating material, ¶ 611,1046) comprises silicon dioxide or silicon nitride (¶ 466,1039).
In re claim 17, Nakagawa discloses (e.g. FIGs. 18 & 70) further comprising a gate dielectric layer 131b,434b between the buried gate structure 132+434,435+632 and the drift region 115,425.
In re claim 22, Nakagawa discloses (e.g. FIG. 14) wherein the wide bandgap semiconductor structure further comprises a shield region 148a beneath the gate trench 121, the shield region 148a having the second conductivity (p) type.
In re claim 23, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein the wide bandgap semiconductor structure 102,402 comprises silicon carbide (¶ 419,971).
In re claim 24, Nakagawa discloses (e.g. FIGs. 18 & 70) wherein the semiconductor device is a MOSFET (¶ 424,0975).
In re claim 26, Nakagawa discloses (e.g. FIGs. 18 & 70) a semiconductor device, comprising:
a wide bandgap semiconductor structure 102,402 (¶ 419,971), the wide bandgap semiconductor structure comprising a drift region 115,425 of a first conductivity (n) type and a well region 116,426 of a second conductivity (p) type;
a gate trench 121,431 in the wide bandgap semiconductor structure, the gate trench 121,431 extending through the well region 116,426 into the drift region 115,425;
a gate structure 132+134,435+632 in the gate trench;
a dielectric layer 153,491 in the gate trench and on the gate structure 132+134,435+632;
a spacer layer 172,434d (bulging portion) in the gate trench and between the dielectric layer 153,491 and a sidewall of the gate trench 121,431 (there exist a straight line that intersect the spacer layer 172,434d, the dielectric layer 153,491 and the sidewall of the gate trench, such that the spacer layer 172,434d is between the dielectric layer 153,491 and the sidewall of the gate trench along the straight line); and
a gate dielectric layer 131b,434b in the gate trench between the gate structure 132+134,435+632 and the drift region 115,425;
wherein the spacer layer 172,434d comprises a dielectric material (of gate insulating material, ¶ 611,1046) and defines an opening (region surrounded by spacer layer 172,434d, see FIG. 65O), and the dielectric layer 153,491 is disposed within (at least partially within) the opening defined by the spacer layer 172,434d (see FIG. 74D-74E, showing dielectric layer 491 including a lower portion disposed within the opening defined by spacer layer 434d).
In re claim 61, Nakagawa discloses (e.g. FIGs. 70) wherein the dielectric layer 491 (PSG, ¶ 1195,1746) is a different material relative to the spacer layer 172,434d (silicon oxide or silicon nitride, ¶ 466,1039).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6-9, 15, 17, 19, 23-24 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu US 2007/0075362 A1 in view of Purtell et al. US 2010/0244126 A1 (Purtell).
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In re claim 1, Wu discloses (e.g. FIGs. 5-6) a semiconductor device, comprising:
a semiconductor structure 200+201, the semiconductor structure comprising a drift region 201 of a first conductivity (n) type and a well region 204b of a second conductivity (p) type;
a gate trench in the semiconductor structure 200+201, the gate trench extending through the well region 204b into the drift region 201;
a spacer layer 213a in the gate trench and between a dielectric layer 208b and a sidewall of the gate trench (there exist a straight line that intersect the spacer layer 213a, the dielectric layer 208b and the sidewall of the gate trench, such that the spacer layer 213a is between the dielectric layer 208b and the sidewall of the gate trench along the straight line; alternatively, claim does not require the entirety of the gate trench to be below the top surface of the semiconductor body and the gate trench may include a region between spacers 209a, see trench shown in FIG. 4A, as such, the spacer layer 213a is laterally between the dielectric layer 208b and the sidewall of the gate trench defined by 209a); and
a buried gate structure 207b+214a, 207c+215a in the gate trench, the buried gate structure comprising a gate polysilicon layer 207b,207c (¶ 36) and a gate silicide layer 214a,215a (¶ 36,39);
wherein the spacer layer 213a comprises a dielectric material (¶ 36) and defines an opening (region surrounded by spacer layer 213a), and the dielectric layer 208b is disposed within the opening defined by the spacer layer 213a.
Wu discloses the semiconductor structure 200,201 is formed of silicon (¶ 21). Wu does not explicitly a wide bandgap semiconductor structure.
However, Purtell discloses (e.g. FIG. 1J) a semiconductor device comprising a semiconductor device comprising a semiconductor structure 100 including a gate trench 103 having a buried gate structure comprising a gate polysilicon layer 110 (¶ 23) and a gate silicide layer 122. Purtell further teaches instead of conventional silicon, the semiconductor structure 100 can be implemented in wide bandgap semiconductor, such as silicon carbide, gallium nitride or diamond (¶ 38).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Wu’s device structure in wide bandgap semiconductor as taught by Purtell for the enhancing the performance of a power transistor with improvement in higher voltages, temperatures, and switching speeds as is well-known in the art.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 3, Wu discloses (e.g. FIGs. 5-6) wherein the buried gate structure 207b,207c,214a,215a is covered within the gate trench.
In re claim 4, Wu discloses (e.g. FIGs. 5-6) wherein the gate silicide layer 214a,215a comprises TaySix or WySix (tungsten silicide, ¶ 36,39). Although Wu does not specify the stoichiometry make-up of the tungsten silicide 214a,215a, the broadly claimed WySix, wherein x is in a range of about 2.0 to about 3.0 can be any stoichiometry. More specifically, only x is specified to be in a rage of about 2.0 to about 3.0, while y is unspecified in the claim. Since the value of y can be any arbitrary value, the relative amount of W to Si in the WySix is also arbitrary. For example, when x is 2, WySi2 can be have any relative stoichiometric ratio since y can be any value; e.g. W-1Si2=W1/2Si, W-2Si2=WSi, W-3Si2=W3/2Si, W-4Si2=W2Si, etc. Similarly, when x is 3, WySi3 can be have any relative stoichiometric ratio since y can be any value; e.g. W1Si3=W1/3Si, W2Si3=W2/3Si, W3Si3=WSi, W-4Si3=W4/3Si, etc.
In re claim 6, Wu discloses (e.g. FIGs. 5-6) wherein the gate polysilicon layer 207b,207c has a different width relative to a width of the gate silicide layer 214a,215a.
In re claim 7, Wu discloses (e.g. FIGs. 5-6) wherein the gate polysilicon layer 207b,207c is between the gate silicide layer 214a,215a and a bottom surface of the gate trench.
In re claim 8, Wu discloses (e.g. FIGs. 5-6) wherein the gate silicide layer 214a,215a (being present at the top surface of the semiconductor body) is closer (in vertical disposition) to an upper surface of the semiconductor structure relative to the gate polysilicon layer 207b,207c (being recessed below).
In re claim 9, Wu discloses (e.g. FIGs. 5-6) the dielectric layer 208b is in the gate trench on the buried gate structure (the gate trench including a region between spacers 209a, see trench shown in FIG. 4A; claim does not require the entirety of the gate trench to be below the top surface of the semiconductor body).
In re claim 15, Wu discloses (e.g. FIGs. 5-6) wherein the spacer layer 213a comprises silicon dioxide or silicon nitride (¶ 36).
In re claim 17, Wu discloses (e.g. FIGs. 5-6) further comprising a gate dielectric layer 206a between the buried gate structure 207b,207c and the drift region 201.
In re claim 19, Wu discloses (e.g. FIGs. 5-6) wherein the semiconductor structure 200,201 comprises a second silicide layer 210a on an upper surface of the wide bandgap semiconductor structure 201, wherein the second silicide layer 210a is a different material (e.g. titanium silicide, cobalt silicide, or nickel silicide, ¶ 26) relative to the gate silicide layer 214a,215a (tungsten silicide, ¶ 36,39), wherein the second silicide layer 210a comprises nickel silicide, tungsten silicide, titanium silicide, aluminum silicide, molybdenum silicide, aluminum- titanium silicide, nickel-titanium-aluminum silicide or titanium-tungsten silicide (e.g. titanium silicide or nickel silicide, ¶ 26).
In re claim 23, Purtell discloses wherein the wide bandgap semiconductor structure comprises silicon carbide (¶ 38).
In re claim 24, Wu discloses (e.g. FIGs. 5-6) wherein the semiconductor device is a MOSFET (¶ 35, 38).
In re claim 26, Wu discloses (e.g. FIGs. 5-6) a semiconductor device, comprising:
a semiconductor structure 200+201, the semiconductor structure comprising a drift region 201 of a first conductivity (n) type and a well region 204b of a second conductivity (p) type;
a gate trench in the semiconductor structure 200+201, the gate trench extending through the well region 204b into the drift region 201;
a gate structure 207b,207c,214a,215a in the gate trench;
a dielectric layer 208b in the gate trench and on the gate structure (the gate trench including a region between spacers 209a);
a spacer layer 213a in the gate trench and between the dielectric layer 208b and a sidewall of the gate trench (there exist a straight line that intersect the spacer layer 213a, the dielectric layer 208b and the sidewall of the gate trench, such that the spacer layer 213a is between the dielectric layer 208b and the sidewall of the gate trench along the straight line; alternatively, claim does not require the entirety of the gate trench to be below the top surface of the semiconductor body and the gate trench may include a region between spacers 209a, see trench shown in FIG. 4A, as such, the spacer layer 213a is laterally between the dielectric layer 208b and the sidewall of the gate trench defined by 209a); and
a gate dielectric layer 206a in the gate trench between the gate structure 207b,207c and the drift region 201;
wherein the spacer layer 213a comprises a dielectric material (¶ 36) and defines an opening (region surrounded by spacer layer 213a), and the dielectric layer 208b is disposed within the opening defined by the spacer layer 213a.
Wu discloses the semiconductor structure 200,201 is formed of silicon (¶ 21). Wu does not explicitly a wide bandgap semiconductor structure.
However, Purtell discloses (e.g. FIG. 1J) a semiconductor device comprising a semiconductor device comprising a semiconductor structure 100 including a gate trench 103 having a buried gate structure comprising a gate polysilicon layer 110 (¶ 23) and a gate silicide layer 122. Purtell further teaches instead of conventional silicon, the semiconductor structure 100 can be implemented in wide bandgap semiconductor, such as silicon carbide, gallium nitride or diamond (¶ 38).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Wu’s device structure in wide bandgap semiconductor as taught by Purtell for the enhancing the performance of a power transistor with improvement in higher voltages, temperatures, and switching speeds as is well-known in the art.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claims 1-4, 6-10, 12-13, 15, 17, 23-24, 26 and 61 is/are rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. US 2004/0183129 A1 (Williams; cited in IDS filed 3/3/2025) in view of Purtell et al. US 2010/0244126 A1 (Purtell).
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In re claim 1, Williams discloses (e.g. FIG. 23G) a semiconductor device, comprising:
a semiconductor structure, the semiconductor structure comprising a drift region 1722 of a first conductivity (n) type and a well region 1723 of a second conductivity (p) type;
a gate trench in the semiconductor structure, the gate trench extending through the well region into the drift region; and
a spacer layer (upper portion of 1725 adjacent 1729) in the gate trench and between a dielectric layer 1729 and a sidewall of the gate trench; and
a buried gate structure 1726-1728 in the gate trench, the buried gate structure comprising a gate polysilicon layer 1726,1727 and a gate silicide layer 1728 (¶ 139);
wherein the spacer layer (upper portion of 1725) comprises a dielectric material (¶ 139) and defines an opening (region surrounded by upper portion of 1725 corresponding to space occupied by 1729, opening exist before filling with 1729), and the dielectric layer 1729 is disposed within the opening defined by the spacer layer.
Williams discloses the semiconductor structure is formed of silicon (¶ 66). Williams does not explicitly a wide bandgap semiconductor structure.
However, Purtell discloses (e.g. FIG. 1J) a semiconductor device comprising a semiconductor device comprising a semiconductor structure 100 including a gate trench 103 having a buried gate structure comprising a gate polysilicon layer 110 (¶ 23) and a gate silicide layer 122. Purtell further teaches instead of conventional silicon, the semiconductor structure 100 can be implemented in wide bandgap semiconductor, such as silicon carbide, gallium nitride or diamond (¶ 38).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Williams’ device structure in wide bandgap semiconductor as taught by Purtell for the enhancing the performance of a power transistor with improvement in higher voltages, temperatures, and switching speeds as is well-known in the art.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 2, Williams discloses (e.g. FIGs. 23G) wherein an upper surface of the gate silicide layer 1728 is below an upper surface of the semiconductor structure.
In re claim 3, Williams discloses (e.g. FIG. 23G) wherein the buried gate structure 1726-1728 is covered within the gate trench.
In re claim 4, Williams discloses (e.g. FIGs. 23G) wherein the gate silicide layer 1728 comprises TaySix or WySix (tungsten-silicide, ¶ 120). Although Williams does not specify the stoichiometry make-up of the tungsten silicide, the broadly claimed WySix, wherein x is in a range of about 2.0 to about 3.0 can be any stoichiometry. More specifically, only x is specified to be in a rage of about 2.0 to about 3.0, while y is unspecified in the claim. Since the value of y can be any arbitrary value, the relative amount of W to Si in the WySix is also arbitrary. For example, when x is 2, WySi2 can be have any relative stoichiometric ratio since y can be any value; e.g. W-1Si2=W1/2Si, W-2Si2=WSi, W-3Si2=W3/2Si, W-4Si2=W2Si, etc. Similarly, when x is 3, WySi3 can be have any relative stoichiometric ratio since y can be any value; e.g. W1Si3=W1/3Si, W2Si3=W2/3Si, W3Si3=WSi, W-4Si3=W4/3Si, etc.
In re claim 6, Williams discloses (e.g. FIG. 23G) wherein the gate polysilicon layer 1726 has a different width (narrow bottom portion) relative to a width of the gate silicide layer 1728.
In re claim 7, Williams discloses (e.g. FIG. 23G) wherein the gate polysilicon layer 1726,1727 is between the gate silicide layer 1728 and a bottom surface of the gate trench.
In re claim 8, Williams discloses (e.g. FIG. 23G) wherein the gate silicide layer 1728 is closer to an upper surface of the semiconductor structure relative to the gate polysilicon layer 1726,1727.
In re claim 9, Williams discloses (e.g. FIG. 23G) the dielectric layer 1729 is in the gate trench on the buried gate structure.
In re claim 10, Williams discloses (e.g. FIGs. 4J & 9B) further comprising a metallization layer 230+231,422A on the semiconductor structure, the metallization layer 230+231,422A having a planar surface contacting the semiconductor structure and the dielectric layer (225A in FIG. 4J; 421A in FIG. 9B; 1729 in FIG. 23G), wherein the dielectric layer 225A,421A,1729 is arranged to electrically insulate the buried gate structure 215,405,1726-1728 from the metallization layer 230+231,422A.
In re claim 12, Williams discloses (e.g. FIG. 23G) wherein the dielectric layer 1729 has an upper surface that is coplanar with an upper surface of the semiconductor structure.
In re claim 13, Williams discloses (e.g. FIG. 23G) wherein the dielectric layer is a silicate glass (¶ 90).
In re claim 15, Williams discloses (e.g. FIG. 23G) wherein the spacer layer (upper portion of 1725 adjacent 1729 and 1728) comprises silicon dioxide or silicon nitride (formed by oxidation on silicon surface, ¶ 83-84).
In re claim 17, Williams discloses (e.g. FIG. 23G) further comprising a gate dielectric layer 1725 (lower portion) between the buried gate structure 1726 and the drift region 1722.
In re claim 23, Purtell discloses wherein the wide bandgap semiconductor structure comprises silicon carbide (¶ 38).
In re claim 24, Williams discloses (e.g. FIG. 23G) wherein the semiconductor device is a MOSFET (¶ 61).
In re claim 26, Williams discloses (e.g. FIG. 23G) a semiconductor device, comprising:
a semiconductor structure, the semiconductor structure comprising a drift region 1722 of a first conductivity (n) type and a well region 1723 of a second conductivity (p) type;
a gate trench in the semiconductor structure, the gate trench extending through the well region into the drift region;
a gate structure 1726-1728 in the gate trench;
a dielectric layer 1729 in the gate trench and on the gate structure;
a spacer layer (upper portion of 1725 adjacent 1729) in the gate trench and between the dielectric layer 1729 and a sidewall of the gate trench; and
a gate dielectric layer (lower portion of 1725) in the gate trench between the gate structure 1726 and the drift region 1722;
wherein the spacer layer (upper portion of 1725) comprises a dielectric material (¶ 139) and defines an opening (region surrounded by upper portion of 1725 corresponding to space occupied by 1729, opening exist before filling with 1729), and the dielectric layer 1729 is disposed within the opening defined by the spacer layer.
Williams discloses the semiconductor structure is formed of silicon (¶ 66). Williams does not explicitly a wide bandgap semiconductor structure.
However, Purtell discloses (e.g. FIG. 1J) a semiconductor device comprising a semiconductor device comprising a semiconductor structure 100 including a gate trench 103 having a buried gate structure comprising a gate polysilicon layer 110 (¶ 23) and a gate silicide layer 122. Purtell further teaches instead of conventional silicon, the semiconductor structure 100 can be implemented in wide bandgap semiconductor, such as silicon carbide, gallium nitride or diamond (¶ 38).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Williams’ device structure in wide bandgap semiconductor as taught by Purtell for the enhancing the performance of a power transistor with improvement in higher voltages, temperatures, and switching speeds as is well-known in the art.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 61, Williams discloses (e.g. FIG. 23G) wherein the dielectric layer 1729 (e.g. glass, ¶ 90) is a different material relative to the spacer layer (upper portion of 1725 adjacent 1729 formed by oxidation on silicon surface, ¶ 83-84).
Response to Arguments
Applicant's arguments filed 4/9/2026 have been fully considered but they are not persuasive.
Nakagawa
Applicant argues Nakagawa’s spacer layer “bulging portion” 172,434d is not “disposed within the opening defined by the spacer layer” (Remark, page 7).
This is not persuasive. Claim does not recite the spacer layer to be “disposed within the opening defined by the spacer layer”. Rather, claim recites the spacer layer is “in the gate trench” and the dielectric layer is “disposed within the opening defined by the spacer layer”.
The spacer layer corresponds to bulging portion 172,434d shown in Nakagawa’s FIG. 18 & 70. The bulging portion or spacer layer 172,434d are disposed in the gate trench. I.e. at least a part of the bulging portion/spacer layer 172,434d is in the gate trench. Alternatively, the spacer layer may correspond to only the portion of the bulging portion 172,434d that is in the gate trench. Furthermore, the opening corresponding to space that is surrounded and defined by the spacer layer 172,434d. And the dielectric layer 153,491 is disposed within the opening as shown in, e.g. FIG. 74D-74E wherein the lower portion of dielectric layer 491 is disposed within the opening defined by spacer layer 434d.
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Wu and Purtell
Applicant argues Wu’s does not teach “a spacer layer buried within the gate trench” (Remark, pages 7-8).
This is not persuasive. Claim does not recite the spacer layer is “buried within the gate trench”. Rather, claim recites the spacer layer is “in the gate trench”.
The spacer layer corresponds to Wu’s spacer 213a which is at least partially within the gate trench defined in the semiconductor body. Alternatively, the spacer may correspond only to the portion of 213a that is buried within the gate trench in the semiconductor body. Furthermore, claim does not require the entirety of the gate trench to be below the top surface of the semiconductor body. The gate trench may include a region between spacers 209a. E.g. see trench shown in FIG. 4A. As such, the spacer layer 213a entirely buried (not claimed) within the gate trench.
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Applicant argues Williams’ upper portion of 1725 is the sidewall of the gate trench and is not between the dielectric layer and a sidewall of the gate trench (Remark, page 8).
This is not persuasive. Williams teaches element 1725 is a gate oxide (¶ 139). The sidewall of the gate trench is covered by gate oxide 1725. Therefore, the upper portion of oxide layer 1725 correspond to the claimed spacer layer that is between the dielectric 1729 and the sidewall of the gate trench.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights