Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of in the reply filed on 12/18/2025 is acknowledged.
Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election of group I claims 1-14 was made without traverse in the reply filed on 12/18/2025.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 10-14 is/are rejected under 35 U.S.C. 102102 (a) (1) as being anticipated by Chen et al. (US 20220093849 A1).
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CLAIM 1 . Chen et al. discloses a resistive memory structure, comprising:
a substrate 310 (Chen ¶36, Fig. 3);
a dielectric 220l layer located on the substrate 310 (Chen ¶26, Fig. 2-3);
a conductive plug 106 located in the dielectric layer 204l and having a protrusion portion 106ub located outside the dielectric layer 204l (Chen ¶20, Fig. 2-3);
a resistive memory device RRAM 102 [108+110+112] located on the conductive plug 106 (Chen ¶16-17, Fig. 2-3) and comprising:
a first electrode 108 located on the conductive plug 106;
a variable resistance layer 110 located on the first electrode 108; and
a second electrode 112 located on the variable resistance layer 112;
a spacer 208+210 located on a sidewall of the resistive memory device 102 (Chen ¶29-30, Fig. 2-3; and
a protective layer 204u located on a sidewall of the protrusion portion 106ub and between the first electrode 108 and the dielectric layer 204l (Chen fig. 2-3).
CLAIM 2. Chen et al. discloses a resistive memory structure according to claim 1, wherein a top surface 106t of the conductive plug 106 is higher than a top surface of the dielectric layer204l (Chen, Fig. 2-3).
CLAIM 3. Chen et al. discloses a resistive memory structure according to claim 1, wherein a top surface 106t of the conductive plug is coplanar with a top surface of the protective layer204u (Chen, Fig. 2-3).
CLAIM 4. Chen et al. discloses a resistive memory structure according to claim 1, wherein the protective layer 204u is in direct contact with the first electrode 108, the dielectric layer, and the protrusion portion 106ub (Chen, Fig. 2-3).
CLAIM 5. Chen et al. discloses a resistive memory structure according to claim 1, wherein the spacer 208+210 is in direct contact with the first electrode108, the variable resistance layer 110, and the second electrode 112 (Chen, Fig. 2-3).
CLAIM 6. Chen et al. discloses a resistive memory structure according to claim 5, wherein the spacer 208+210 is further in direct contact with the protective layer 204u (Chen, Fig. 2-3).
CLAIM 7. Chen et al. discloses a resistive memory structure according to claim 1, wherein the spacer 208+210 completely covers a sidewall of the first electrode 108 (Chen, Fig. 2-3).
CLAIM 8. Chen et al. discloses a resistive memory structure according to claim 1, wherein the spacer 208+210 completely covers a sidewall of the variable resistance layer 110 (Chen, Fig. 2-3).
CLAIM 10. Chen et al. discloses a resistive memory structure according to claim 1, wherein a material of the first electrode 108 comprises titanium 108 (Chen, ¶16).
CLAIM 11. Chen et al. discloses a resistive memory structure according to claim 1, wherein a material of the variable resistance layer 110 comprises tantalum oxide or hafnium oxide (Chen, ¶17).
CLAIM 12. Chen et al. discloses a resistive memory structure according to claim 1, wherein a material of the second electrode 112 comprises titanium (Chen, ¶17).
CLAIM 13. Chen et al. discloses a resistive memory structure according to claim 1, wherein a material of the spacer 208+2110 comprises silicon nitride (Chen, ¶29-30 – Note: Both may be formed of the same material.).
CLAIM 14. Chen et al. discloses a resistive memory structure according to claim 1, wherein a material of the protective layer 204u comprises silicon nitride (Chen, ¶26).
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102102 (a) (1) as being anticipated by Ando et al. (US 20210193920 A1).
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CLAIM 1 . Ando et al. discloses a resistive memory structure, comprising:
a substrate 208 (Ando ¶23, Fig. 2);
a dielectric 306 layer located on the substrate 208 (Ando ¶28, Fig. 2-3);
a conductive plug 314 located in the dielectric layer 306 and having a protrusion portion located outside the dielectric layer 306 (Ando, Fig. 3);
a resistive memory device RRAM [316+322+(318++320)] located on the conductive plug 314 (Ando ¶27, Fig. 3) and comprising:
a first electrode 316 located on the conductive plug 314;
a variable resistance layer 322 located on the first electrode 108; and
a second electrode 318++320 located on the variable resistance layer 322;
a spacer 324 located on a sidewall of the resistive memory device RRAM [316+322+(318+320)] (Ando Fig. 3; and
a protective layer 312 located on a sidewall of the protrusion portion 314 and between the first electrode 316 and the dielectric layer 306 (Ando fig. 3).
CLAIM 2. Ando et al. discloses a resistive memory structure according to claim 1, wherein a top surface of the conductive plug 314 is higher than a top surface of the dielectric layer 306 (Ando, Fig. 3).
CLAIM 3. Ando et al. discloses a resistive memory structure according to claim 1, wherein a top surface of the conductive plug 314 is coplanar with a top surface of the protective layer 312 (Ando, Fig. 3).
CLAIM 4. Ando et al. discloses a resistive memory structure according to claim 1, wherein the protective layer 314 is in direct contact with the first electrode 316, the dielectric layer, and the protrusion portion (Ando, Fig. 3).
CLAIM 5. Ando et al. discloses a resistive memory structure according to claim 1, wherein the spacer 324 is in direct contact with the first electrode 316, the variable resistance layer 322, and the second electrode 318+320 (Ando, Fig. 3).
CLAIM 6. Ando et al. discloses a resistive memory structure according to claim 5, wherein the spacer 324 is further in direct contact with the protective layer 312 (Ando, Fig. 3).
CLAIM 7. Ando et al. discloses a resistive memory structure according to claim 1, wherein the spacer 324 completely covers a sidewall of the first electrode 316 (Ando, Fig. 3).
CLAIM 8. Ando et al. discloses a resistive memory structure according to claim 1, wherein the spacer 324 completely covers a sidewall of the variable resistance layer 322 (Ando, Fig. 3).
CLAIM 9. Ando et al. discloses a resistive memory structure according to claim 1, wherein a top of the spacer 324 is lower than a top surface of the second electrode 318 & 318+320 (Ando, Fig. 3).
CLAIM 10. Ando et al. discloses a resistive memory structure according to claim 1, wherein a material of the first electrode 316 comprises titanium 108 (Ando ¶31, Fig. 3).
CLAIM 11. Ando et al. discloses a resistive memory structure according to claim 1, wherein a material of the variable resistance layer 322 comprises tantalum oxide or hafnium oxide (Ando, ¶32).
CLAIM 12. Ando et al. discloses a resistive memory structure according to claim 1, wherein a material of the second electrode 112 comprises titanium (Ando, ¶31).
CLAIM 13. Ando et al. discloses a resistive memory structure according to claim 1, wherein a material of the spacer 324 comprises silicon nitride (Ando, ¶33).
CLAIM 14. Ando et al. discloses a resistive memory structure according to claim 1, wherein a material of the protective layer 312 comprises silicon nitride (Chen, ¶30).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20220093849 A1) in view of Ando et al. (US 20210193920 A1).
CLAIM 9. Both Chen et al. and Ando et al. disclose resistive memory structures according to claim 1.
While Chen may not explicitly state that the “top of the spacer is lower than a top surface of the second electrode,” this specific structural relationship is expressly demonstrated in Ando et al. figure 3.
Chen and Ando demonstrate that the profile of RRAM layers and sidewall spacers is a variable of the fabrication process, subject to specific manufacturing preferences or design goals. Because RRAM devices utilizing similar materials for identical purposes were known in the art, a POSITA would have found it obvious to form a sidewall spacer with a top surface lower than the upper electrode.
Such a structural modification represents a predictable change in shape and spatial relationship that yields no unexpected results or benefits. Therefore, modifying the structure of Chen in view of Ando would have been obvious by a POSITA at the time of the invention. See MPEP §21440.4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
1/15/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898