DETAILED ACTION
This Office action is in response to the election filed 26 December 2025. Claims 1-15 and 21-25 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species II, claims 1-4, 6-9, 11-15, and 21-25 in the reply filed on 26 December 2025 is acknowledged. The traversal is on the ground(s) that it should be no serious burden to consider all claims in the single application and that two is a reasonable number of species. This is not found persuasive because the examination and search of all species requires employing different search strategies and search queries, thus presenting undue search and examination burden. Applicant is respectfully reminded that upon allowance of a generic claim, Applicant will be entitled to consideration of claims to additional species which depend from or otherwise require all limitations of an allowable generic claim as provided by 37 CFR 1.141.
The requirement is still deemed proper and is therefore made FINAL.
Claims 5 and 10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 26 December 2025.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-24 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: providing a nanostructure stack over the substrate which is essential to the invention because the method would not form a functional semiconductor device structure without the above step. Claims 22-24 depend from claim 21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0376072 A1 to Yu et al. (hereinafter “Yu”).
Regarding independent claim 11, Yu (Figs. 1-34) disclose a method for forming a semiconductor device structure, comprising:
providing a substrate 202/204 (Fig. 2A; ¶ 0018) and a nanostructure stack 205/206 (Fig. 2A; ¶ 0021), wherein the substrate has a base 202 and a fin 204a/b (Fig. 2A; ¶ 0022) over the base, the nanostructure stack is over the fin 204a/b;
forming a gate stack 210 (Fig. 3; ¶ 0024) wrapped around the nanostructure stack 205/206 (Fig. 2A);
forming a first source/drain structure 214 (Fig. 3; ¶ 0018) in the nanostructure stack and adjacent to the gate stack 210;
removing the second gate stack 210b, the nanostructure stack 205/206 and the fin 204 under the gate stack to form a trench 232 (¶ 0037) passing through the nanostructure stack and the fin (Figs. 10-12; ¶¶ 0036-38);
forming a dielectric isolation structure 284 (¶ 0050; Fig. 27) in the trench; and
forming a contact structure 294 over the source/drain structure 214, wherein the contact structure has a wide strip portion (Fig. 34 - wide strip of 294 closer to 284) and a narrow strip portion (Fig. 34 - narrow strip of 294 farther away from 284), and the wide strip portion is closer to the dielectric isolation structure 284 than the narrow strip portion in a top view of the contact structure and the dielectric isolation structure (Fig. 34).
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0377943 A1 to Wu et al. (hereinafter “Wu”).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding independent claim 1, Wu (Figs. 1-21) discloses a method for forming a semiconductor device structure, comprising:
providing a substrate 202 (Fig. 3; ¶ 0016)and a nanostructure stack 204 (Fig. 3; ¶¶ 0016, 0011), wherein the substrate has a base and a fin 205 (Fig. 2; ¶ 0016) over the base, the nanostructure stack is over the fin 205 and has a first nanostructure 206 (¶ 0016) and a second nanostructure 208 (¶ 0016) over the first nanostructure (Fig. 3);
forming a first gate stack 212a (Fig. 3; ¶ 0018) and a second gate stack 212b (Fig. 3; ¶ 0018) wrapped around the nanostructure stack 204 (see ¶ 0011 - gate wraps a top and sidewalls of fin);
forming a first source/drain structure 218 (Fig. 3; ¶ 0020) in the nanostructure stack 204 and between the first gate stack 212a and the second gate stack 212b;
removing the second gate stack 212b, the nanostructure stack 204 and the fin under the second gate stack to form a trench 232 passing through the nanostructure stack and the fin (Figs. 5-7; ¶¶ 0024-25);
forming a dielectric isolation structure 235 (¶ 0026; Fig. 9) in the trench;
removing the first gate stack 212a and the first nanostructure 206 (Figs. 11-12; ¶¶ 0028-29);
forming a third gate stack 242 (Figs. 13-14; ¶ 0030) wrapped around the second nanostructure 208 (Figs. 13-14; ¶ 0030); and
forming a first contact structure 264 (Fig. 19; ¶ 0038) over the first source/drain structure 218, wherein the dielectric isolation structure 235 is closer to the first contact structure 264 than the third gate stack 242 (Fig. 19).
Claims 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0060454 A1 to Jhan et al. (hereinafter “Jhan”).
Regarding independent claim 21, Jhan (Figs. 1-13) discloses a method for forming a semiconductor device structure, comprising:
forming a first gate stack 40 (¶ 0066; Fig. 9) and a second gate stack (¶ 0066 - not in figures) over a substrate 110 (¶ 0043; Fig. 9);
forming a source/drain structure 82 (¶ 0015; Fig. 1C) between the first gate stack and the second gate stack (Fig. 1B);
replacing the first gate stack 40 (Fig. 9; ¶ 0066) with a metal gate stack 200B (Fig. 13; ¶ 0075);
forming a dielectric isolation structure 420 (¶ 0012; Fig. 1B) extending through the second gate stack (Fig. 1B - 200P; ¶ 0012); and
forming a contact structure 120 (¶ 0028; Fig. 1C - 120 above 420) over the source/drain structure 82, wherein the dielectric isolation structure 420 is closer to the contact structure 120 than the metal gate stack 200B (Figs. 1B-1C).
Regarding claim 22, Jhan (Fig. 1C) discloses the method for forming the semiconductor device structure as claimed in claim 21, wherein the contact structure 120 (Fig. 1C - 120 above 420) has a wide strip portion (Fig. 1C - wide strip of 120 closer to 420) and a narrow strip portion (Fig. 1C - narrow strip of 120 farther away from 420), and the wide strip portion is closer to the dielectric isolation structure 420 than the narrow strip portion in a top view of the contact structure 120 and the dielectric isolation structure 420 (Fig. 1C).
Regarding claim 23, Jhan (Fig. 1C) discloses the method for forming the semiconductor device structure as claimed in claim 21, wherein the contact structure 120 is formed to extend into the dielectric isolation structure 420 (Fig. 1C - from a top view, wide strip of 120 extends into 420).
Regarding claim 24, Jhan (Fig. 1C) discloses the method for forming the semiconductor device structure as claimed in claim 21, wherein the contact structure 120 (Fig. 1C - 120 above 420) is formed to extend across a first edge (Fig. 1C - left edge of 82) of the source/drain structure 82.
Regarding claim 25, Jhan (Fig. 1C) discloses the method for forming the semiconductor device structure as claimed in claim 24, wherein the contact structure 120 (Fig. 1C - 120 above 420) is formed to extend across a second edge (Fig. 1C - right edge of 420) of the dielectric isolation structure 420.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 9, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu.
Regarding independent claim 1, Yu (Figs. 1-34) discloses a method for forming a semiconductor device structure, comprising:
providing a substrate 202/204 (Fig. 2A; ¶ 0018) and a nanostructure stack 205/206 (Fig. 2A; ¶ 0021), wherein the substrate has a base 202 and a fin 204a/b (Fig. 2A; ¶ 0022) over the base, the nanostructure stack is over the fin 204a/b and has a first nanostructure 205 (¶ 0021) and a second nanostructure 206 (¶ 0021) over the first nanostructure (Fig. 3);
forming a first gate stack 210a (Fig. 3; ¶ 0024) and a second gate stack 210b (Fig. 3; ¶ 0021) wrapped around the nanostructure stack 205/206 (Fig. 2A);
forming a first source/drain structure 214 (Fig. 3; ¶ 0018) in the nanostructure stack and between the first gate stack 210a and the second gate stack 210b;
removing the second gate stack 210b, the nanostructure stack 205/206 and the fin 204 under the second gate stack to form a trench 232 (¶ 0037) passing through the nanostructure stack and the fin (Figs. 10-12; ¶¶ 0036-38);
forming a dielectric isolation structure 284 (¶ 0050; Fig. 27) in the trench;
removing the first gate stack 210a and the first nanostructure 205 (Figs. 15, 17; ¶¶ 0041,43);
forming a third gate stack 260 (Figs. 18-19; ¶ 0045) wrapped around the second nanostructure 206 (Fig. 18; ¶ 0045); and
forming a first contact structure 294 (Fig. 34; ¶ 0063) over the first source/drain structure 214.
Yu does not expressly disclose the dielectric isolation structure is closer to the first contact structure than the third gate stack. Nonetheless, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Here, the distance between the dielectric isolation structure and the first contact structure as compared to the third gate stack, is considered a mere dimensional limitation. The instant disclosure is silent as to a particular unobvious purpose, unexpected result, or criticality of the above dimensional limitation, and thus it is found to be prima facie obvious.
Regarding claim 8, Yu discloses the method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a gate spacer 212/217 (¶ 0027; Fig. 3) over a sidewall of the second gate stack 210b, wherein the trench 232 further passes through the gate spacer 212/217 (Fig. 12A), the dielectric isolation structure 284 (Fig. 27) is adjacent to the gate spacer, and the first contact structure 294 extends into the gate spacer (Fig. 34).
Yu fails to expressly disclose forming the gate spacer before the first source/drain structure, however, selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to alter the order of performing the process steps of Yu, to form the gate spacer prior to the formation of the first source/drain structure, in the absence of new or unexpected results.
Regarding claim 9, Yu discloses the method for forming the semiconductor device structure as claimed in claim 8, wherein the first contact structure 294 passes through the gate spacer 212.
Regarding claim 13, Yu discloses the method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a gate spacer 212/217 (¶ 0027; Fig. 3) over a sidewall of the gate stack 210, wherein the trench 232 further passes through the gate spacer 212 (Fig. 12A), the dielectric isolation structure 284 (Fig. 27) is adjacent to the gate spacer, and the wide strip portion of the contact structure 294 extends into the gate spacer 212/217 (Fig. 34).
Yu fails to expressly disclose forming the gate spacer before the source/drain structure, however, selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to alter the order of performing the process steps of Yu, to form the gate spacer prior to the formation of the source/drain structure, in the absence of new or unexpected results.
Regarding claim 14, Yu discloses the method for forming the semiconductor device structure as claimed in claim 13, wherein the wide strip portion of the contact structure 294 penetrates through the gate spacer 212/217 (Fig. 34).
Claims 2-4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Wu.
Regarding claim 2, Wu (Figs. 1-21) discloses the method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second source/drain structure (Fig. 3 - the figures are understood to be a representative subsection of the substrate with repeating structures, 218 formed to the left of 212a; ¶ 0020) in the nanostructure stack 204, wherein the first gate stack 212a is between the first source/drain structure 218 and the second source/drain structure 218 (to the left of 212a in Fig. 3); and forming a second contact structure 264 (Fig. 19; ¶ 0038) over the second source/drain structure.
Wu fails to expressly disclose: wherein a first average width of the first contact structure is greater than a second average width of the second contact structure. Nonetheless, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Here, relationship between the average widths, i.e., the first average width greater than the second average width, is considered a mere dimensional limitation. The instant disclosure is silent as to a particular unobvious purpose, unexpected result, or criticality of the above dimensional limitation, and thus it is found to be prima facie obvious.
Regarding claim 3, Wu (Figs. 1-21) discloses the method for forming the semiconductor device structure as claimed in claim 2, further comprising: forming a first metal silicide layer 262 (Fig. 19; ¶ 0038) over the first source/drain structure 218 and a second metal silicide layer 262 over the second source/drain structure 218 (to the left of region 205C in Fig. 19), wherein the first contact structure 264 is formed over the first metal silicide layer 262, the second contact structure 264 is formed over the second metal silicide layer 262 (Fig. 19)
Wu fails to expressly disclose: the first metal silicide layer is wider than the second metal silicide layer. Nonetheless, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Here, relationship between the widths of the first and second metal silicide layers, i.e., the first metal silicide layer is wider than the second metal silicide layer, is considered a mere dimensional limitation. The instant disclosure is silent as to a particular unobvious purpose, unexpected result, or criticality of the above dimensional limitation, and thus it is found to be prima facie obvious.
Regarding claim 4, Wu (Figs. 1-21) discloses the method for forming the semiconductor device structure as claimed in claim 3, wherein a first distance between the first contact structure 264 and the third gate stack (242 in region 205C in Fig. 19) is substantially equal to a second distance between the second contact structure (264 over 218 to the left of region 205C in Fig. 19) and the third gate stack (Fig. 19).
Regarding claim 6, Wu (Figs. 1-21) discloses the method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a first conductive via structure over the first contact structure 264 and a second conductive via structure over the second contact structure 264 (over 218 to the left of 205C in Fig. 21) (¶ 0041 - disclosing multi-layer interconnect structure (not depicted) over the structure of Fig. 21 configured to interconnect source/drain contacts 264 and gate contacts), wherein the dielectric isolation structure 235 is closer to the first conductive via structure (Fig. 21 - above 264 in region 205SD) than the third gate stack (Fig. 21 - 242 in region 205C).
Regarding claim 7, Wu (Figs. 1-21) discloses the method for forming the semiconductor device structure as claimed in claim 1, however fails to expressly disclose wherein the first contact structure has an L-like shape in a top view of the first contact structure.
Where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular arrangement, the particular arrangement is deemed to have been a design consideration within the skill of the art. In re Kuhle, 526 F.2d 553, 555, 188 USPQ 7, 9 (CCPA 1975). Here, the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to the claimed L-like shape in a top view of the first contact structure, thus for this reason and in view of the disclosure of Wu, the recited particular shape is deemed to have been a design consideration within the skill of the art.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jhan.
Regarding claim 11, Jhan (Figs. 1-13) discloses a method for forming a semiconductor device structure, comprising:
providing a substrate 110 (Fig. 3; ¶ 0043) and a nanostructure stack 22/24 (Fig. 3; ¶ 0043), wherein the substrate has a base and a fin 321-324 (¶ 0043) over the base, and the nanostructure stack is over the fin (Fig. 3);
forming a gate stack 40 (¶ 0066) wrapped around the nanostructure stack 22/24 (Fig. 9);
forming a source/drain structure 82 (see Fig. 1C; ¶ 0015) in the nanostructure stack 22/24 and adjacent to the gate stack (¶ 0071; Fig. 11);
removing the nanostructure stack 22A3/22B3/22C3/24 and the fin 323 under the gate stack to form a trench passing through the nanostructure stack and the fin (¶ 0053; Figs. 4C-4D);
forming a dielectric isolation structure 420 (¶ 0056) in the trench (¶ 0055); and
forming a contact structure 120 (¶ 0028; Fig. 1C - 120 above 420) over the source/drain structure 82, wherein the contact structure 120 has a wide strip portion (Fig. 1C - wide strip of 120 closer to 420) and a narrow strip portion (Fig. 1C - narrow strip of 120 farther away from 420), and the wide strip portion is closer to the dielectric isolation structure 420 than the narrow strip portion in a top view of the contact structure 120 and the dielectric isolation structure 420 (Fig. 1C).
Jhan does not expressly disclose removing the gate stack to form the trench, however, selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to alter the order of performing the process steps of Jhan, to form gate stack 40 (¶ 0076 - a dummy gate stack that will be removed in subsequent steps) prior to the formation of the dielectric isolation structure in the trench in the absence of new or unexpected results.
Regarding claim 12, Jhan (Fig. 1C) discloses the method for forming the semiconductor device structure as claimed in claim 11, wherein the wide strip portion (Fig. 1C - wide strip of 120 closer to 420) of the contact structure extends into the dielectric isolation structure 420 (Fig. 1C - from a top view, wide strip of 120 extends into 420).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jhan as applied to claim 11 above, and further in view of US 2023/0395596 A1 to Fan et al. (hereinafter “Fan”).
Regarding claim 15, Jhan discloses the method for forming the semiconductor device structure as claimed in claim 11, however fails to expressly disclose wherein the contact structure has a stepped edge in the top view of the contact structure and the dielectric isolation structure. In the same field of endeavor, Fan discloses a contact structure 144/132 with a stepped edge in top view (cover figure; ¶ 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a contact structure with an additional via (e.g. 144) in the method of Jhan, thus having a stepped edge in top view, for the purpose of decreasing the space necessary between individual electrical connections (Fan, ¶ 0041).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2022/0344465 A1 to Chen et al. disclosing a method of manufacturing a transistor including a dielectric barrier; US 2023/0402528 A1 to Chen et al. disclosing a method of forming semiconductor structures with reduced parasitic capacitance; US 2020/0381426 A1 to Xu et al. disclosing a method of manufacturing gate-all-around field effect transistors.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
10 January 2026
/KHAJA AHMAD/ Primary Examiner, Art Unit 2813