DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-20 in the reply filed on 01/29/26 is acknowledged. The traversal is on the ground(s) that the office fails to properly establish that examination of all pending claims would not present a serious burden.
Applicant’s election is acknowledged. Applicant’s traversal of the restriction is noted. Examiner notes that species A and B can be simultaneously examined. Examiner will examine claims 9-20 and the newly amended claims 1-8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su(USPGPUB DOCUMENT: 2017/0133351, hereinafter Su) in view of Chen (USPGPUB DOCUMENT: 2020/0411445, hereinafter Chen).
Re claim 1 Su discloses in Fig 15 a three-dimensional integrated circuit stack, comprising: a first integrated circuit structure, comprising: a first semiconductor device(34/434); a first buffer structure(66/50); a first interconnect structure(202/90), wherein the first semiconductor device(34/434) is located between the first buffer structure(66/50) and the first interconnect structure(202/90); a first conductive via(56/52/32/44), extending through the first buffer structure(66/50) and in contact with the first semiconductor device(34/434); and a first through via(56/52/32/44), extending from the first buffer structure(66/50) to the first interconnect structure(202/90); and a redistribution structure(70/68), disposed under the first buffer structure(66/50), electrically connected to the first semiconductor device(34/434) through the first conductive via(56/52/32/44), and electrically connected to the first interconnect structure(202/90) through the first through via(56/52/32/44).
Su does not disclose and a second integrated circuit structure, bonding to the first integrated circuit structure;
Chen disclose in Fig 4 a second integrated circuit structure(204/200), bonding to the first integrated circuit structure(104/100);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chen to the teachings of Su in order to improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area [0002, Chen].
Re claim 2 Su and Chen disclose the three-dimensional integrated circuit stack of claim 1, wherein the second integrated circuit structure comprises:a second semiconductor device(34/434);a second buffer structure;a second interconnect structure, wherein the second semiconductor device(34/434) is located between the second buffer structure and the second interconnect structure;a third interconnect structure(304/404), disposed on the second buffer structure and bonding with the first interconnect structure(202/90);a second conductive via(56/52/32/44), extending from the third interconnect structure(304/404) to the second semiconductor device(34/434) through the second buffer structure; and a second through via(56/52/32/44), extending from the third interconnect structure(304/404) to the second interconnect structure through the second buffer structure.
Re claim 3 Su and Chen disclose the three-dimensional integrated circuit stack of claim 2, further comprising a third integrated circuit structure, wherein the third integrated circuit structure comprises:a substrate;a third semiconductor device(34/434);a fourth interconnect structure(304/404), wherein the third semiconductor device(34/434) is disposed between the substrate and the fourth interconnect structure(304/404), and the fourth interconnect structure(304/404) is bonding with the second interconnect structure.
Re claim 4 Su and Chen disclose the three-dimensional integrated circuit stack of claim 1, wherein a surface of the first conductive via(56/52/32/44) is coplanar with a surface of the first through via(56/52/32/44).
Re claim 5 Su and Chen disclose the three-dimensional integrated circuit stack of claim 1, wherein the second integrated circuit structure comprises:a second semiconductor device(34/434);a second buffer structure;a second interconnect structure, bonding with the first interconnect structure(202/90), wherein the second semiconductor device(34/434) is located between the second buffer structure and the second interconnect structure;a third interconnect structure(304/404), disposed on the second buffer structure;a second conductive via(56/52/32/44), extending from the third interconnect structure(304/404) to the second semiconductor device(34/434) through the second buffer structure; anda second through via(56/52/32/44), extending from the third interconnect structure(304/404) to the second interconnect structure through the second buffer structure.
Re claim 6 Su and Chen disclose the three-dimensional integrated circuit stack of claim 1, wherein the second integrated circuit structure comprises:a second semiconductor device(34/434);a second buffer structure;a second interconnect structure, wherein the second semiconductor device(34/434) is located between the second buffer structure and the second interconnect structure;a third interconnect structure(304/404), disposed on the second buffer structure and wherein a bonding pad of the third interconnect structure(304/404) is bonded with a bonding pad of the first interconnect structure(202/90), the third interconnect structure(304/404) including a dielectric layer surrounding the bonding pad of the third interconnect structure(304/404), wherein a portion of the dielectric layer of the third interconnect structure(304/404) and the first through via(56/52/32/44) are passing through the second buffer structure;a second conductive via(56/52/32/44), extending from the third interconnect structure(304/404) to the second semiconductor device(34/434) through the second buffer structure and the dielectric layer of the third interconnect structure(304/404).
Re claim 7 Su and Chen disclose the three-dimensional integrated circuit stack of claim 1, wherein the first conductive via(56/52/32/44) is connected with a source/drain region of the first semiconductor device(34/434).
Re claim 8 Su and Chen disclose the three-dimensional integrated circuit stack of claim 1, wherein the first buffer structure(66/50) comprises a silicon layer and an insulation layer, wherein the silicon layer is located between the redistribution structure(70/68) and the insulation layer.
Re claim 14 Su discloses in Fig 15 a three-dimensional integrated circuit stack, comprising: a first integrated circuit structure, comprising: a first semiconductor device(34/434);a first buffer structure(66/50), disposed under the first semiconductor device(34/434);a first interconnect structure(202/90), disposed above the first semiconductor device(34/434);a first conductive via(56/52/32/44), extending through the first buffer structure(66/50), and in contact (examiner interprets contact as electrical contact) with the first semiconductor device(34/434) at a bottom surface of the first semiconductor device(34/434); and a first through via(56/52/32/44), extending through the first buffer structure(66/50); and a redistribution structure(70/68), disposed under the first integrated circuit structure.
Su does not disclose a first conductive via(56/52/32/44), extending through the first buffer structure(66/50), and in contact with a source/ drain region of the first semiconductor device(34/434) at a bottom surface of the first semiconductor device(34/434); and a second integrated circuit structure, attached to the first interconnect structure(202/90);
Chen disclose in Fig 4 a source/ drain region[0029 of Chen] of the first semiconductor device(103); and a second integrated circuit structure(204/200), attached to the first interconnect structure(104/100);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chen to the teachings of Su in order to improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area [0002, Chen]. In doing so, a first conductive via(56/52/32/44), extending through the first buffer structure(66/50), and in contact with a source/ drain region[0029 of Chen] of the first semiconductor device(34/434) at a bottom surface of the first semiconductor device(34/434); and a second integrated circuit structure(204/200), attached to the first interconnect structure(104/100);
Re claim 15 Su and Chen disclose the three-dimensional integrated circuit stack of claim 14, wherein the first integrated circuit structure further comprises:a first insulation structure(48) surrounding the first semiconductor device(34/434),wherein the first insulation structure(48) and the first semiconductor device(34/434) are located between the first buffer structure(66/50) and the first interconnect structure(202/90), and the first through via(56/52/32/44) is passing through the first buffer structure(66/50) and the first insulation structure(48).
Re claim 16 Su and Chen disclose the three-dimensional integrated circuit stack of claim 14, wherein the second integrated circuit structure comprises:a second semiconductor device(34/434);a second buffer structure, disposed on a first side of the second semiconductor device(34/434);a second interconnect structure, disposed on a second side of the second semiconductor device(34/434);a third interconnect structure(304/404), disposed on the second buffer structure,wherein a bonding pad of the first interconnect structure(202/90) is attached to a bonding pad of the third interconnect structure(304/404);a second conductive via(56/52/32/44), extending from a first side of the second buffer structure to the first side of the second semiconductor device(34/434); anda second through via(56/52/32/44), extending from the first side of the second buffer structure to the second interconnect structure through the second buffer structure.
Re claim 17 Su and Chen disclose the three-dimensional integrated circuit stack of claim 16, wherein a thickness of the second through via(56/52/32/44) is larger than a thickness of the second conductive via(56/52/32/44).
Re claim 18 Su and Chen disclose the three-dimensional integrated circuit stack of claim 14, wherein the second integrated circuit structure comprises:a second semiconductor device(34/434);a second buffer structure;a second interconnect structure, bonding with the first interconnect structure(202/90), wherein the second semiconductor device(34/434) is located between the second buffer structure and the second interconnect structure;a third interconnect structure(304/404), disposed on the second buffer structure; a second conductive via(56/52/32/44), extending from the third interconnect structure(304/404) to the second semiconductor device(34/434) through the second buffer structure; and a second through via(56/52/32/44), extending from the third interconnect structure(304/404) to the second interconnect structure through the second buffer structure.
Re claim 19 Su and Chen disclose the three-dimensional integrated circuit stack of claim 18, wherein a width of a bottom surface of the second through via(56/52/32/44) facing towards the first integrated circuit structure is smaller than a width of a top surface of the second through via(56/52/32/44) facing away from the first integrated circuit structure, and a width of a top surface of the first through via(56/52/32/44) facing towards the second integrated circuit structure is smaller than a width of a bottom surface of the first through via(56/52/32/44) facing away from the second integrated circuit structure.
Re claim 20 Su and Chen disclose the three-dimensional integrated circuit stack of claim 14, wherein the first through via(56/52/32/44) is extending from the first buffer structure(66/50) into the first interconnect structure(202/90), and is in contact with a first bonding pad of the first interconnect structure(202/90), wherein the first bonding pad is bonded with the second integrated circuit structure.
Claim(s) 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su(USPGPUB DOCUMENT: 2017/0133351, hereinafter Su) in view of an alternative interpretation of Chen (USPGPUB DOCUMENT: 2020/0411445, hereinafter Chen).
Re claim 9 Su discloses in Fig 15 a three-dimensional integrated circuit stack, comprising: a first die, comprising: a first semiconductor device(34/434) and a first insulation structure(48) adjacent to the first semiconductor; a first buffer structure(66/50) and a first interconnect structure(202/90), wherein the first semiconductor device(34/434) and the first insulation structure(48) are located between the first buffer structure(66/50) and the first interconnect structure(202/90); a first conductive via(56/52/32/44), continuously passing through the first buffer structure(66/50) and electrically connected with the first semiconductor device(34/434); and a first through via(56/52/32/44), continuously passing through the first buffer structure(66/50) and the first insulation structure(48), and electrically connected with the first interconnect structure(202/90); and a redistribution structure(70/68), disposed under the first buffer structure(66/50), and electrically connected to the first conductive via(56/52/32/44) and the first through via(56/52/32/44).
Su does not disclose a second die, bonding to the first die;
Chen disclose in Fig 4 a second die(204/200), bonding to the first die(104/100);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chen to the teachings of Su in order to improvement in integration density has come from successive reductions in minimum feature size, which allows more components to be integrated into a given area [0002, Chen].
Re claim 10 Su and Chen disclose the three-dimensional integrated circuit stack of claim 9, wherein the second die comprises:a second semiconductor device(34/434) and a second insulation structure adjacent to the second semiconductor device(34/434);a second buffer structure;a second interconnect structure and a third interconnect structure(304/404), wherein the third interconnect structure(304/404) is located between the second buffer structure and the first interconnect structure(202/90), and the second semiconductor device(34/434) and the second insulation structure are located between the second buffer structure and the second interconnect structure;a second conductive via(56/52/32/44), passing through the second buffer structure and connected with a source/drain region of the second semiconductor device(34/434); anda second through via(56/52/32/44), passing through the second buffer structure and the second insulation structure, and electrically connected with the second interconnect structure and the third interconnect structure(304/404).
Re claim 11 Su and Chen disclose the three-dimensional integrated circuit stack of claim 10, further comprising a third die, wherein the third die comprises:a substrate;a third semiconductor device(34/434); a fourth interconnect structure(304/404), wherein the third semiconductor device(34/434) is disposed between the substrate and the fourth interconnect structure(304/404), and the fourth interconnect structure(304/404) is bonding with the second interconnect structure.
Re claim 12 Su and Chen disclose the three-dimensional integrated circuit stack of claim 10, wherein a surface of the second conductive via(56/52/32/44) is coplanar with a surface of the second through via(56/52/32/44).
Re claim 13 Su and Chen disclose the three-dimensional integrated circuit stack of claim 9, wherein a thickness of the first through via(56/52/32/44) is larger than a thickness of the first conductive via(56/52/32/44).
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812