DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-3, 5 and 7-14 in the reply filed on 3/17/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/8/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Sorgeloos et al. US 2009/0195951 in view of Salcedo et al. US 2020/0286889.
Re claim 1, Sorgeloos teaches a circuit (fig 6 or 7 with leakage device added as in 10A and 10B), comprising:
a substrate (layer holding 600 or 700, fig6 or 7);
a target device on the substrate (IC connected between node1 and node2 protected against ESD, fig6 or 7, [4]); and
an electrostatic discharge (ESD) device (600, fig6, [38]) electrically coupled to the target device, the ESD device comprising:
an ESD detection circuit (402 with R 403 and C 401, fig6, [37]) electrically coupled to a first reference voltage supply (Vdd connected with node1 308, fig6, [28, 39]) and a second reference voltage supply (voltage supply 310, fig6, [39]);
an inverter circuit (602, fig6, [38]) electrically coupled to the ESD detection circuit (402, fig6, [37]) and configured to trigger in response to an ESD event on the first reference voltage supply or the second reference voltage supply;
a rectifier circuit (more than one diode leakage device added, 1002 between gate of ESD device 304 and second voltage supply as in fig10A and 1004 added between 306 and Vdd in fig10B, [45]) electrically coupled to the inverter circuit (602, fig6, [38]) and configured to rectify a current discharged from the inverter circuit ([45]); and
a transistor (304/404 of fig6 and 10A/10B, [31, 45]) electrically coupled to the rectifier circuit (diode 1002 added between gate of 304 and Vdd and 1004 added between gate of 304 and 10B, and second voltage supply as in fig10A) and configured to discharge a remaining current passing through the rectifier circuit ([45]).
Sorgeloos teaches more than one leakage device ([45]); leakage device 1002 as diode added between gate of 304 and second voltage supply (fig10A) and leakage device 1004 as diode added between gate of 304 and first voltage supply (fig10B).
Sorgeloos does not explicitly show the detail of a substrate; a target device on the substrate and the rectifier circuit.
Salcedo teaches a rectifier circuit (204, fig5, [113]) formed between VDD and VSS on a substrate connected with a target device (205, fig5, [113]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sorgeloos and Salcedo to form 204 of Salcedo between 300/306 and gate of 304 of Sorgeloos. The motivation to do so is to provide path for the leakage current (Sorgeloos, [45]) and customizable protection against electrical overstress to the target device (Salcedo, [114]).
Re claim 3, Sorgeloos modified above teaches the circuit of claim 1, wherein the ESD detection circuit comprises a resistor and a capacitor electrically coupled with each other (402 with R 403 and C 401, fig6, [37]).
Re claim 5, Sorgeloos modified above teaches the circuit of claim 1, wherein the inverter circuit comprises an enhancement mode transistor device (602, fig6, [38]) electrically coupled to a resistive element (403, fig6, [37]).
Re claim 7, Sorgeloos modified above teaches the circuit of claim 1, wherein the rectifier circuit comprises a diode configured to rectify a current from the ESD event (1002 as diode added between gate of ESD device 304 and second voltage supply as in fig10A and 1004 added between 306 and Vdd in fig10B, [45]).
Re claim 8, Sorgeloos modified above teaches the circuit of claim 1, wherein the rectifier circuit comprises a plurality of diodes arranged in a reverse bias configuration (1004 as 222/223 of Salcedo for customizable protection added between 306 and Vdd in fig10B in reverse bias configuration with respect to Vdd to provide path for the leakage current form 306 to Vdd, fig10B [45]).
Re claim 9, Sorgeloos modified above teaches the circuit of claim 1, wherein the transistor (304/404 of fig6 and 10A/10B, [31, 45]) is electrically coupled to the target device (Salcedo, 205, fig5, [113]; Sorgeloos, IC connected between node1 and node2 protected against ESD, fig6, [4]).
Claim(s) 2, 10-14 and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Sorgeloos et al. US 2009/0195951 in view of Salcedo et al. US 2020/0286889 and Gittemeier US 2017/0126002.
Re claim 2, Sorgeloos does not explicitly show the circuit of claim 1, wherein the substrate comprises an n-type substrate.
Gittemeier teaches n-type GaN used as the active layer ([38]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sorgeloos in view of Salcedo and Gittemeier to use n-type GaN as the substrate to form the PMOS of Sorgeloos or according to the type of IC circuits connected with the protection circuits. The motivation to do so is to achieve high electrical performance at higher temperature and resistant to avalanche breakdown (Gittemeier, [5]).
Re claim 10, Sorgeloos teaches a circuit (fig 6 with leakage device added as in 10A and 10B), comprising:
a target device (IC connected between node1 and node2 protected against ESD, fig6, [4]); and
an electrostatic discharge (ESD) device (600, fig6, [38]) electrically coupled to the target device, the ESD device comprising:
an ESD detection circuit (402 with R 403 and C 401, fig6, [37]) electrically coupled to a first reference voltage supply (Vdd connected with node1 308, fig6, [28, 39]) and a second reference voltage supply (voltage supply 310, fig6, [39]);
Sorgeloos does not explicitly show a gallium nitride (GaN) substrate; and the ESD device comprising a GaN inverter circuit.
Gittemeier teaches GaN used as the active layer ([38]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sorgeloos in view of Gittemeier to use GaN as the substrate to form the inverter circuit of Sorgeloos. The motivation to do so is to achieve high electrical performance at higher temperature and resistant to avalanche breakdown (Gittemeier, [5]).
Sorgeloos in view of Gittemeier teaches a GaN inverter circuit (Sorgeloos, 602, fig6, [38]) comprising an enhancement mode transistor device (Sorgeloos, one transistor of 602, fig6) and a resistive element (Sorgeloos, Channel region of the other transistor of 602, fig6),
wherein the GaN inverter circuit (Sorgeloos, 602, fig6, [38]) is electrically coupled to the ESD detection circuit (Sorgeloos, 402 with R 403 and C 401, fig6, [37]), and
wherein the GaN inverter circuit (Sorgeloos, 602, fig6, [38]) is configured to trigger in response to an ESD event on the first reference voltage supply or the second reference voltage supply;
a rectifier circuit (more than one diode leakage device added, 1002 between gate of ESD device 304 and second voltage supply as in fig10A and 1004 added between 306 and Vdd in fig10B, [45]) electrically coupled to the GaN inverter circuit and configured to rectify current discharged from the GaN inverter circuit ([45]); and
a field effect transistor (FET) (304/404 of fig6 and 10A/10B, [31, 45]) electrically coupled to the rectifier circuit (diode 1002 between gate of ESD device 304 and second voltage supply as in fig10A and 1004 added between 306 and Vdd in fig10B) and configured to discharge a remaining current passing through the rectifier circuit ([45]).
Sorgeloos does not explicitly show the detail of a target device on the substrate and the rectifier circuit.
Salcedo teaches a rectifier circuit (204, fig5, [113]) formed between VDD and VSS on a substrate connected with a target device (205, fig5, [113]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sorgeloos in view of Gittemeier and Salcedo to form 204 of Salcedo between 300/306 and gate of 304 of Sorgeloos. The motivation to do so is to provide path for the leakage current (Sorgeloos, [45]) and customizable protection against electrical overstress to the target device (Salcedo, [114]).
Re claim 11, Sorgeloos modified above teaches the circuit of claim 10, wherein the ESD detection circuit comprises a resistor electrically coupled to a capacitor (Sorgeloos, 402 with R 403 and C 401, fig6, [37]).
Re claim 12, Sorgeloos modified above teaches the circuit of claim 10, wherein the GaN inverter circuit, wherein the enhancement mode transistor device (Sorgeloos, one transistor of 602, fig6) electrically coupled to the resistive element (Sorgeloos, Channel region of the other transistor of 602, fig6).
Re claim 13, Sorgeloos modified above teaches the circuit of claim 10, wherein the rectifier circuit comprises a plurality of diodes arranged in a reverse bias configuration (1004 as 222/223 of Salcedo for customizable protection added between 306 and Vdd in fig10B in reverse bias configuration with respect to Vdd to provide path for the leakage current form 306 to Vdd, fig10B [45]).
Re claim 14, Sorgeloos modified above teaches the circuit of claim 10, wherein the FET (304/404 of fig6 and 10A/10B, [31, 45]) is electrically coupled to the target device (Salcedo, 205, fig5, [113]; Sorgeloos, IC connected between node1 and node2 protected against ESD, fig6, [4]).
Re claim 21, Sorgeloos modified above teaches the circuit of claim 10, wherein the resistive element (Sorgeloos, Channel region of the other transistor of 602, fig6) is configured to switch from an on state to an off state in response to the ESD event.
Re claim 22, Sorgeloos modified above teaches the circuit of claim 10, wherein the enhancement mode transistor device (Sorgeloos, one transistor of 602, fig6) is configured to be activated in response to the ESD event.
Re claim 23, Sorgeloos teaches a circuit (fig7 with leakage device added as in 10A and 10B), comprising:
an electrostatic discharge (ESD) device (700, fig7, [41]) configured to protect the device (IC connected between node1 and node2 protected against ESD, fig7, [4]) from an ESD event occurring in a voltage supply to the device,
wherein the ESD device comprises:
a detection circuit (402 with R 403 and C 401, fig6, [37]) coupled to the voltage supply (Vdd connected with node1 308 and voltage supply 310, fig7, [28, 39]) and comprising a resistor (R 403, fig7, [37]) and a capacitor (C 401, fig7, [37]);
a first transistor (bottom transistor of 602, fig7, [41]) coupled to the voltage supply and the detection circuit, wherein the first transistor is configured to be activated in response to the ESD event ([41]);
a rectifier circuit (more than one diode leakage device added, 1002 between gate of ESD device 304 and second voltage supply as in fig10A and 1004 added between 306 and Vdd in fig10B, [45]) coupled to the transistor and the voltage supply,
Sorgeloos does not explicitly show the detail of a target device on the substrate and the rectifier circuit.
Salcedo teaches a rectifier circuit (204, fig5, [113]) formed between VDD and VSS on a substrate connected with a target device (205, fig5, [113]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sorgeloos in view of Salcedo to form 204 of Salcedo between 300/306 and gate of 304 of Sorgeloos. The motivation to do so is to provide path for the leakage current (Sorgeloos, [45]) and customizable protection against electrical overstress to the target device (Salcedo, [114]).
Sorgeloos in view of Salcedo teaches wherein the rectifier circuit is configured to discharge a first portion of a current corresponding to the ESD event (discharge through 1002 between gate of ESD device 304 and second voltage supply as in fig10A and 1004 added between 306 and Vdd in fig10B, [45]); and
a second transistor (top transistor of 602, fig7, [41]) coupled to the rectifier circuit and the voltage supply,
wherein the second transistor is configured to discharge a second portion of the current (discharge through 1004 added between 306/406 and Vdd in fig10B, [45]).
Sorgeloos does not explicitly show a device on an n-type substrate.
Gittemeier teaches n-type GaN used as the active layer ([38]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sorgeloos in view of Salcedo and Gittemeier to use n-type GaN as the substrate to form the PMOS of Sorgeloos or according to the type of IC circuits connected with the protection circuits. The motivation to do so is to achieve high electrical performance at higher temperature and resistant to avalanche breakdown (Gittemeier, [5]).
Re claim 24, Sorgeloos modified above teaches the circuit of claim 23, wherein the circuit further comprising a resistive element (Sorgeloos, Channel region of the top transistor of 602, fig7) coupled to the first transistor (Sorgeloos, bottom transistor of 602, fig7), wherein the resistive element is configured to switch from an on state to an off state in response to the ESD event.
Re claim 25, Sorgeloos modified above teaches the circuit of claim 24, wherein the resistive element (Sorgeloos, Channel region of the top transistor of 602, fig7) is coupled to a drain of the first transistor (Sorgeloos, drain of bottom transistor of 602, fig7).
Re claim 26, Sorgeloos modified above teaches the circuit of claim 23, wherein a gate of the second transistor (Sorgeloos, top transistor of 602, fig7, [41]) is coupled to a drain of the first transistor (Sorgeloos, drain of bottom transistor of 602, fig7).
Re claim 27, Sorgeloos modified above teaches the circuit of claim 23, wherein the rectifier circuit comprises a plurality of diodes in series, wherein each of the plurality of diodes is in a reverse bias configuration (1004 as 222/223 of Salcedo for customizable protection added between 306 and Vdd in reverse bias configuration with respect to Vdd to provide path for the leakage current form 306 to Vdd, fig10B, [45]).
Re claim 28, Sorgeloos modified above teaches the circuit of claim 27, wherein the first transistor (Sorgeloos, bottom transistor of 602, fig7) is further configured to be activated at a voltage discharge from the capacitor, wherein the voltage is in a range between about 1 V and about 3 V ("[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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