Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on December 5, 2025, regarding the application filed August 16, 2023. Applicant’s amendment to claim 14 has been entered into the record. Claims 1-20 are currently pending.
Election/Restrictions
Applicant’s election with traverse of Group I, corresponding to claims 1-13 and 18-20 in the reply filed on December 5, 2025 is acknowledged. The traversal is on the ground(s) that amended claim 14 does not specify the timing of forming a buried cavity and is aligned with claim 1 … claims 1 and 14 should be examined together. This argument is persuasive and therefore the restriction requirement has been withdrawn.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on an application filed in Italy on August 26, 2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 16, 2023 has been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on August 16, 2023 are objected to because Figures 1A, 1B, 2, and 3 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Applicant’s specification, page 2, lines 10-15, states “commercially available MOSFET devices are typically formed by a plurality of transistors 1 of the type shown in Figures 1A, 1B”. Additionally, each of Figures 1A, 1B, 2, and 3 are identically reproduced from Applicant’s 2019 patent application 16/389,866, published October 24, 2019, and cited in the rejection of claims below as Patané. Figures 1A, 1B, 2, and 3 should therefore be designated by a legend such as --Prior Art-- because only that which is old is illustrated.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Patané et al. US 2019/0326217 A1 (hereinafter Patané) and further in view of Hsu et al., US 2007/0210890 A1 (hereinafter Hsu).
Regarding claim 1, Patané discloses: An electronic device comprising: a body including Silicon Carbide (Patané, FIG. 5, substrate 48, made of silicon carbide (SiC), [0029]); a gate terminal on the body (Patané, FIG. 5, gate region 24, “forms a control terminal G,” [0019]); a conductive path on the body (Patané, FIGs. 3, 5, connection region 36, [0026]), the conductive path configured to be electrically coupled to a generator of a biasing voltage of the gate terminal (Patané, FIG. 2, 3, 5, connection region 36 [the conductive path] is “configured to be electrically coupled to the generator 23 [the generator of a biasing voltage of the gate terminal],” [0026; 0019]); a protection element of a solid-state material (Patané, FIGs. 2, 5, fuse 21, [0044]), coupled to the gate terminal and to the conductive path (Patané, FIGs. 2, 5, fuse 21 [the protection element] shown coupled to gate region 24 [the gate terminal] and to connection region 36 [the conductive path], [0034]), the protection element being an electrical connection between the gate terminal and the conductive path (Patané, FIGs. 2, 5, “fuse 21 [the protection element] is in electrical and structural continuity with the gate region 24 [the gate terminal]. Moreover, the fuse 21 [the protection element] is in electrical and structural continuity with the connection region 36 [the conductive path],” [0034]), the protection element configured to change from a solid state to a melted or gaseous state (Patané, FIGs. 2, 5, “fuse 21 [the protection element] is designed so as to change its physical state (e.g., from solid to molten or from solid to gaseous),” [0044]), interrupting the electrical connection (Patané, FIGs. 2, 5, “fuse 21 [the protection element] is designed so as to interrupt the electrical connection between the connection region 36 [the conductive path] (connected in use to the generator 23) and the gate region 24 [the gate terminal],” [0045]), in response to a leakage current through the protection element greater than a threshold (Patané, FIGs. 2, 5, “fuse 21 [the protection element] is designed so as to change its physical state (e.g., from solid to molten or from solid to gaseous) in the presence of the short circuit current iSC … to interrupt the electrical connection between the connection region 36 [the conductive path] and the gate region 24 [the gate terminal] … in the presence of a current higher than a critical threshold that is at least one order of magnitude higher than the leakage current in normal operating conditions,” [0044-0045]);
Although Patané discloses “an opening 70 through the insulating layer 56, which reaches the fuse 21,” (Patané, FIG. 5, [0047]), i.e., an opening in the body accommodating the protection element, Patané does not explicitly teach that the opening forms “a buried cavity in the body”.
However, Hsu, in the same field of endeavor, teaches an electronic fuse for an integrated circuit, comprising: a buried cavity in the body (Hsu, FIG. 13, voids 1300, [0053]) accommodating, at least in part, the protection element (Hsu, FIG. 13, “voids 1300 [the buried cavity] underneath the respective fuse elements [the protection element] provide a region into which the open circuited fuse material may melt,” i.e., accommodating the protection element, [0053]). Hsu teaches that by providing a void, i.e., a cavity, below the fuse element, the fuse element is better thermally isolated, resulting in a reduced open circuit current/voltage, additionally, the melted fuse metal can flow into the void (Hsu, [0041-0042]). These advantages result in improved programming efficiency, resulting in improved manufacturing process efficiency as well as improved device performance and reliability.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Patané with the teachings of Hsu, arriving at Applicant’s claimed structural arrangement with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Hsu, to better thermally isolate the fuse element, thereby improving programming efficiency, resulting in improved manufacturing process efficiency as well as improved device performance and reliability.
Regarding claim 2, Patané in view of Hsu teaches: The electronic device according to claim 1, wherein the buried cavity is configured to contain material in melted or gaseous state of the protection element (Hsu, FIG. 13, “voids 1300 [the buried cavity] underneath the respective fuse elements [the protection element] provide a region into which the open circuited fuse material may melt,” i.e., the buried cavity is configured to contain material in melted state of the protection element, [0053]).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Hsu include one or more of Applicant’s claimed alternative elements, for example: to contain material in melted state.
Regarding claim 3, Patané in view of Hsu teaches: The electronic device according to claim 1, wherein the buried cavity (Hsu, FIG. 13, voids 1300) accommodates a support for supporting, at least in part, the protection element (Hsu, “the fuse element [the protection element] resides … over a void [the buried cavity] in a supporting structure,” i.e., the buried cavity accommodates a support for supporting the protection element, [0010]).
Regarding claim 4, Patané in view of Hsu teaches: The electronic device according to claim 1, wherein the protection element is a fuse (Patané, FIGs. 2, 5, fuse 21, “the protection element 21 is a fuse configured to interrupt the electrical connection between the generator 23 and the gate region 24 in the presence of the short circuit current iSC,” [0020]).
Regarding claim 5, Patané in view of Hsu teaches: The electronic device according to claim 1, wherein the protection element (Patané, FIGs. 2, 5, fuse 21) is of a material having an electrical resistivity lower than 10 Ω·cm chosen from among polysilicon, metal, or conductive polymer (Patané, “p is the electrical resistivity of the fuse 21 (which, in the case of polysilicon, is 10−4 Ω·cm),” [0042]; “fuse 21 [the protection element] may be made of … for example, metal or conductive polymer, with an electrical resistivity of less than 10 Ω·cm,” [0060]).
Regarding claim 6, Patané in view of Hsu teaches: The electronic device according to claim 1, wherein the protection element, the gate terminal and the conductive path form a monolithic structure (Patané, FIG. 3, “the connection region 36 [the conductive path], the plurality of fuses 21 [the protection element], and the plurality of gate regions 24 [the gate terminal] form a monolithic structure,” [0027]).
Regarding claim 7, Patané in view of Hsu teaches: The electronic device according to claim 1, further comprising: a covering layer including polymeric material (Patané, FIG. 5, passivation layer 62, polyamide, [0038; 0047-0048]; Hsu, FIG. 17, polyimide 1700, [0058]), the covering layer encloses the buried cavity (Hsu, FIG. 17, polyimide 1700 [the covering layer] shown enclosing voids 1300 [the buried cavity], [0058]).
Regarding claim 8, Patané in view of Hsu teaches nearly every element of claim 8 but is silent regarding: wherein the covering layer partially extends into the buried cavity and physically contacts the protection element.
However, given the teachings of Patané and Hsu it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed covering layer partially extends into the buried cavity and physically contacts the protection element because each of Patané and Hsu teach a covering layer including a polymeric material (Patané, FIG. 5, passivation layer 62, polyamide, [0038; 0047-0048]; Hsu, FIG. 17, polyimide 1700, [0058]), and Patané teaches that “passivation layer 62 [analogous to the covering layer of Hsu] extends within the opening 70 [analogous to the buried cavity of Hsu] so as to contact the fuse 21 [the protection element],” [0047], see FIG. 5.
Therefore, one of ordinary skill in the art, given the teachings of Patané and Hsu, would have recognized that applying the buried cavity teachings of Hsu to the structural arrangement shown in FIG. 5 of Patané would have yielded predictable results and resulted in an improvement. The motivation for doing so would be, as expressly recognized by Hsu, to improve thermal isolation of the fuse element, yielding reduced open circuit current/voltage; additionally, the melted fuse metal can flow into the buried cavity (Hsu, [0041-0042]). These advantages result in improved programming efficiency, resulting in improved manufacturing process efficiency as well as improved device performance and reliability.
Regarding claim 9, Patané in view of Hsu teaches: The electronic device according to claim 7, wherein the covering layer includes Polyimide (PI) (Hsu, FIG. 17, polyimide 1700, [0058]) or Polyimide-Iso-IndroQuinazalinedione (PIQ).
Regarding claim 10, Patané in view of Hsu teaches: The electronic device according to claim 7, wherein the covering layer (Patané, FIG. 5, passivation layer 62, polyamide, [0038; 0047-0048]; Hsu, FIG. 17, polyimide 1700, [0058]) has a lower mechanical resistance with respect to a mechanical resistance of the body (Patané, FIG. 5, substrate 48, made of silicon carbide (SiC), [0029]). Patané teaches that by selecting a material for the passivation layer 62 [the covering layer] that has a lower mechanical strength, i.e., mechanical resistance, “the passivation layer 62 [the covering layer] allows to absorb and attenuate the products that derive from melting of the fuse 21 [the protection element] in a more effective way,” [0048].
Regarding claim 11, Patané in view of Hsu teaches: The electronic device according to claim 1, wherein the protection element includes a metal (Patané, fuse 21 [the protection element], metal, [0060]), and partially extends on the gate terminal (Patané, FIG. 5 shows fuse 21 [the protection element] partially extends on the gate region 24 [the gate terminal]), and on the conductive path (Patané, FIG. 5 shows fuse 21 [the protection element] partially extends on the connection region 36 [the conductive path]), the gate terminal and the conductive path being electrically coupled to each other exclusively by the protection element (Patané, FIGs. 2, 5, fuse 21 [the protection element] shown as the exclusive electrical coupler between gate region 24 [the gate terminal] and connection region 36 [the conductive path], electrically coupled to the generator 23 [the generator of a biasing voltage of the gate terminal]; “the fuse 21 [the protection element] is designed so as to interrupt the electrical connection between the connection region 36 [the conductive path] and the gate region 24 [the gate terminal],” [0045]).
Regarding claim 12, Patané in view of Hsu teaches: The electronic device according to claim 1, wherein the electronic device is a vertical conduction MOSFET (Patané, FIG. 2, “a vertical-channel MOSFET,” [0019]), and further includes a source terminal (Patané, FIGs. 2, 3, source region 26, [0019]) extending on the body laterally to the gate terminal at a first side of the body (Patané, FIG. 3 shows source region 26 [the source terminal] extending laterally to gate region 24 [the gate terminal], on upper surface, i.e., on the first side of the body, [0019]), and a drain terminal extending at a second side, opposite to the first side, of the body (Patané, FIGs. 2, 5, metallization layer 66, shown on bottom surface, i.e., opposite to the first side of the body, forms the second conduction terminal D [the drain terminal], [0039]).
Regarding claim 13, Patané in view of Hsu teaches: The electronic device according to claim 1, wherein the gate terminal is a strip type gate terminal (Patané, FIG. 3, gate region 24, “a strip type,” [0023]).
Regarding claim 14, Patané discloses: A method comprising: forming a gate terminal on a body including Silicon Carbide (Patané, FIG. 5, substrate 48, made of silicon carbide (SiC), [0029]); forming a conductive path on the body (Patané, FIGs. 3, 5, connection region 36, [0026]), the conductive path configured to be electrically coupled to a generator of a biasing voltage of the gate terminal (Patané, FIG. 2, 3, 5, connection region 36 [the conductive path] is “configured to be electrically coupled to the generator 23 [the generator of a biasing voltage of the gate terminal],” [0026; 0019]); forming a protection element of a solid-state material (Patané, FIGs. 2, 5, fuse 21, [0044]), coupled to the gate terminal and the conductive path (Patané, FIGs. 2, 5, fuse 21 [the protection element] shown coupled to gate region 24 [the gate terminal] and to connection region 36 [the conductive path], [0034]), the protection element being an electrical connection between the gate terminal and the conductive path (Patané, FIGs. 2, 5, “fuse 21 [the protection element] is in electrical and structural continuity with the gate region 24 [the gate terminal]. Moreover, the fuse 21 [the protection element] is in electrical and structural continuity with the connection region 36 [the conductive path],” [0034]), the protection element configured to change from a solid state to a melted or gaseous state (Patané, FIGs. 2, 5, “fuse 21 [the protection element] is designed so as to change its physical state (e.g., from solid to molten or from solid to gaseous),” [0044]), interrupting the electrical connection (Patané, FIGs. 2, 5, “fuse 21 [the protection element] is designed so as to interrupt the electrical connection between the connection region 36 [the conductive path] (connected in use to the generator 23) and the gate region 24 [the gate terminal],” [0045]), in response to a leakage current through the protection element greater than a threshold (Patané, FIGs. 2, 5, “fuse 21 [the protection element] is designed so as to change its physical state (e.g., from solid to molten or from solid to gaseous) in the presence of the short circuit current iSC … to interrupt the electrical connection between the connection region 36 [the conductive path] and the gate region 24 [the gate terminal] … in the presence of a current higher than a critical threshold that is at least one order of magnitude higher than the leakage current in normal operating conditions,” [0044-0045]);
Although Patané discloses “an opening 70 through the insulating layer 56, which reaches the fuse 21,” (Patané, FIG. 5, [0047]), i.e., forming an opening in the body accommodating the protection element, Patané does not explicitly teach that the opening forms “a buried cavity in the body”.
However, Hsu, in the same field of endeavor, teaches forming an electronic fuse for an integrated circuit, comprising: forming a buried cavity in the body (Hsu, FIG. 13, voids 1300, [0053]) accommodating, at least in part, the protection element (Hsu, FIG. 13, “voids 1300 [the buried cavity] underneath the respective fuse elements [the protection element] provide a region into which the open circuited fuse material may melt,” i.e., accommodating the protection element, [0053]). Hsu teaches that by forming a void, i.e., a cavity, below the fuse element, the fuse element is better thermally isolated, resulting in a reduced open circuit current/voltage, additionally, the melted fuse metal can flow into the void (Hsu, [0041-0042]). These advantages result in improved programming efficiency, resulting in improved manufacturing process efficiency as well as improved device performance and reliability.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Patané with the teachings of Hsu, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Hsu, to better thermally isolate the fuse element, thereby improving programming efficiency, resulting in improved manufacturing process efficiency as well as improved device performance and reliability.
Regarding claim 15, Patané in view of Hsu teaches: The method according to claim 14, further comprising: forming a support in the buried cavity, the support supporting, at least in part, the protection element (Hsu, “the fuse element [the protection element] resides … over a void [the buried cavity] in a supporting structure,” i.e., the buried cavity accommodates a support for supporting the protection element, [0010]).
Regarding claim 16, Patané in view of Hsu teaches: The method according to claim 14, wherein the protection element, the gate terminal and the conductive path form a monolithic structure (Patané, FIG. 3, “the connection region 36 [the conductive path], the plurality of fuses 21 [the protection element], and the plurality of gate regions 24 [the gate terminal] form a monolithic structure,” [0027]).
Regarding claim 17, Patané in view of Hsu teaches: The method according to claim 14, wherein the protection element (Patané, FIG. 5, fuse 21) partially extends on the gate terminal (Patané, FIG. 5 shows fuse 21 [the protection element] partially extends on the gate region 24 [the gate terminal]) and on the conductive path (Patané, FIG. 5 shows fuse 21 [the protection element] partially extends on the connection region 36 [the conductive path]), the gate terminal and the conductive path being electrically coupled to each other exclusively by the protection element (Patané, FIGs. 2, 5, fuse 21 [the protection element] shown as the exclusive electrical coupler between gate region 24 [the gate terminal] and connection region 36 [the conductive path], electrically coupled to the generator 23 [the generator of a biasing voltage of the gate terminal]; “the fuse 21 [the protection element] is designed so as to interrupt the electrical connection between the connection region 36 [the conductive path] and the gate region 24 [the gate terminal],” [0045]).
Claims 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Patané et al. US 2019/0326217 A1 (hereinafter Patané) and further in view of Brintzinger et al., U.S. Pat. No. 6,252,292 B1 (hereinafter, Brintzinger).
Regarding claim 18, Patané discloses: A device comprising: a substrate (Patané, FIG. 5, substrate 48, made of silicon carbide (SiC), [0029]); a first insulating layer on the substrate (Patané, FIG. 5, insulating layer 52, [0030]); an oxide layer on the first insulating layer (Patané, FIGs. 4, 5, field-plate-oxide layer 54, [0032]); a conductive layer on the first insulating layer and the oxide layer (Patané, FIG. 5, the conductive layer is the layer including gate region 24, fuse 21, and connection region 36, [0033-0034]); a second insulating layer on the conductive layer (Patané, FIG. 5, further insulating layer 56, [0035]), the second insulating layer including a first opening (Patané, FIG. 5 shows opening 70 [the first opening] through insulating layer 56 [the second insulating layer], [0047]) (Patané, FIG. 5, fuse 21 [the protection element], shown in opening 70 [the first opening], [0033]) (Patané, FIG. 5 shows the supporting portion of field-plate oxide layer 54 [the oxide layer] as the portion of field-plate oxide layer 54 below fuse 21 [the protection element] and in protection region 34, indicated by vertical dashed lines); first conductive material on the second insulating layer at a first side of the cavity (Patané, FIG. 5, shows metallization layer 58 [the first conductive material] on insulating layer 56 [the second insulating layer] at the right side of opening 70 [the first side of the first opening], [0036]); and second conductive material on the conductive layer, (Patané, FIG. 5 shows further metallization layer 60 [the second conductive material] on the portion of the conductive layer above connection region 36 at the left side of opening 70 [the second side of the first opening], [0026; 0037]).
Patané does not explicitly teach a second opening. However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, given the teachings of Patané, to arrive at Applicant’s claimed structural arrangement with a high likelihood of success and without undue experimentation because although Patané does not provide an illustration of the second opening, the written description of the structure indicates that a conductive material is present and crosses through insulating layer 56 [the second insulating layer] through an opening to electrically connect the connection region 36 [the conductive path] to the generator 23 [the generator of a biasing voltage of the gate terminal] by means of further metallization layer 60 [the second conductive material], (Patané, see FIGs. 2, 3, 5, [0026]).
Patané is silent regarding: a cavity in the first opening and extending into the oxide layer.
However, Brintzinger, in the same field of endeavor, discloses a vertically arranged fuse structure for a semiconductor device, comprising: a cavity in the first opening and extending into the oxide layer (Brintzinger, FIGs. 2, 4, fuse void [the cavity] shown in fuse stud cavity 23 [analogous to the first opening taught by Patané] and extending into first dielectric layer 21 [analogous to the oxide layer taught by Patané], col. 3, lines 1-6; col. 5, lines 29-43). Brintzinger teaches that a fuse structure that includes a fuse void or other cavity yields a larger separation of the fuse and therefore has a higher reliability as compared to electrical fuses lacking a cavity, see col. 4, lines 23-34.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Patané with the teachings of Brintzinger, arriving at Applicant’s claimed structural arrangement with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Brintzinger, to produce a fuse with larger separation, thereby improving device performance and reliability.
Regarding claim 19, Patané in view of Brintzinger teaches: The device according to claim 18, wherein the protection element is a portion of the conductive layer (Patané, FIG. 5, fuse 21 shown as a portion of the conductive layer that includes gate region 24, fuse 21, and, connection region 36, “the fuse 21 is in electrical and structural continuity with the gate region 24. Moreover, the fuse 21 is in electrical and structural continuity with the connection region 36,” [0034]).
Regarding claim 20, Patané in view of Brintzinger teaches: The device according to claim 18, wherein the protection element (Patané, FIG. 5, fuse 21) is another conductive layer that extends on portions of the conductive layer at the first and second sides of the cavity (Patané, FIG. 5, in an alternative embodiment, fuse 21 [the protection element] is described as being made of a different material, i.e., another conductive layer, than the portions of the conductive layer at the first and second sides of the cavity, i.e., gate region 24 and connection region 36, “fuse 21 [the protection element] may be made of a material different from the material of the gate region 24 and/or of the connection region 36,” [0060]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899