Attorney’s Docket Number: 35044-0362US
Filing Date: 08/16/2023
Claimed Foreign Priority Date: none
Applicants: Yu et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 12/09/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group Invention I, drawn to a semiconductor structure, in the reply filed on 12/09/2025, is acknowledged. Applicant cancelled claims 16-20, added new claims 21-25, and indicated that claims 1-15 and 21-25 read on the elected Group invention. The examiner agrees. Accordingly, pending in this application are claims 1-15 and 21-25.
Claim Objections
Claim 7 is objected to because of the following informalities:
- L. 1: amend to --wherein the [[at]] tubular metallics shield portion…--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 23 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 23 recites limitations identical to claim 22, from which it depends, thus fails to further limit claim 22. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu (WO2024060595 and associated Machine Translation).
Regarding Claim 1, Liu (see, e.g., Fig. 12) shows all aspects of the instant invention, including a device structure comprising a silicon interconnect die, wherein the silicon interconnect die comprises:
- a through-substrate via (TSV) structure (e.g., via interconnect structure 204) extending through a silicon substrate (e.g., silicon substrate 200)
- an insulating spacer layer (e.g., dielectric layer 203) including a horizontally-extending portion overlying a top surface of the silicon substrate and a tubular insulating material portion laterally surrounding the TSV structure
- a front metallic shield layer (e.g., grounded metal shielding layer 202) including a horizontally-extending metallic shield portion and a tubular metallic shield portion laterally surrounding the tubular insulating material portion.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu et al. (CN102130042 and associated Machine Translation).
Regarding Claim 1, Zhu (see, e.g., Fig. 4b) shows all aspects of the instant invention, including a device structure comprising a silicon interconnect die, wherein the silicon interconnect die comprises:
- a through-substrate via (TSV) structure (e.g., conductive material via 410) extending through a silicon substrate (e.g., substrate 110 of silicon)
- an insulating spacer layer (e.g., organic dielectric film 210) including a horizontally-extending portion overlying a top surface of the silicon substrate and a tubular insulating material portion laterally surrounding the TSV structure
- a front metallic shield layer (e.g., grounded seed layer 130 implementing electromagnetic shielding) including a horizontally-extending metallic shield portion and a tubular metallic shield portion laterally surrounding the tubular insulating material portion.
Regarding Claim 2, Zhu (see, e.g., Fig. 4b) shows that the tubular metallic shield portion (e.g., vertical portion of 130) is in contact with a respective cylindrical sidewall of the silicon substrate (e.g., 110).
Regarding Claim 3, Zhu (see, e.g., Fig. 4b) shows that the horizontally-extending metallic shield portion (e.g., horizontal portion of 130) contacts a top surface of the silicon substrate (e.g., 110).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 10-15, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US2022/0045008) in view of Zhu et al. (CN102130042 and associated Machine Translation).
Regarding Claim 1, Kang (see, e.g., Figs. 1-5) shows most aspects of the instant invention, including a device structure comprising a silicon interconnect die (e.g., interposer chip 120), wherein the silicon interconnect die comprises:
- a through-substrate via (TSV) structure (e.g., via 126) extending through a silicon substrate (e.g., silicon base layer 121) (see, e.g., Fig. 2)
However, Kang is silent about having an insulating spacer layer and a front metallic shield layer, as well as the remaining associated limitations. Zhu (see, e.g., Fig. 4b and Abstract), on the other hand and in the related field of electronic shielding of through holes, teaches implementing an electromagnetic shield structure around a through substrate via, to beneficially improve the electric signal transmission performance of the TSV, and reduce the interference between the TSV and neighboring circuits, wherein the electromagnetic shield structure comprises:
- an insulating spacer layer (e.g., organic dielectric film 210) including a horizontally-extending portion overlying a top surface of a silicon substrate (e.g., substrate 110 of silicon) and a tubular insulating material portion laterally surrounding a TSV structure (e.g., conductive material via 410), and
- a front metallic shield layer (e.g., grounded seed layer 130 implementing electromagnetic shielding) including a horizontally-extending metallic shield portion and a tubular metallic shield portion laterally surrounding the tubular insulating material portion.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the insulating spacer layer and a front metallic shield layer arranged as claimed in the structure of Kang, as taught by Zhu, to beneficially improve the electric signal transmission performance of the TSV, and reduce the interference between the TSV and neighboring circuits.
Therefore, Kang in view of Zhu teaches an insulating spacer layer including a horizontally-extending portion overlying a top surface of the silicon substrate and a tubular insulating material portion laterally surrounding the TSV structure; and a front metallic shield layer including a horizontally-extending metallic shield portion and a tubular metallic shield portion laterally surrounding the tubular insulating material portion.
Regarding Claim 2, Zhu (see, e.g., Fig. 4b) teaches that the tubular metallic shield portion (e.g., vertical portion of 130) is in contact with a respective cylindrical sidewall of the silicon substrate (e.g., 110).
Regarding Claim 3, Zhu (see, e.g., Fig. 4b) teaches that the horizontally-extending metallic shield portion (e.g., horizontal portion of 130) contacts a top surface of the silicon substrate (e.g., 110).
Regarding Claim 10, Kang (see, e.g., Fig. 2) shows that:
- the silicon interconnect die (e.g., 120) comprises metal interconnect structures (e.g., vertical and horizontal portions of conductive patterns 124) embedded in dielectric material layers (e.g., chip dielectric layer 125)
- the metal interconnect structures comprise metal via structures (e.g., vertical portions of 124) contacting the TSV structure (e.g., vertical portions of 124 are at least electrically contacting 126)
Regarding Claim 11, Kang (see, e.g., Figs. 1-5) shows most aspects of the instant invention, including a device structure comprising an interposer (e.g., wiring substrate 100), wherein the interposer comprises:
- a silicon interconnect die (e.g., interposer chip 120) comprising a through-substrate via (TSV) structure (e.g., via 126) extending through a silicon substrate (e.g., silicon base layer 121), and metal interconnect structures (e.g., vertical and horizontal portions of conductive patterns 124) formed in dielectric material layers (e.g., chip dielectric layer 125) and overlying the substrate (see, e.g., Fig. 2)
- a first redistribution structure (e.g., buildup portion 130) comprising first redistribution wiring interconnects (e.g., line patterns 134) formed in first redistribution dielectric layers (e.g., dielectric patterns 132) and overlying the silicon interconnect die
However, Kang is silent about having a front metallic shield layer, as well as the remaining associated limitations. Zhu (see, e.g., Fig. 4b and Abstract), on the other hand and in the related field of electronic shielding of through holes, teaches implementing an electromagnetic shield structure around a through substrate via, to beneficially improve the electric signal transmission performance of the TSV, and reduce the interference between the TSV and neighboring circuits, wherein the electromagnetic shield structure comprises:
- a front metallic shield layer (e.g., grounded seed layer 130 implementing electromagnetic shielding) including a horizontally-extending metallic shield portion overlying a top surface of a silicon substrate (e.g., substrate 110 of silicon) and a tubular metallic shield portion laterally surrounding the TSV structure.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the front metallic shield layer arranged as claimed in the structure of Kang, as taught by Zhu, to beneficially improve the electric signal transmission performance of the TSV, and reduce the interference between the TSV and neighboring circuits.
Therefore, Kang in view of Zhu teaches a front metallic shield layer including a horizontally-extending metallic shield portion overlying a top surface of the silicon substrate and a tubular metallic shield portion laterally surrounding the TSV structure, and metal interconnect structures formed in dielectric material layers and overlying the front metallic shield layer.
Regarding Claim 12, Zhu (see, e.g., Fig. 4b) teaches that the silicon interconnect die comprises an insulating spacer layer (e.g., organic dielectric film 210) including a horizontally-extending portion overlying a top surface of the silicon substrate (e.g., 110) and a tubular insulating material portion laterally surrounding the TSV structure (e.g., 410).
Regarding Claim 13, Zhu (see, e.g., Fig. 4b) teaches that the tubular metallic shield portion comprises an inner cylindrical sidewall that contacts an outer cylindrical sidewall of the tubular insulating material portion.
Regarding Claim 14, Kang (see, e.g., Figs. 1-5) shows that the interposer (e.g., 100) comprises a molding compound (MC) interposer frame (e.g., insulating layer 113 of epoxy molding compound (EMC)) laterally surrounding the silicon interconnect die (e.g., 120) and contacting a bottom surface of the first redistribution structure (e.g., 130).
Regarding Claim 15, Kang (see, e.g., Figs. 1-5) shows that the interposer (e.g., 100) comprises a second redistribution structure (e.g., buildup portion 140) comprising second redistribution wiring interconnects (e.g., line patterns 144) embedded in second redistribution dielectric layers (e.g., dielectric patterns 142) and underlying the silicon interconnect die, wherein the second redistribution wiring interconnects comprise redistribution via structures contacting bottom surfaces of the TSV structure (e.g., vertical portions of 144 are at least electrically contacting a bottom surface of 126).
Regarding Claim 21, Kang (see, e.g., Figs. 1-5) shows most aspects of the instant invention, including a semiconductor device structure, comprising:
- a silicon substrate (e.g., silicon base layer 121) having a top surface and a bottom surface
- a Through-Substrate Via (TSV) structure (e.g., via 126) extending through the silicon substrate, wherein the TSV structure comprises a conductive core portion
- a metallic interconnect stack (e.g., conductive pattern 124) formed over the top surface of the silicon substrate, the metallic interconnect stack being electrically connected to the TSV structure (see, e.g., Fig. 2).
However, Kang is silent about having a front metallic shield layer, as well as the remaining associated limitations. Zhu (see, e.g., Fig. 4b and Abstract), on the other hand and in the related field of electronic shielding of through holes, teaches implementing an electromagnetic shield structure around a through substrate via having a metallic core portion (see, e.g., Par. [0046]: conductive material 410 of gold, silver,…), to beneficially improve the electric signal transmission performance of the TSV, and reduce the interference between the TSV and neighboring circuits, wherein the electromagnetic shield structure comprises:
- a front metallic shield layer in an upper portion of a silicon substrate (e.g., substrate 110), the front metallic shield layer having a barrier layer and a metal layer (see, e.g., Par. [0042]: barrier layer of Ti/TiN, and grounded seed layer 130 of Cu, implementing an electromagnetic shielding)
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the front metallic shield layer arranged as claimed in the structure of Kang, as taught by Zhu, to beneficially improve the electric signal transmission performance of the TSV, and reduce the interference between the TSV and neighboring circuits.
Therefore, Kang in view of Zhu teaches a TSV having a metallic core portion, and a front metallic shield layer formed in an upper portion of the silicon substrate, the front metallic shield layer having a barrier layer and a metal layer.
Allowable Subject Matter
Claims 4-9, 22, and 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814