Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/451,269 filed on December 09, 2025.
Information Disclosure Statement
3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
4. Applicant’s election of claims 8-15 drawn to method, Group II, in the reply filed on 12/09/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
5. Claims 1-7 are cancelled from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected device claims, Group I, there being no allowable generic or linking claim.
6. However, the applicant has failed to mention device claims 16-20 while cancelling the claims 1-7. Therefore, the device claims 16-20 are also cancelled because these claims fall under Group I, drawn to device claims.
7. New method claims 21-27 have been added.
Specification
8. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Stress Buffer In Integrated Circuit Package Comprising Directly Bonded Integrated Circuit Dies to an Interposer .
Claim Objections
9. Claim 21 is objected to because of the following informalities: In the following, the claim should be recited to avoid indefiniteness due to lack of antecedent basis, and/or perform proper alignment along with the claim languages/phrases:
21. (Currently Amended) A method comprising:
bonding an integrated circuit die to an interposer, wherein the integrated circuit die comprises a first insulating bonding layer and a first semiconductor substrate, wherein the interposer comprises a second insulating bonding layer and a second semiconductor substrate, wherein the second insulating bonding layer is bonded to the first insulating bonding layer with dielectric-to-dielectric bonds; and
forming an encapsulant over the interposer and surrounding the integrated circuit die, wherein forming the encapsulant comprises dispensing the encapsulant between the first insulating bonding layer and the second insulating bonding layer along a line perpendicular to a major surface of the first semiconductor substrate.
Appropriate correction is needed.
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
13. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. Claim 21, 24-25, 27 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2019/0164860 A1) in view of Yang et al. (US 2017/0186798 A1).
Regarding claim 21, Lin et al. teaches a method comprising (Figs. 3-4):
bonding (see Fig. 3, para [0020]) an integrated circuit die (50A) to an interposer (70, para [0019] called wafer), wherein the integrated circuit die (50A) comprises a first insulating bonding layer (54 interconnect structure comprises insulating/dielectric layer) and a first semiconductor substrate (50A), wherein the interposer (70) comprises a second insulating bonding layer (76 interconnect structure comprises insulating/dielectric layer) and a second semiconductor substrate (72, para [0015]), wherein the second insulating bonding layer (76) is bonded to the first insulating bonding layer (54) with conductive bumps/connector (102/106/104, para [0021]) bonds; and
forming (see Fig. 4) an encapsulant (108, para [0023] called underfill material) over the interposer (70 wafer) and surrounding the integrated circuit die (50A), wherein forming the encapsulant (108) comprises dispensing the encapsulant between the first insulating bonding layer (54) and the second insulating bonding layer (76) along a line perpendicular to a major surface of the first semiconductor substrate (50A).
Lin et al. is silent to explicitly disclose, wherein the second insulating bonding layer is bonded to the first insulating bonding layer with dielectric-to-dielectric bonds.
Yang et al. discloses wherein (Fig. 1), the second insulating bonding layer (116 ILD- inter-layer dielectric, para [0021]) is bonded to the first insulating bonding layer (106 ILD- inter-layer dielectric, para [0021]) with dielectric-to-dielectric bonds (see para [0021]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yang et al. and modify the bonding structure while performing the interconnection between the integrated circuit die and the wafer of Lin et al., in order to offer/enhance superior electrical performance through reduced capacitance and resistance, while eliminating solder bumps to enhance bandwidth, density, and thermal management.
Regarding claim 24, Lin et al. and Yang et al. teach all of the limitations of claim 21 from which this claim depends.
Lin et al. teaches wherein, bonding (see Fig. 3) the integrated circuit die (50A) to the interposer (70) comprises contacting the first insulating bonding layer (54) to the second insulating bonding layer (76) at an interface (102/106/104), and wherein forming (see Fig. 4) the encapsulant (108) comprises dispensing the encapsulant into the interface (102/106/104) between the first insulating bonding layer (54) and the second insulating bonding layer (76).
Regarding claim 25, Lin et al. and Yang et al. teach all of the limitations of claim 21 from which this claim depends.
Lin et al. teaches wherein (Fig. 4), the encapsulant (108) comprises filler materials (underfill material, para [0023]), and wherein the filler materials (108) are disposed between the first insulating bonding layer (54) and the second insulating bonding layer (76) along the line perpendicular to the major surface of the first semiconductor substrate (50A).
Regarding claim 27, Lin et al. and Yang et al. teach all of the limitations of claim 21 from which this claim depends.
Lin et al. is silent to explicitly disclose, wherein bonding the integrated circuit die to the interposer further comprises:
bonding first bonding pads to second bonding pads with metal-to-metal bonding, wherein the first bonding pads are in the first insulating bonding layer, and wherein the second bonding pads are in the second insulating bonding layer.
Yang et al. teaches wherein (Fig. 1), bonding the imaging chip (112, para [0021]) to the CMOS chip (102, para [0021]) further comprises:
bonding first bonding pads (117a metal layer, para [0021]) to second bonding pads (107a metal layer, para [0021]) with metal-to-metal bonding (para [0021]), wherein the first bonding pads (117a) are in the first insulating bonding layer (116: see the annotated figure below), and wherein the second bonding pads (107a, see the annotated figure below) are in the second insulating bonding layer (106).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Yang et al. and modify the bonding structure between the integrated circuit dies and the wafer of Lin et al., in order to provide/enhance superior structural strength through uniform stress distribution, enhanced corrosion resistance, and the ability to join dissimilar materials without thermal distortion.
15. Claim 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2019/0164860 A1) in view of Yang et al. (US 2017/0186798 A1) as applied to claim 21 above, and further in view of Wang et al. (US 2022/0310501 A1).
Regarding claim 22, Lin et al. and Yang et al. teach all of the limitations of claim 21 from which this claim depends.
Lin et al. and Yang et al. are silent to explicitly disclose, further comprising singulating the integrated circuit die from a plurality of integrated circuit dies, wherein singulating the integrated circuit die comprises forming a chamfer-shaped corner in the first insulating bonding layer a top-down view.
Wang et al. discloses wherein (Fig. 3, para [0030]), further comprising singulating the integrated circuit die (120a) from a plurality of integrated circuit dies (120a/120b), wherein singulating the integrated circuit die comprises forming a chamfer-shaped corner (chamfered corner CC, para [0035]) in the first insulating bonding layer a top-down view (see Fig. 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Wang et al. and singulate the wafer into multiple individual dies with chamfered corner, in order to effectively reduce thermally-induced stress caused due to CTE mismatch between the semiconductor package and the package substrate and experienced by the encapsulant, thereby avoiding the crack and/or delamination issue of the encapsulant and enhancing the reliability of the package structure (para [0037]).
Regarding claim 23, Lin et al. and Yang et al. and Wang et al. teach all of the limitations of claim 22 from which this claim depends.
Wang et al. discloses wherein (Fig. 3, para [0030]), the first semiconductor substrate (120) has a right-angle corner in a top-down view (see Fig. 3) after singulating the integrated circuit die (120a) from the plurality of integrated circuit dies (120: 120a/120b).
16. Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2019/0164860 A1) in view of Yang et al. (US 2017/0186798 A1) as applied to claim 21 above, and further in view of Uzoh et al. (US 2017/0338214 A1).
Regarding claim 26, Lin et al. and Yang et al. teach all of the limitations of claim 21 from which this claim depends.
Lin et al. and Yang et al. are silent to explicitly disclose, further comprising forming a void in the encapsulant, wherein the void is disposed between the first insulating bonding layer and the second insulating bonding layer along the line perpendicular to the major surface of the first semiconductor substrate.
Uzoh et al. discloses wherein (Fig. 3O), further comprising forming a void (37, para [0056]) in the encapsulant (15 filler layer, para [0057]), wherein the void (37) is disposed between the first insulating bonding layer (36) and the second insulating bonding layer (34) along the line perpendicular to the major surface of the first semiconductor substrate (2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the encapsulant or filler material with any suitable material comprising voids or pores as taught by Uzoh et al. between the integrated circuit dies of Lin et al. and Yang et al., in order to facilitate planarization (para [0057]).
Allowable Subject Matter
17. Claims 8-15 are allowed.
18. The following is an examiner’s statement of reasons for allowance:
Claim 8: the prior art of record alone or in combination neither teaches nor makes obvious a method comprising:
Claim 8 recites….
performing a plasma dicing process to define a first recess in a first insulating bonding layer, wherein the first insulating bonding layer is disposed over a semiconductor substrate, and wherein a bottom surface of the first recess is above a top surface of the semiconductor substrate; and
performing a sawing process through the first recess and the semiconductor substrate to separate the first integrated circuit die from the second integrated circuit die;
directly bonding the first integrated circuit die to an interposer, wherein the first insulating bonding layer is directly bonded to a second insulating bonding layer of the interposer by dielectric-to-dielectric bonding; and
encapsulating the first integrated circuit die with an encapsulant, wherein encapsulating the first integrated circuit die comprises dispensing the encapsulant into a gap between the first insulating bonding layer and the second insulating bonding layer.
The prior art, Lin et al. (US 2019/0164860 A1) or Yang et al. (US 2017/0186798 A1) does not disclose the processing steps- plasma dicing defines a recess in the insulating layer wherein a bottom surface of the recess is above a top surface of the semiconductor substrate; then next step of performing sawing process through the recess and singulate the wafer into individual integrated dies. Therefore, none of the prior art of references quoted in PTO-892, discloses the limitations as stated above.
Examiner’s Note
19. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
20. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
21. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812