Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Kao et al. (US-20220223635-A1 referred as Kao).
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Regarding claim 21. Kao discloses a pixel sensor array, comprising:
a plurality of pixel sensors ([0017], [0047], [0061], figure 2h, a plurality of pixel sensors #PD which is further seen in the pixel region #R1 in figure 3a);
a trench isolation structure disposed between the plurality of pixel sensors ([0028], [0083], figure 2h, the trench isolation structure is made up of #P1a, #116 and #117 as described which are disposed between the plurality of pixel sensors #PD),
wherein the trench isolation structure is included through a semiconductor layer of the pixel sensor array ([0028], figure 2h, the trench isolation structure (#P1a/#116/#117) is included through a semiconductor layer #100),
wherein a first portion of the trench isolation structure is surrounded by a first polysilicon well under the semiconductor layer ([0047], [0044], figure 2h annotated above, a first portion of the trench isolation structure #Pos1 is surrounded by a first polysilicon well #81a under the semiconductor layer #100), and
wherein a second portion of the trench isolation structure is surrounded by a second polysilicon well under the semiconductor layer ([0047], figure 2h annotated above, a second portion of the trench isolation structure #Pos2 is surrounded by a second polysilicon well #81b under the semiconductor layer #100), and
a contact etch stop layer (CESL) disposed around sidewalls and under a bottom surface of the first polysilicon well, disposed around sidewalls and under a bottom surface of the second polysilicon well, and disposed between the first polysilicon well and the second polysilicon well ([0050], figure 2h annotated above, a contact etch stop layer #85/107 (containing silicon oxide) is seen disposed around and in between the first polysilicon well #81a and the second polysilicon well #81b).
Regarding claim 22. Kao discloses a first sidewall spacer disposed around sidewalls of the first polysilicon well ([0047], figure 2h annotated above, a first sidewall spacer is seen disposed around the sidewalls of the first polysilicon well #81a); and a second sidewall spacer disposed around sidewalls of the second polysilicon well ([0047], figure 2h annotated above, a second sidewall spacer is seen disposed around the sidewalls of the second polysilicon well #82b).
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Regarding claim 23. Kao discloses wherein the first portion of the trench isolation structure is between two pixel sensors of the plurality of pixel sensors ([0024], figure 3a annotated above, a first portion of the trench isolation structure #Pos1 is seen as #NCRP between two vertical pixels sensors #PD), and
wherein the second portion of the trench isolation structure is at a corner of at least three pixel sensors of the plurality of pixel sensors ([0024], figure 3a annotated above, a second portion of the trench isolation structure #Pos2 is seen as #CRP at a corner of three vertical and horizontal pixel sensors #PD).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US-20220223635-A1 referred as Kao), in view of Choi et al. (US-20230039809-A1 referred as Choi).
Regarding claim 1. Kao discloses a pixel sensor array, comprising:
a plurality of pixel sensors ([0017], [0047], [0061], figure 2h, a plurality of pixel sensors #PD which is further seen in the pixel region #R1 in figure 3a); and
a backside deep trench isolation (BDTI) structure at least laterally surrounding the plurality of pixel sensors ([0028], [0083], figure 2h, the BDTI structure is made up of #P1a, #116 and #117 as described which laterally surrounds the plurality of pixel sensors #PD),
wherein the BDTI structure is included through a semiconductor layer of the pixel sensor array between a front side of the semiconductor layer and a backside of the semiconductor layer ([0028], figure 2h, the BDTI structure (#P1a/#116/#117) is included through a semiconductor layer #100 which extends from the front side and the backside of the semiconductor layer #100 as described), and
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wherein a first portion of the BDTI structure is surrounded by a first polysilicon well under the semiconductor layer ([0047], [0044], figure 2h annotated above, a first portion of the BDTI structure #Por1 is surrounded by a first polysilicon well #81a under the semiconductor layer #100. Please note that there is a portion of the semiconductor layer #100 is seen over the polysilicon well #81), and
and wherein a second portion of the BDTI structure is surrounded by a second polysilicon well under the semiconductor layer ([0050], figure 2h annotated above, the second portion of the BDTI structure #Por2 is seen surrounded by a second polysilicon #81b well under the semiconductor layer #100); and
a contact etch stop layer (CESL) disposed around the first polysilicon well, disposed around the second polysilicon well, and disposed between the first polysilicon well and the second polysilicon well ([0050], figure 2h annotated above, a contact etch stop layer #85/107 (containing silicon oxide) is seen disposed around and in between the first polysilicon well #81a and the second polysilicon well #81b).
Kao lacks wherein the BDTI structure is included fully through a semiconductor layer.
Choi discloses wherein the BDTI structure is included fully through a semiconductor layer ([0077], figure 8, the BDTI structure #226 is seen fully through the semiconductor layer #220).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao to include a BDTI structure fully through a semiconductor layer as taught by Choi in order to increase the devices integrity, reduce unwanted electrical signals, and to enhance the devices efficiency.
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Regarding claim 2. Kao as modified discloses wherein the first portion of the BDTI structure is a non-cross-road portion of the BDTI structure between two pixel sensors of the plurality of pixel sensors ([0034], figure 3a annotated above, the first portion of the BDTI structure #Por1 is seen as the non-cross-road portion #NCRP which is in between two pixel sensors #PD in the vertical direction); and
wherein the second portion of the BDTI structure is a cross-road portion of the BDTI structure, at a corner of at least three pixel sensors of the plurality of pixel sensors ([0034] [0044], figure 3a annotated above, the second portion of the BDTI structure #Por2 is seen as a cross-road portion #CRP surrounded by more than three pixel sensors #PD in the vertical and horizontal direction).
Regarding claim 3. Kao as modified lacks wherein a first distance between a bottom of the first polysilicon well and a bottom of the non-cross-road portion of the BDTI structure is greater than a second distance between a bottom of the second polysilicon well and a bottom of the cross-road portion of the BDTI structure.
MPEP 2144.04 IV A - describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified for Kao as modified to include first distance between a bottom of the first polysilicon well and a bottom of the non-cross-road portion of the BDTI structure is greater than a second distance between a bottom of the second polysilicon well and a bottom of the cross-road portion of the BDTI structure in order to distribute the overall weight of the device, improve device reliability, and potentially reduce stress concentrations.
Regarding claim 4. Kao as modified discloses wherein the first polysilicon well is configured to be electrically biased to increase hole density around the first portion of the BDTI structure ([0044] [0028], figure 2h, the first polysilicon well #81a is doped which could be configured to be electrically biased to increase hole density around the portion of the BDTI structure).
Regarding claim 7. Kao as modified discloses wherein the BDTI structure comprises: a polysilicon trench structures arranged in an interconnected grid around the plurality of pixel sensors ([0061], [0044], figure 2c, a polysilicon trench structures #P1a is seen arranged in a interconnected grid around the plurality of pixel sensors #PD. Please note the interconnected grid is further seen in figure 3a with respect to the pixels #PD placement); and
one or more dielectric liners between the polysilicon trench structures and the semiconductor layer ([0025], figure 2c, one dielectric liner #116 is seen in between the polysilicon trench structure #P1a and the semiconductor layer #100), wherein the portion of the BDTI structure is electrically coupled with the first polysilicon well ([0044], figure 2c, a portion of the BDTI structure (more specifically #Por1) is seen and also described to be electrically coupled to the first polysilicon well #81a).
Regarding claim 8. Kao as modified discloses wherein the first portion of the BDTI structure is configured to be electrically biased through the first polysilicon well to increase hole density around the first portion of the BDTI structure ([0061], [0044], figure 2c, the portion of the BDTI structure (more specifically #P1a) and the polysilicon well #81a is doped which could be configured to be electrically biased to increase hole density around the portion of the BDTI structure #Por1).
Regarding claim 9. Kao as modified discloses wherein the one or more dielectric liners comprise at least one of: an oxide-containing dielectric liner, or a high dielectric constant (high-k) dielectric liner ([0070], figure 2c, the dielectric liner #116 comprises of an oxide containing dielectric liner as described).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US-20220223635-A1 referred as Kao) and Choi et al. (US-20230039809-A1 referred as Choi), in further view of Peng et al. (US-6492263-B1 referred as Peng) and Cheng et al. (US-20210335861-A1 referred as Cheng).
Regarding claim 5. Chen as modified lacks wherein a dielectric sidewall spacer is included around sidewalls of the polysilicon well;
wherein the CESL is included around the dielectric sidewall spacer and under a bottom surface of the first polysilicon well; and
wherein the second portion of the BDTI structure is a non-cross-road portion of the BDTI structure between two pixel sensors of the plurality of pixel sensors, and is surrounded by a portion of the CESL.
Peng discloses wherein a dielectric sidewall spacer is included around sidewalls of the polysilicon well ([col 5 lines 4-34], figure 3d, the dielectric sidewall spacer #50 is seen around the sidewalls of the polysilicon well #52);
wherein the CESL is included around the dielectric sidewall spacer and under a bottom surface of the first polysilicon well ([col 5 lines 4-34], figure 3d, the contact etch stop layer #36 is seen around the dielectric sidewall spacer #50 and under a bottom surface of the first polysilicon well #52).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao as modified to include a dielectric sidewall spacer and a contact etch stop layer (CESL) as taught by Pang in order to increase the electrical protection, provide safety steps in the manufacturing process, and to enhance the devices lifetime.
Kao as modified by Pang still lacks wherein the second portion of the BDTI structure is a non-cross-road portion of the BDTI structure between two pixel sensors of the plurality of pixel sensors, and is surrounded by a portion of the CESL.
Cheng discloses wherein the second portion of the BDTI structure is a non-cross-road portion of the BDTI structure between two pixel sensors of the plurality of pixel sensors, and is surrounded by a portion of the CESL ([0024], figure 3, the second portion of the BDTI structure is a non-cross-road portion of the BDTI structure #111 at the center of two sensors #104a is seen surrounded by a portion of the CESL #110 underneath it).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao as modified by Pang to include a portion of the CESL surrounding a portion of the BDTI structure as taught by Cheng in order to increase manufacturing speed, reduce waste in material, and to increase etching safety measures.
Regarding claim 6. Chen as modified lacks wherein a dielectric sidewall spacer is included around sidewalls of the first polysilicon well;
wherein a hard mask layer is included under a bottom surface of the first polysilicon well;
wherein the CESL is included under and around the dielectric sidewall spacer and the hard mask layer; and
wherein the second portion of the BDTI structure is a non-cross-road portion of the BDTI structure, between two pixel sensors of the plurality of pixel sensors, is surrounded by a portion of the CESL.
Peng discloses wherein a dielectric sidewall spacer is included around sidewalls of the polysilicon well ([col 5 lines 4-34], figure 3d, the dielectric sidewall spacer #50 is seen around the sidewalls of the polysilicon well #52);
wherein a hard mask layer is included under a bottom surface of the polysilicon well ([col 5 lines 4-34], figure 3d, the hard mask layer #51 is included under a bottom surface of the polysilicon well #52);
wherein the CESL is included under and around the dielectric sidewall spacer and the hard mask layer ([col 5 lines 4-34], figure 3d, the contact etch stop layer #36 is seen around the dielectric sidewall spacer #50 and the hard mask layer #51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao as modified to include a dielectric sidewall spacer, hard mask layer, and a contact etch stop layer (CESL) as taught by Pang in order to increase the electrical protection, provide safety steps in the manufacturing process, and to enhance the devices lifetime.
Kao as modified by Pang still lacks wherein the second portion of the BDTI structure is a non-cross-road portion of the BDTI structure between two pixel sensors of the plurality of pixel sensors, is surrounded by a portion of the CESL.
Cheng discloses wherein the second portion of the BDTI structure is a non-cross-road portion of the BDTI structure between two pixel sensors of the plurality of pixel sensors, is surrounded by a portion of the CESL ([0024], figure 3, the second portion of the BDTI structure is a non-cross-road portion of the BDTI structure #111 at the center of two sensors #104a is seen surrounded by a portion of the CESL #110 underneath it).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao as modified by Pang to include a portion of the CESL surrounding a portion of the BDTI structure as taught by Cheng in order to increase manufacturing speed, reduce waste in material, and to increase etching safety measures.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US-20220223635-A1 referred as Kao) and Choi et al. (US-20230039809-A1 referred as Choi), in view of Sze et al. (US-20200176500-A1 referred as Sze).
Regarding claim 17. Kao discloses a pixel sensor array, comprising:
a plurality of pixel sensors ([0017], [0047], [0061], figure 2e, a plurality of pixel sensors #PD which is further seen in the pixel region #R1 in figure 3a); and
a backside deep trench isolation (BDTI) structure that is included through a semiconductor layer of the pixel sensor array between a front side of the semiconductor layer and a backside of the semiconductor layer ([0028], figure 2e, the BDTI structure (#P1a/#116/#117) is included through a semiconductor layer #100 which extends from the front side and the backside of the semiconductor layer #100 as described),
wherein a bottom portion of the BDTI structure is surrounded by one or more dielectric layers under the semiconductor layer ([0050], figure 2e, a bottom portion of the BDTI structure (#P1a/#116/#117) is surrounded by one dielectric layer #80 under the semiconductor layer #100),
wherein a ring-shaped well is included around the bottom portion of the BDTI structure in the one or more dielectric layers ([0047], figure 2e, a ring-shaped well #81 is included around a bottom portion of the BDTI structure (#P1a/#116/#117) in the one dielectric layer #80),
wherein the one or more dielectric layers comprise a contact etch stop layer (CESL) around and under the ring-shaped polysilicon well ([0050], figure 2h, the CESL #84/107 are seen around and under the ring-shaped polysilicon well #81) ; and
wherein the CESL is included between the ring-shaped polysilicon well and another ring-shaped polysilicon well around another bottom portion of the BDTI structure ([0050], figure 2h, the CESL #84/107 are seen between the ring shaped polysilicon well #81 and another ring shaped polysilicon well #81 underneath another bottom portion of the BDTI strucutere).
Kao lacks a backside deep trench isolation (BDTI) structure that is included fully through a semiconductor layer; and a ring-shaped polysilicon well.
Choi discloses wherein the BDTI structure is included fully through a semiconductor layer ([0077], figure 8, the BDTI structure #226 is seen fully through the semiconductor layer #220).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao to include a BDTI structure fully through a semiconductor layer as taught by Choi in order to increase the devices integrity, reduce unwanted electrical signals, and to enhance the devices efficiency.
Kao as modified by Choi still lacks a ring-shaped polysilicon well.
Sze discloses a ring-shaped polysilicon well ([0032], figure 1, the ring-shaped polysilicon well #124 can be seen and described in the specifications).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao as modified by Choi to include a ring-shaped polysilicon well as taught by Sze in order to have an improved isolation while increasing the signal integrity, and also to reduce noise and interference.
Regarding claim 18. Kao as modified lacks wherein the one or more dielectric layers further comprise an oxide layer between the ring-shaped polysilicon well and the BDTI structure.
Sze discloses wherein the one or more dielectric layers comprise an oxide layer between the ring-shaped polysilicon well and the BDTI structure ([0032], figure 1, the one dielectric layer #126 comprises of an oxide layer which also is positioned in between the ring shaped polysilicon well #124 and the BDTI structure #118).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao as modified to include one or more dielectric layers comprise an oxide layer between the ring-shaped polysilicon well and the BDTI structure as taught by Sze in order to have an a high dielectric constants, provide thermal stability, and to enhance the electrical resistivity.
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Annotated figure 2e – close up
Regarding claim 19. Kao as modified discloses wherein the one or more dielectric layers further comprise a silicon nitride (SixNy) spacer layer between the ring-shaped polysilicon well and the BDTI structure ([0044], annotated figure 2e – close up, the one dielectric layer #80 comprises of silicon nitride is seen between the ring-shaped polysilicon well #102a and the BDTI structure (#P1a/#116/#117) – noting that you can draw a line starting from well #102a go through dielectric layer #80 and end at the BDTI structure, therefore, dielectric layer #80 is broadly is ‘between’).
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US-20220223635-A1 referred as Kao).
Regarding claim 24. Kao lacks wherein a first distance between a bottom of the first polysilicon well and a bottom of the first portion of the trench isolation structure is greater than a second distance between a bottom of the second polysilicon well and a bottom of the second portion of the trench isolation structure.
MPEP 2144.04 IV A - describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified for Kao to include a first distance between a bottom of the first polysilicon well and a bottom of the first portion of the trench isolation structure is greater than a second distance between a bottom of the second polysilicon well and a bottom of the second portion of the trench isolation structure in order to distribute the overall weight of the device, improve device reliability, and potentially reduce stress concentrations.
Claims 26, 27, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US-20220223635-A1 referred as Kao) in view of Ho et al. (US-10290535-B1 referred as Ho).
Regarding claim 26. Kao lacks wherein comprising one or more electrodes coupled to at least one the first polysilicon well or the second polysilicon well.
Ho discloses wherein comprising one or more electrodes coupled to at least one the first polysilicon well or the second polysilicon well ([col 3, lines 50-54], figure 2, electrode #224 is seen coupled to the second polysilicon well #208).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao to include wherein comprising one or more electrodes coupled to at least one the first polysilicon well or the second polysilicon well as taught by Ho in order to offer greater device versatility, reduce long distance circuit paths, and to reduce total weight of the device.
Regarding claim 27. Kao discloses further comprising wherein the second portion of the trench isolation structure is at a corner of at least three pixel sensors of the plurality of pixel sensors ([0047], [0044], figure 2e annotated above, wherein the second portion of the trench isolation structure #Pos2 is further seen as #NCRP in annotated figure 3a annotated above being in between three pixel sensors #PD).
Kao lacks further comprising a hard mask layer under a bottom surface of the second polysilicon well.
Ho discloses further comprising a hard mask layer under a bottom surface of the second polysilicon well ([col 3, lines 50-54], figure 2, a hard mask layer #210 is seen under a bottom surface of the second polysilicon well #208)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao to include wherein comprising one or more electrodes coupled to at least one the first polysilicon well or the second polysilicon well as taught by Ho in order to provide additional protection to the circuitry, distribute the weight across the device and to extend the devices lifetime.
Regarding claim 29. Kao lacks further comprising one or more electrodes coupled to at least one of the first polysilicon well or the second polysilicon well to provide a voltage bias to at least one of the first polysilicon well or the second polysilicon well.
Ho discloses further comprising one or more electrodes coupled to at least one of the first polysilicon well or the second polysilicon well to provide a voltage bias to at least one of the first polysilicon well or the second polysilicon well ([col 4, lines 52-56], figure 2, electrode #224 coupled to the second polysilicon well is able to provide voltage bias through its conductivity, as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao to include wherein comprising one or more electrodes coupled to at least one the first polysilicon well or the second polysilicon well as taught by Ho in order to offer greater device versatility, reduce long distance circuit paths, and to maximize the circuitries voltage.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (US-20220223635-A1 referred as Kao) and Choi et al. (US-20230039809-A1 referred as Choi), in further view of Ho et al. (US-10290535-B1 referred as Ho).
Regarding claim 28, Kao as modified lacks further comprising one or more electrodes coupled to at least one of the first polysilicon well or the second polysilicon well to provide a voltage bias to at least one of the first polysilicon well or the second polysilicon well.
Ho discloses further comprising one or more electrodes coupled to at least one of the first polysilicon well or the second polysilicon well to provide a voltage bias to at least one of the first polysilicon well or the second polysilicon well ([col 4, lines 52-56], figure 2, electrode #224 coupled to the second polysilicon well is able to provide voltage bias through its conductivity, as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kao to include wherein comprising one or more electrodes coupled to at least one the first polysilicon well or the second polysilicon well as taught by Ho in order to offer greater device versatility, reduce long distance circuit paths, and to maximize the circuitries voltage.
Response to Amendment
Applicant's arguments filed 04/02/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art to Kao et al. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Regarding claim 1, claim 17, and claim 21.. As can be seen in the new rejection above, because of the new consideration applied using broadest reasonable interpretation, a new interpretation of the previous prior art to Kao et al. has been applied. Regrettably, this interpretation was not realized in the limited amount of time allotted to prepare for an interview. It is recommended to further amend the BDTI structure to have multiple sides in contact with and surrounded by the first and second polysilicon wells (making clear language that overcomes one side of the BDTI structure being surrounded [fully contacting and encompassed] by the polysilicon wells). Proceeding with this amendment will overcome the broadest reasonable interpretation which is using the bottom part of the BDTI structure and the sides of the BDTI structure of “surrounded by the first/second polysilicon well”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action (new reference to Ho was applied to new claims 28 and 29). Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272 - 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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