DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election (which is considered as without traverse since Applicants did not traverse) of claims 14-25 in the reply filed on 04/21/26 is acknowledged.
Claims 1-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/17/23 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14-15, 17-21 and 23-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2017/0301559).
a. Re claim 14, Wang et al. disclose a semiconductor device, comprising: a substrate 310 (see fig. 3D and related text; see remaining of disclosure for more details); a first conductive post 321 (or 321&541) formed over the substrate; a second conductive post 323 (or 323&543) formed over the substrate; a flux material (461, 463; [0042]) disposed over a top surface of the first conductive post and second conductive post; a first electrical component 651 ([0042]) disposed over the flux material on the first conductive post; and a second electrical component 652 disposed over the flux material on the second conductive post, wherein the flux material maintains position of the first electrical component and second electrical component to avoid contact between the first electrical component and second electrical component (see [0043]).
b. Re claim 15, the flux material includes a flux print material ([0046]).
c. Re claim 17, the first conductive post (when it is 321&541) includes a first portion 321 of a first conductive layer 321-324 formed over the substrate and a first portion 541 of a second conductive layer 541-544 formed over the first portion of the first conductive layer; and the second conductive post (when it is 323&543) includes a second portion 323 of the first conductive layer formed over the substrate and a second portion 543 of the second conductive layer formed over the second portion of the first conductive layer.
d. Re claim 18, a thickness of the second conductive layer (thickness at the middle, which is the thickest, for each layer 541, 542, 543, 544) is greater than a thickness of the first conductive layer (this explicit on figs. 3C-D).
e. Re claim 19, the semiconductor device of claim 14, further includes an encapsulant (molded compound disclosed in [0044]) deposited over the first electrical component and second electrical component.
f. Re claim 20, Wang et al. disclose a semiconductor device, comprising: a substrate 310 (see fig. 3D and related text; see remaining of disclosure for more details); a first conductive post 321 (or 321&541) formed over the substrate; a second conductive post 323 (or 323&543) formed over the substrate; a flux material (461, 463; [0042]) disposed over a top surface of the first conductive post and second conductive post; a first electrical component 651 disposed over the flux material on the first conductive post; and a second electrical component 652 disposed over the flux material on the second conductive post, wherein the flux material maintains separation between the first electrical component and second electrical component (see [0043]).
g. Re claims 21, 23, 24 and 25, see respectively claims 15, 17, 18 and 19 rejections above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 and 22 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2017/0301559) in view of Morti et al. (US 2007/0145575, cited on IDS).
a. Re claim 16, Wang et al. disclose all the limitations of claim 14 as stated above except explicitly for the semiconductor device of claim 20, further including a pre-solder material disposed on a contact pad of the first electrical component and on a contact pad of the second electrical component, wherein the pre-solder material contacts the flux material with the first electrical component and second electrical component disposed over the flux material.
However, Morti et al. disclose providing a pre-solder layer 43 on a contact pad 41 of an electrical component 4 to be bonded to electrodes 31 bearing a flux 73 on their top surfaces (see fig. 9B, [0155]-[0158]).
As such, and noting that the pair of unlabeled rectangles on opposite sides of each components 651 and 652 are conventionally known in the art to represent contact pads (or electrodes) of surface mount components (SMT) such as components 651&652, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided a layer of pre-solder on the contact pads of components 651 and 652, and this as a non-inventive step of applying a known boding technique in order to bond an electronic component to an electrode or interconnect structure or something obvious to try with a reasonable expection of success for enhanced bonding (see MPEP 2143. D&E).
b. Re claim 22, see claim 16 rejection above wherein the same rationale applies, noting that Wang et al. disclose all the limitations of claim 20 as stated above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
Prosecution Insights