Prosecution Insights
Last updated: October 01, 2026
Application No. 18/451,923

DIVIDING METHOD OF WAFER

Non-Final OA §102§103
Filed
Aug 18, 2023
Priority
Aug 26, 2022 — JP 2022-134988
Examiner
VU, HUNG K
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
DISCO Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
892 granted / 1018 resolved
+19.6% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
35 currently pending
Career history
1043
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
43.8%
+3.8% vs TC avg
§102
37.1%
-2.9% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1018 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 03/06/2026 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 4-5 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kazunao et al. (JP 2004-228218 A). Regarding claim 1, Kazunao et al. discloses, as shown in Figures 3-13, a dividing method [0020] of a wafer (10) by which the wafer having device regions marked out by a plurality of planned dividing lines that intersect in a front surface is divided along the planned dividing lines, the dividing method comprising: a back surface grinding step of grinding a back surface of the wafer ([0022], grinding back surface 10b of semiconductor wafer 10, Fig. 8); a dividing step of dividing the wafer from the front surface along the planned dividing lines to form a plurality of chips ([0022], Fig. 9, semiconductor wafer (10) is separated into individual semiconductor chips 100); and a first energy supply step of supplying energy to at least any part of edges, back surfaces, and side surfaces of the chips from the back surface of the wafer and melting the at least any part to repair at least part of processing strain ([0023]-[0024], irradiating the peripheral edge of the back surface of each semiconductor chip 100 with a laser beam/ [0027], the peripheral edge of the semiconductor chip 100 is melted). An energy supply step of repairing at least a part of the processing strain (the bonding strength of the semiconductor chip is weakened due to the influence of fine microcracks and strains / [0028], the internal stress (sigma, σ) generated inside the semiconductor chip is called the bonding strength / [0031], the semiconductor chip chamfered by irradiating the peripheral edge of the back surface of the semiconductor chip with a laser beam has a bonding strength four times that of a semiconductor chip of the same size divided by a conventional method / for these descriptions the bonding strength is improved by irradiation with a laser beam, that is, the internal stress, and the distortion is improved. Regarding claim 2, Kazunao et al. discloses, as shown in Figures, a dividing method [0020] of a wafer (10) by which the wafer having device regions marked out by a plurality of planned dividing lines that intersect in a front surface is divided along the planned dividing lines, the dividing method comprising: a processing groove forming step of forming processing grooves deeper than a finished thickness in the wafer from the front surface ([0020], Fig. 5, forming a dividing groove 111 along a street 101); a back surface grinding step of grinding the wafer (10) to the finished thickness from a back surface of the wafer to divide the wafer and form a plurality of chips after execution of the processing groove forming step ([0022], Fig. 8, grinding the back surface 10b of the semiconductor wafer 10 having a protective member 8 attached to the front surface, exposing the dividing groove 111 on the back surface 10b, and dividing the wafer into individual semiconductor chips (dividing groove exposing step)); and a first energy supply step of supplying energy to at least any part of edges, back surfaces, and side surfaces of the chips from the back surface of the wafer and melting ([0023], irradiating a peripheral edge of the back surface of each semiconductor chip 100 with a laser beam / [0027], the peripheral edge of the semiconductor chip 100 is melted), the at least any part to repair at least part of processing strain ([0003], the bending strength of the semiconductor chip is weakened due to the influence of fine microcracks and strains / [0028], the internal stress (sigma, σ) generated inside the semiconductor chip is called bending strength / [0031], a semiconductor chip chamfered by irradiating a peripheral edge of a back surface of the semiconductor chip with a laser beam has a bending strength four times that of a semiconductor chip of the same size divided by a conventional method). Regarding claim 4, Kazunao et al. discloses the first energy providing step is a step of irradiating laser light ([0026]-[0031], the first energy providing step is a step of irradiating laser light). Regarding claim 5, Kazunao et al. discloses a wavelength of the laser beam is a wavelength having absorbability with respect to the wafer ([0026]-0027, the wafer is melted and chambered 110). Regarding claim 7, Kazunao et al. discloses the method further comprising: a second energy supply step of supplying energy to at least any part of the edges, the back surfaces, and the side surfaces of the chips from the front surface of the wafer and melting the at least any part ([0016]-[0017], a pulse laser beam having a predetermined repetition frequency). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kazunao et al. (JP 2004-228218 A). Kazunao et al. discloses the claimed invention including the diving method as explained in the above rejection. Kazunao et al. further discloses at [0016]-[0017] and [0026] that the wavelength is set to a predetermined value (the YAG laser or YVO4 laser wavelength = 355 nm). Kazunao et al. does not the wavelength of the laser beam is a wavelength in a range of 500 to 1000 nm. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, thickness, range, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, range, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934). Allowable Subject Matter Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Applicant' s claim 3 is allowable over the references of record because none of these references disclose or can be combined to yield the claimed first energy supply step includes a side surface exposure step of pushing up chips of a supply target of the energy relatively compared with other chips and exposing side surfaces of the chips of the supply target of the energy, and the energy is supplied to the side surfaces exposed in the side surface exposure step, as recited in claim 3. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JACOB CHOI can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUNG K VU/ Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Aug 18, 2023
Application Filed
Dec 30, 2025
Examiner Interview (Telephonic)
Mar 06, 2026
Request for Continued Examination
Aug 20, 2026
Response after Non-Final Action
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+9.4%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1018 resolved cases by this examiner. Grant probability derived from career allowance rate.

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