DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election
Applicant’s election of claims #1-12 and 21-28 in the reply filed on January 6, 2026 is acknowledged. Because the Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
IDS
The IDS document(s) filed on April 25, 2024, June 10, 2025, October 13, 2025 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “forming a source/drain region contacting an end of each of a first semiconductor layer and a second semiconductor layer …wherein a portion of the gate stack is between the first semiconductor layer and the second semiconductor layer, wherein the portion of the gate stack contacts the dielectric inner spacer” (claim 21) and “forming a gate stack underlying a semiconductor layer; forming an inner spacer underlying the gate stack, wherein both of the gate stack and the inner spacer are in contact with a bottom surface of the semiconductor layer” (claim 26) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections – 35 U.S.C. § 112(a)
The following is a quotation of 35 U.S.C. § 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 21-25 and 26-28 are rejected under 35 U.S.C. § 112(a) or pre-AIA 35 U.S.C. § 112, first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
As to claim 21, the limitation “forming a source/drain region contacting an end of each of a first semiconductor layer and a second semiconductor layer…wherein a portion of the gate stack is between the first semiconductor layer and the second semiconductor layer, wherein the portion of the gate stack contacts the dielectric inner spacer” comprises new matter. Refer to the 35 U.S.C. § 112(b) rejection below.
As to claim 26, the limitation “forming a gate stack underlying a semiconductor layer; forming an inner spacer underlying the gate stack, wherein both of the gate stack and the inner spacer are in contact with a bottom surface of the semiconductor layer” comprises new matter. Refer to the 35 U.S.C. § 112(b) rejection below.
Claim Rejections – 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 21-25 and 26-28 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
As to claim 21, the limitation “forming a source/drain region contacting an end of each of a first semiconductor layer and a second semiconductor layer…wherein a portion of the gate stack is between the first semiconductor layer and the second semiconductor layer, wherein the portion of the gate stack contacts the dielectric inner spacer” (emphasis added) is unclear.
Specifically, it is unclear how a source/drain region 48 contacts an end of each of a first semiconductor layer 22A and a second semiconductor layer 22B. FIG. 9B of the instant application shows the source/drain region 48 unable to contact an end of the first semiconductor layer 22A because of the inner spacer 44.
Furthermore, it is unclear how a portion of the gate stack (30/34 or 68/70) is between the first semiconductor layer 22A and the second semiconductor layer 22B and the same portion of the gate stack contacts the dielectric inner spacer 44. This limitation is not illustrated in corresponding FIGS. 6A-17.
As to claim 26, the limitation the “forming a gate stack underlying a semiconductor layer; forming an inner spacer underlying the gate stack, wherein both of the gate stack and the inner spacer are in contact with a bottom surface of the semiconductor layer” (emphasis added) is unclear.
Specifically, it is unclear how a gate stack (30/34 or 68/70) underlies a semiconductor layer 22A/22B. The claim construction “gate stack underlying a semiconductor layer” makes it clear that it is the gate stack that underlies or lies below the semiconductor layer. Compare with the subsequent limitation “forming an inner spacer underlying the gate stack” which employs the same construction and teaches the inner spacer 44 underlying or lying below the gate stack. The drawings do not show the gate stack underlying semiconductor layer 22A/22B or any other semiconductor layer.
Furthermore, it is unclear how the gate stack and the inner spacer 44 are in contact with a bottom surface of the semiconductor layer if the gate stack underlies or lies below the semiconductor layer. In FIGS. 5A-17, the gate stack (30/34 or 68/70) is formed above the semiconductor layer 22A/22B and therefore cannot contact a bottom surface of the semiconductor layer.
Indication of Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter: “performing a treatment process to reduce dielectric constant values of the inner spacers” (claim 1).
As to claim 1, Peng et al. (U.S. Patent Publication No. 2021/00831091 A1), hereafter “Peng”, teaches forming a stack of layers 204 comprising: a plurality of semiconductor nanostructures 208 and a plurality of sacrificial layers 206, wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly (FIGS. 2A-4); laterally recessing (FIG. 5) the plurality of sacrificial layers to form lateral recesses 226; depositing (FIG. 6) a spacer layer 228 extending into the lateral recesses; trimming (FIG. 8) the spacer layer to form inner spacers 228; performing (FIG. 7C) a treatment process 500.
However Peng does not teach the treatment process to reduce dielectric constant values of the inner spacers because Peng explicitly teaches away from this limitation as the treatment process does not materially change the property nor structure of the inner spacer layer, including its dielectric constant. See Peng, ¶ [0036].
No Prior Art Applied
The Examiner was unable to find prior art applicable to the claims 21-28 as presently written and in view of the unclear claim language.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUBERR L CHI/Primary Examiner, Art Unit 2893
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