DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
All references provided in the IDS have been considered.
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-17) in the reply filed on 02/06/26 is acknowledged. Examiner notes the addition of claims 21-23 drawn to Group I.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0061], line 9 describes a “TCTT” parameter. No such parameter is defined. It has been interpreted to mean “TCCT” parameter.
Appropriate correction is required.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 3, 4, 5, 21, 22, and 23 are provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 9, 5, 3, 1, 3, and 9, respectively, of copending Application No. 19/287,418 (continuing application, published as US 2025/0364259 A1). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4, line 1 recites “third TCC” parameter. Such a parameter has not been defined. It has been taken to mean “TCCT” parameter. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang (US 20200044045 A1).
Re: Independent Claim 1, Wang discloses:
A method (Wang, Fig. 1), comprising:
forming a fin (Wang, not labeled, Fig. 3B, not numbered, the fin including elements 218, 216, 211, 222, 220, 224, and 204) protruding from a substrate (Wang, substrate; Fig. 3B, element 202), the fin including an epitaxial stack (Wang, semiconductor materials; Fig. 4A, elements 204A, 204B) over a fin base (Wang, bottom most part of the fin; Fig. 3B, element 204) and a hard mask layer (Wang, first hard mask layer, second hard mask layer, and dielectric layer; Fig. 4A, elements 216, 218, and 228, respectively make up the hard mask layer ¶ [0033]) over the epitaxial stack, the epitaxial stack including first (Wang, first semiconductor material; Fig. 3B, element 204A) and second semiconductor (Wang, second semiconductor layer; Fig. 3B, element 204B) layers of different material compositions (Wang, ¶ [0023] discloses that 204A includes while 204B includes SiGe);
performing a first etching process to etch the hard mask layer (Wang mentions the layer 228 functions as a hard mask so that the subsequent etching process is applied to the desired regions, ¶ [0033], which can be called a first etching process, step 110), the first etching process including applying a first combination of etchants (Wang, ¶ [0034] discloses the etchants can include a bromine-containing gas, a fluorine-containing gas,..etc. the combination of which can be considered a first combination of etchants);
performing a second etching process to etch the epitaxial stack (Wang, ¶ [0035] discloses that the etching process substantially etches both semiconductor materials, elements 204B and 204A), may be removed during the etching process, which can be considered a second etching process, step 112), the second etching process including applying a second combination of etchants (Wang, ¶[0035], which can be considered a second group of etchants); and
performing a third etching process to etch the fin base (Wang, ¶ [0044] discloses an etching process to remove the second semiconductor material, element 204B. Fig. 3B, shows that by etching this layer (204B), it would be etching the fin base. This can be considered a third etching process, step 126),
Wang does not explicitly disclose:
wherein the first, second, and third combinations of etchants are different from each other.
Wang discloses that the etching process may utilize an etchant including a bromine-containing gas (e.g., HBr and/or CHBR.sub.3), a fluorine-containing gas (e.g., CF.sub.4, SF.sub.6, CH.sub.2F.sub.2, CHF.sub.3, and/or C.sub.2F.sub.6), other suitable gases, or combinations thereof. Wang also discloses that the second and third etching processes may utilize HF and/or NH.sub.4OH as an etchant. It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to select different etchant chemistries for the second and third etching processes from the disclosed etchants in order to tailor etch selectivity, rate, and material compatibility for the different layers being process. Etchants are recognized as result-effective variables in semiconductor fabrication and yields predictable results. Selecting a different combination of etchants for the first, second, and third etchants, from the disclosed lists of etchants would have been an obvious to a POSITA with reasonable expectation of success to selectively etch the desired layers with different etch rates.
Claim 2 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang (US 20200044045 A1) in view of Kumar (US20020003126A1), and further in view of Chang (US20180233451).
Re: Claim 2, Wang discloses all the limitations of claim 1 on which this claim depends. Wang further discloses:
wherein etchants includes CHF3 (Wang, CHF3, ¶ [0034])
Wang does not explicitly disclose:
wherein the first combination of etchants includes CHF3 and S02
Kumar discloses:
the first combination of etchants includes CHF3 and S02 (Kumar, a source gas includes a fluorine containing compound, sulfur dioxide is added to the plasma source gas, ¶ [0011]).
Wang discloses etching processes utilizing an etchant including a bromine-containing gas (e.g., HBr and/or CHBR.sub.3), a fluorine-containing gas (e.g., CF.sub.4, SF.sub.6, CH.sub.2F.sub.2, CHF.sub.3, and/or C.sub.2F.sub.6), other suitable gases, or combinations thereof, but does not explicitly disclose SO2 to be used in combination with CHF3. Kumar discloses that adding sulfur dioxide (SO2) to a fluorine containing compound in a plasma source gas. Both Wang and Kumar disclose etching processes and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include CHF3 and SO2 as a first combination of etchants to improve on anisotropic or isotropic etching processes (Kumar, ¶ [0011]).
Wang further discloses:
CF4 (Wang, CF.sub.4, ¶ [0034]),
Wang does not explicitly disclose:
the second combination of etchants includes CF4
Wang discloses etching processes utilizing an etchant including a bromine-containing gas (e.g., HBr and/or CHBR.sub.3), a fluorine-containing gas (e.g., CF.sub.4, SF.sub.6, CH.sub.2F.sub.2, CHF.sub.3, and/or C.sub.2F.sub.6), other suitable gases, or combinations thereof, but does not explicitly disclose CH4 as the second combination of etchants, as recited in the claim. It would have been obvious to a POSITA before the effective filing date to include CF4 in the second combination of etchants as Wang identifies it as a suitable etchant in this process. A POSITA would have reasonably selected CF4 from the disclosed list of suitable etchants in the second combination in order to achieve desired etching characteristics, like the etching rate. Such selection of a known etchant from a finite set of disclosed options would have been a matter of routine optimization.
Wang further discloses:
and CH2F2 (Wang, CH.sub.2F.sub2, ¶ [0034]), SF6 (Wang, SF.sub.6, ¶ [0034]).
Wang does not explicitly disclose:
and the third combination of etchants includes CH2F2, SF6, and CH3F.
Chang further discloses:
and the third combination of etchants includes CH2F2, SF6, and CH3F. (Chang, an etching gas used in the first etching process could be selected from the group consisting of NF3, SF6, CH2F2, CH3F, and CHF3, ¶ [0018]).
Wang discloses etching processes utilizing an etchant including a bromine-containing gas (e.g., HBr and/or CHBR.sub.3), a fluorine-containing gas (e.g., CF.sub.4, SF.sub.6, CH.sub.2F.sub.2, CHF.sub.3, and/or C.sub.2F.sub.6), other suitable gases, or combinations thereof, but does not explicitly disclose CH3F used in combination with CH2F2 and SF6 as the third combination of etchants, as recited in the claim. Chang discloses an etching gas used in an etching process could be selected from the group consisting of NF3, SF6, CH2F2, CH3F, and CHF3 for use in etching silicon nitride. Both Wang and Chang discloses etching processes and are therefore analogous arts. It would have been obvious to a POSITA before the effective filing date to include CH2F2, SF6, and CH3F as a third combination of etchants to selectively etch a conductive layer while protecting the material layer (Chang, ¶ [0018]).
Claims 3-5, 7-8, 11-14, and 21-23 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang (US 20200044045 A1) in view of Tan (US 20220035247 A1).
Re: Claim 3, Wang discloses all the limitations of claim 1 on which this claim depends. Wang further discloses:
the first etching process (Wang, ¶ [0034]) Wang is silent regarding:
wherein: the first etching process includes applying a first transformer-coupled capacitive tuning (TCCT) parameter,
the second etching process includes applying a second TCCT parameter,
the third etching process includes applying a third TCCT parameter, and
the first TCCT parameter is different from the second and third TCCT parameters.
Tan discloses:
wherein: the first etching process (Tan, embodiment 1; Table 7, can be considered a first etching process) includes applying a first transformer-coupled capacitive tuning (TCCT) parameter (Tan, Table 7, embodiment 1 has a TCCT value of 0.2-1.2),
Wang generally discloses that etching processes may include dry etching, wet etching, reactive ion etching (RIE) and/or other suitable methods (Wang, ¶ [0033]). Wang does not explicitly disclose transformer-couple capacitive tuning (TCCT) parameters. Tan discloses etching processes using TCCT parameters as a part of general deposition conditions within a processing chamber (Tan, ¶ [0098]). Both Wang and Tan disclose semiconductor processing and fabrication and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include TCCT parameters in the etching process of Wang to improve etching efficiency (Tan, ¶ [0102]).
Tan further discloses:
the second etching process (Tan, embodiment 4; Table 4, can be considered a second etching process) includes applying a second TCCT parameter (Tan, Table 4, embodiment 4 has a TCCT value of 1.3)
the third etching process (Tan, embodiment 9, Table 7) includes applying a third TCCT parameter (Tan, table 7, embodiment 9 has a TCCT value of 1.3), and
the first TCCT parameter is different from the second and third TCCT parameters.
Re: Claim 4, Wang and Tan disclose all the limitations of claim 3 on which this claim depends. Tan further discloses:
wherein the second (Tan, Table 4, embodiment 4 has a TCCT value of 1.3) and third TCCT parameters (Tan, table 7, embodiment 9 has a TCCT value of 1.3) have a same value (Tan, table 4 and table 7 show that embodiment 4 and embodiment 9 have the same TCCT value of 1.3).
Re: Claim 5, Wang and Tan disclose all the limitations of claim 3 on which this claim depends. Tan further discloses:
wherein the first TCCT parameter (Tan, Table 7, embodiment 1 has a TCCT value of 0.2-1.2) is smaller than the second and third TCCT parameters (Tan, the first TCCT parameter is between 0.2-1.2, and the second and third TCCT parameters have a value of 1.3, which is larger than the first TCCT parameter)
Re: Claim 7, Wang discloses all the limitations of claim 1 on which this claim depends. Wang further discloses:
wherein: the hard mask layer (Wang, first hard mask layer, second hard mask layer, and dielectric layer; Fig. 4A, elements 216, 218, and 228, respectively make up the hard mask layer ¶ [0033]) includes a nitride layer (Wang, first hard mask layer, Fig. 4A, element 216, ¶ [0029]) and an oxide layer (Wang, second hard mask layer; Fig. 4A, element 218, ¶ [0029)] over the nitride layer,
the first etching process includes a first etching step to etch the oxide layer (Wang, ¶ [0034]) and a second etching step to etch the nitride layer (Wang, ¶ [0034])
Wang is silent regarding:
the first etching process includes a first etching step to etch the oxide layer with a first transformer-coupled capacitive tuning (TCCT) parameter and a second etching step to etch the nitride layer with a second TCCT parameter, and
and the first TCCT parameter is larger than the second TCCT parameter.
Tan discloses:
a first transformer-coupled capacitive tuning (TCCT) parameter (Tan, Table 7, embodiment 9 has a TCCT value of 1.3), and a second TCCT parameter (Tan, Table 7, embodiment 1 has a TCCT value of 0.2-1.2), and the first TCCT parameter is larger than the second TCCT parameter.
Wang generally discloses that etching processes may include dry etching, wet etching, reactive ion etching (RIE) and/or other suitable methods (Wang, ¶ [0033]). Wang does not disclose transformer-couple capacitive tuning (TCCT) parameters. Tan discloses etching processes using TCCT parameters as a part of general deposition conditions within a processing chamber (Tan, ¶ [0098]). Both Wang and Tan disclose semiconductor processing and fabrication and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include TCCT parameters in the etching process of Wang, therefore meeting the invention as claimed, to improve etch resistance of different layers (Tan, ¶ [0102]).
Re: Claim 8, Wang and Tan disclose all the limitations of claim 7 on which this claim depends. Wang further discloses:
wherein: the first etching step (Wang, ¶ [0034]) includes applying the first combination of etchants (Wang, ¶ [0034] discloses the etchants can include a bromine-containing gas, a fluorine-containing gas,..etc. the combination of which can be considered the first combination of etchants),
the second etching step (Wang, ¶ [0034])
Wang is silent regarding:
the second etching step includes applying a fourth combination of etchants,
Wang discloses etching processes utilizing an etchant including a bromine-containing gas (e.g., HBr and/or CHBR.sub.3), a fluorine-containing gas (e.g., CF.sub.4, SF.sub.6, CH.sub.2F.sub.2, CHF.sub.3, and/or C.sub.2F.sub.6), other suitable gases, or combinations thereof. Wang does not explicitly disclose the second etching step includes applying a fourth combination of etchants. Etchant, used by themselves, and in combination, are recognized as result-effective variables in semiconductor fabrication and yield predictable results. It would have been obvious to a POSITA before the effective filing date to apply a fourth combination of etchants to the second etching step for selective etching of the layer.
Wang is also silent regarding:
and the first combination of etchants is different from the fourth combination of etchants.
Wang discloses etching processes utilizing an etchant including a bromine-containing gas (e.g., HBr and/or CHBR.sub.3), a fluorine-containing gas (e.g., CF.sub.4, SF.sub.6, CH.sub.2F.sub.2, CHF.sub.3, and/or C.sub.2F.sub.6), other suitable gases, or combinations thereof. Wang does not explicitly disclose that the first combination of etchants is different from the fourth combination of etchants. It would have been obvious to a POSITA before the effective filing date to utilize different combinations of etchants for different etching steps, including selecting a fourth combination of etchants that differs from the first combination of etchants, as Wang explicitly discloses use of alternative etchants and combinations. Selecting particular etchant combinations from the numerous disclosed etchants and combinations thereof for different process steps would have been a matter of routine optimization for different etching characteristics, yielding predictable results of selective etching.
Re: Independent Claim 11, Wang discloses:
A method (Wang, Fig. 1) , comprising:
forming a fin (Wang, not labeled, Fig. 3B, not numbered, the fin including elements 218, 216, 211, 222, 220, 224, and 204) protruding from a substrate (Wang, substrate; Fig. 3B, element 202), the fin including a dielectric portion (Wang, first spacer layer; Fig. 3B, element 220) over a semiconductor portion (Wang, semiconductor fins; Fig. 3B, element 204);
forming a bottom resist layer (Wang, first hard mask layer; Fig. 3B, element 216) over the dielectric portion of the fin;
forming a middle resist layer (Wang, second hard mask layer; Fig. 3B, element 218) over the bottom resist layer;
performing a first plasma etching process to etch the middle resist layer (Wang, ¶ [0034 - 0044]),
performing a second plasma etching process to etch the bottom resist layer (Wang, ¶ [0034 - 0044]),
and performing a third plasma etching process to etch the fin (Wang, ¶ [0034 - 0044]),
Wang is silent regarding:
performing a first plasma etching process to etch the middle resist layer with a first set of plasma etching parameters;
performing a second plasma etching process to etch the bottom resist layer with a second set of plasma etching parameters;
and performing a third plasma etching process to etch the fin with a third set of plasma etching parameters,
wherein the first, second, and third sets of plasma etching parameters are different from each other.
Tan discloses:
a first set of plasma etching parameters (Tan, Table 7, embodiment 1, which is a first set of plasma etching parameters),
a second set of plasma etching parameters (Tan, Table 4, embodiment 4, which is a second set of plasma etching parameters);
a third set of plasma etching parameters (Tan, table 7, embodiment 9, which is a third set of plasma etching parameters)
wherein the first, second, and third sets of plasma etching parameters are different from each other.
Wang generally discloses that etching processes may include dry etching, wet etching, reactive ion etching (RIE) and/or other suitable methods (Wang, ¶ [0033]). Wang does not disclose plasma etching parameters. Tan discloses etching processes using plasma etching parameters as a part of general deposition conditions within a processing chamber (Tan, ¶ [0098], such as for a plasma chamber. Both Wang and Tan disclose semiconductor processing and fabrication and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include plasma etching parameters in the plasma etching process of Wang to improve the etching process (Tan, ¶ [0102]).
Re: Claim 12, Wang and Tan disclose all the limitations of claim 11 on which this claim depends. Tan further discloses:
wherein:
the first plasma etching parameters (Tan, Table 7, embodiment 1, which is a first set of plasma etching parameters) includes a first transformer-coupled capacitive tuning (TCCT) parameter (Tan, table 7 shows a TCCT parameter of 0.2 - 1.2, which is a first TCCT parameter),
the second plasma etching parameters (Tan, Table 4, embodiment 4, which is a second set of plasma etching parameters) includes a second TCCT parameter (Tan, table 4 shows a TCCT parameter of 1.3 which is a second TCCT parameter),
the third plasma etching parameters (Tan, table 7, embodiment 9, which is a third set of plasma etching parameters) includes a third TCCT parameter (Tan, table 7 shows the TCCT parameter to be 1.3, which is a third TCCT parameter), and
and the first TCCT parameter is different from the second TCCT parameter and different from the third TCCT parameter.
Re: Claim 13, Wang and Tan disclose all the limitations of claim 12 on which this claim depends. Tan further discloses:
wherein the second TCCT parameter (Tan, table 4 shows a TCCT parameter of 1.3 which is a second TCCT parameter) equals the third TCCT parameter (Tan, table 7 shows the TCCT parameter to be 1.3, which is a third TCCT parameter).
Re: Claim 14, Wang and Tan disclose all the limitations of claim 12 on which this claim depends. Tan is silent regarding:
wherein the second TCCT parameter is different from the third TCCT parameter.
Tan discloses the second TCCT parameter and third TCCT parameter, but does not explicitly disclose them to be different. Tan explicitly discloses that the TCCT parameter can be from 0.1 to 1.5 as an overall parameter to manipulate to improve etching efficiency (Tan, ¶ [0102]). It would have been obvious to be a POSITA before the effective filing date to select a TCCT parameter from the disclosed range of TCCT parameters, such that the second and third TCCT parameters are different, yielding a predictable result of influencing etch resistance for different layers (Tan, ¶ [0102]).
Re: Independent Claim 21, Wang discloses:
A method (Wang, Fig. 1), comprising:
forming a fin (Wang, not labeled, Fig. 3B, not numbered, the fin including elements 218, 216, 211, 222, 220, 224, and 204) protruding from a substrate (Wang, substrate; Fig. 3B, element 202), the fin including an epitaxial stack (Wang, semiconductor materials; Fig. 4A, elements 204A, 204B) over a fin base (Wang, bottom most part of the fin; Fig. 3B, element 204) and a hard mask layer (Wang, first hard mask layer, second hard mask layer, and dielectric layer; Fig. 4A, elements 216, 218, and 228, respectively make up the hard mask layer ¶ [0033]) over the epitaxial stack, the epitaxial stack including first (Wang, first semiconductor material; Fig. 3B, element 204A) and second semiconductor (Wang, second semiconductor layer; Fig. 3B, element 204B) layers of different material compositions (Wang, ¶ [0023] discloses that 204A includes while 204B includes SiGe);
performing a first etching process to etch the hard mask layer (Wang mentions the layer 228 functions as a hard mask so that the subsequent etching process is applied to the desired regions, ¶ [0033], which can be called a first etching process, step 110),
Wang is silent regarding:
wherein: the first etching process includes applying a first transformer-coupled capacitive tuning (TCCT) parameter;
Tan discloses:
wherein: the first etching process (Tan, embodiment 1; Table 7, can be considered a first etching process) includes applying a first transformer-coupled capacitive tuning (TCCT) parameter (Tan, Table 7, embodiment 1 has a TCCT value of 0.2-1.2),
the second etching process (Tan, embodiment 4; Table 4, can be considered a second etching process) includes applying a second TCCT parameter (Tan, Table 4, embodiment 4 has a TCCT value of 1.3)
the third etching process (Tan, embodiment 9, Table 7) includes applying a third TCCT parameter (Tan, table 7, embodiment 9 has a TCCT value of 1.3),
wherein the first TCCT parameter is different from the second TCCT parameter
wherein the first TCCT parameter is different from the third TCCT parameter
Wang generally discloses that etching processes may include dry etching, wet etching, reactive ion etching (RIE) and/or other suitable methods (Wang, ¶ [0033]). Wang does not explicitly disclose transformer-couple capacitive tuning (TCCT) parameters. Tan discloses etching processes using multiple TCCT parameters as a part of general deposition conditions within a processing chamber (Tan, ¶ [0098]) for controlling etching characteristics. Both Wang and Tan disclose semiconductor processing and fabrication and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include and/or combine one or more TCCT parameters in the etching process of Wang to improve etching efficiency (Tan, ¶ [0102]), since such parameters are recognized in the art to affect etch outcomes.
Wang, as modified by Tan further discloses:
performing a second etching process to etch the epitaxial stack (Wang, ¶ [0035] discloses that the etching process substantially etches both semiconductor materials, elements 204B and 204A), may be removed during the etching process, which can be considered a second etching process, step 112)
and performing a third etching process to etch the fin base (Wang, ¶ [0044] discloses an etching process to remove the second semiconductor material, element 204B. Fig. 3B, shows that by etching this layer (204B), it would be etching the fin base. This can be considered a third etching process, step 126),
Re: Claim 22, Wang and Tan disclose all the limitations of claim 21 on which this claim depends. Tan further discloses:
wherein the first TCCT parameter (Tan, Table 7, embodiment 1 has a TCCT value of 0.2-1.2) is smaller than either of the second (Tan, Table 4, embodiment 4 has a TCCT value of 1.3) and third (Tan, table 7, embodiment 9 has a TCCT value of 1.3) TCCT parameters.
Re: Claim 23, Wang and Tan disclose all the limitations of claim 21 on which this claim depends. Wang further discloses:
wherein the first etching process including applying a first combination of etchants (Wang, ¶ [0034] discloses the etchants can include a bromine-containing gas, a fluorine-containing gas,..etc. the combination of which can be considered a first combination of etchants), the second etching process including applying a second combination of etchants (Wang, ¶ [0035] , which can be considered a second group of etchants), the third etching process including applying a third combination of etchants (Wang, ¶ [0044] discloses the process uses Hf and/or NH_4OH as an etchant, which can be considered the third combination of etchants),
Wang does not explicitly disclose:
and the first, second, and third combinations of etchants are different from each other.
Wang discloses that the first etching process may utilize an etchant including a bromine-containing gas (e.g., HBr and/or CHBR.sub.3), a fluorine-containing gas (e.g., CF.sub.4, SF.sub.6, CH.sub.2F.sub.2, CHF.sub.3, and/or C.sub.2F.sub.6), other suitable gases, or combinations thereof. Wang also discloses that the second and third etching processes may utilize HF and/or NH.sub.4OH as an etchant. It would have been obvious to a POSITA before the effective filing date to select different etchant chemistries for the second and third etching processes from the disclosed etchants in order to tailor etch selectivity, rate, and material compatibility for the different layers being process. Etchants are recognized as result-effective variables in semiconductor fabrication and yields predictable results. Selecting combinations of etchants that are different from each other, amongst the disclosed list of etchants, would have been an obvious design choice with reasonable expectation of success to selectively etch the desired layers as etchants are known to have different etching chemistries.
Claim 6 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang (US 20200044045 A1) in view of Tan (US 20220035247 A1), and in further view of Arghavani (US 9396961 B2).
Re: Claim 6, Wang and Tan disclose all the limitations of claim 3 on which this claim depends. Tan further discloses:
wherein the first TCCT parameter (Tan, Table 7, embodiment 1 has a TCCT value of 0.2-1.2) is in a range between 0 and 2 (Tan, the disclosed range of the first TCCT parameter is within the disclosed range),
Tan is silent regarding:
and the second and third TCCT parameters are in a range between 2 and 4.
Tan discloses a range for TCCT parameters as a part of general deposition conditions within a processing chamber (Tan, ¶ [0098]), but does not disclose this range for the second and third TCCT parameters within a range between 2 and 4. In the absence of any indication that the claimed range is critical or produces unexpected results, it would have been obvious to a POSITA to optimize the TCCT parameter through routine experimentation, resulting in a selection of a value between 2-4 to achieve suitable deposition conditions, as higher TCCT ratios are known to promote high degree for plasma uniformity and etch conductive materials (Arghavani, Col. 5, lines 47-60)
Claims 9-10 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang (US 20200044045 A1) in view of Bih (US 9396961 B2).
Re: Claim 9, Wang discloses all the limitations of claim 1 on which this claim depends. Wang further discloses:
a third etching process (Wang, ¶[0044])
Wang does not explicitly disclose:
wherein: the third etching process includes a first etching step and a second etching step following the first etching step,
the first etching step includes a first lateral etching rate,
the second etching step includes a second lateral etching rate,
and the first lateral etching rate is smaller than the second lateral etching rate.
Bih discloses:
wherein: the etching process (Bih, the etching process; Fig. 2, element 100) includes a first etching step (Bih, a first etching step; ¶ [0033]) and a second etching step (Bih, a second etching step; ¶ [0033]) following the first etching step (Bih, ¶ [0033]),
the first etching step includes a first lateral etching rate (Bih, "each etching step has an associated lateral etching rate" ¶ [0029]),
the second etching step includes a second lateral etching rate (Bih, "each etching step has an associated lateral etching rate" ¶ [0029]),
and the first lateral etching rate is smaller than the second lateral etching rate (Bih, "each subsequent etching step has a greater lateral etching rate than a previous etching step", ¶ [0029]).
Wang discloses a third etching process but does not explicitly disclose the third etching process to include a first etching step and a second etching step following the first etching step, each with lateral etching rates. Bih discloses an etching process which includes a first etching step and a second etching step for forming an upside-down trapezoidal shape of a stack. Both Wang and Bih disclose semiconductor devices and fabrication and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include a first etching step and a second etching step, with different etchants and lateral etching rates, to control the shape and configure the etching characteristics of a stack (Bih, ¶ [0029]).
Re: Claim 10, Wang and Bih disclose all the limitations of claim 9 on which this claim depends. Bih further discloses:
wherein the second etching step (Bih, a second etching step; ¶ [0033]) increases a concentration of one etchant (Bih, "the fluorine content in the etchant increases with each etching step", ¶ [0033]) in the third combination of etchants (Bih, the fluorine containing etchants, ¶ [0030], are within the third group of etchants) compared to the first etching step (Bih, a first etching step; ¶ [0033]).
Claims 15-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang (US 20200044045 A1) in view of Tan (US 20220035247 A1), and in further view of Bih (US 9396961 B2).
Re: Claim 15, Wang and Tan disclose all the limitations of claim 11 on which this claim depends. Wang, as modified by Tan, further discloses:
wherein: the third plasma etching process (Wang, dry etch process, ¶ [0034 - 0044]) to etch the dielectric portion (Wang, first spacer layer; Fig. 3B, element 220) of the fin (Wang, not labeled, Fig. 3B, not numbered, the fin including elements 218, 216, 211, 222, 220, 224, and 204);
Wang and Tan do not explicitly disclose:
wherein: the third plasma etching process includes a first plasma etching step to etch the dielectric portion of the fin with the third set of plasma etching parameters,
the third plasma etching process includes a second plasma etching step to etch the semiconductor portion of the fin with a fourth set of plasma etching parameters, and
the third set of plasma etching parameters is different from the fourth set of plasma etching parameters.
Bih discloses:
the plasma etching process (Bih, the etching process; Fig. 2, element 100, ¶ [0030]) includes a first plasma etching step (Bih, first etching step; Fig. 2) to etch the portion of the fin (Bih, gate structure; Fig. 2, element 120A) with the third set of plasma etching parameters (Bih, ¶ [0030], the disclosed etching conditions can be considered the third set of plasma etching parameters),
Wang, as modified by Tan, disclose a third etching process but do not explicitly disclose this third etching process to include a first plasma etching step to etch the dielectric portion of the fin with a third set of plasma etching parameters. Bih discloses first and second plasma etching steps with plasma etching parameters to change the profile/shape for later fabrication stages. Wang, Tan, and Bih disclose semiconductor fabrication and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include plasma etching steps and etching parameters to an etching process to tailor the shape or profile of the fin and potentially reduce the number of voids (Bih, ¶ [0018]).
Bih further discloses:
the third plasma etching process (Bih, etching process; Fig. 2, element 100) includes a second plasma etching step (Bih, second etching step, ¶ [0033])) to etch the semiconductor portion (Bih, polysilicon layer; Fig. 2, element 80) of the fin (Bih, gate structure; Fig. 2, element 120A) with a fourth set of plasma etching parameters (Bih, ¶ [0030], the disclosed etching conditions can be considered a fourth set of etching parameters)
Bih does not explicitly disclose:
and the third set of plasma etching parameters is different from the fourth set of plasma etching parameters.
Bih discloses many non-limiting etching parameters (i.e. plasma with a flow rate of 30 - 36 sccm, etchants including fluorine, such as C_xF_y, where x and y are positive integers, Bih [0030 - 0032])) but does not explicitly disclose the third set of plasma etching parameters to be different from the fourth set of etching parameters. Bih does disclose that the flow rates of the fluorine containing etchants might be different for different etching steps to etch different portions of the portion of the fin (Bih, ¶ [0033]). A POSITA before the effective filing date would be motivated to select a different set of etching parameters for the third set and the fourth set of plasma etching parameters to selectively etch the portions of the fin more effectively by increasing the lateral etching rate of the etching process (Bih, ¶ [0033]).
Re: Claim 16, Wang, Tan, and Bih disclose all the limitations of claim 15 on which this claim depends. Bih further discloses:
wherein the second plasma etching step (Bih, a second etching step; ¶ [0033]) includes etching the semiconductor portion (Bih, polysilicon layer; Fig. 2, element 80) of the fin (Bih, gate structure; Fig. 2, element 120A) with a first lateral etching rate (Bih, ¶ [0029], can be considered the first lateral etching rate associated with the second etching step) and etching the semiconductor portion of the fin with a second lateral etching rate that is larger than the first lateral etching rate (Bih, "each subsequent etching step has a greater lateral etching rate than a previous etching step", ¶ [0029]).
Re: Claim 17, Wang and Tan disclose all the limitations of claim 11 on which this claim depends. Wang, as modified by Tan, discloses:
a third plasma etching process to etch the fin (Wang, ¶ [0034 - 0044]),
Wang, as modified by Tan, is silent regarding:
wherein the performing of the third plasma etching process creates an edge of the fin, and the edge of the fin from top to bottom tilts inwardly towards the fin.
Bih discloses:
wherein the performing of the third plasma etching process (Bih, etching process; Fig. 2, element 100) creates an edge of the fin (Bih, gate structure; Fig. 2, element 120A, has an edge), and the edge of the fin from top to bottom tilts inwardly towards the fin (Bih, Fig. 2, shows element 120A has an edge tilting inwardly toward the fin from top to bottom).
Wang and Tan disclose a third plasma etching process but do not explicitly disclose this etching process to create an edge of the fin and the edge of the fin tilting inwardly towards the fin. Bih discloses first and second plasma etching steps with plasma etching parameters to change the profile/shape for later fabrication stages. Wang, Tan, and Bih disclose semiconductor fabrication and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to include plasma etching steps and etching parameters to the etching process of Wang, as modified by Tan, to tailor the shape or profile of the fin and potentially reduce the number of voids (Bih, ¶ [0018]) for better device utilization.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 7:00 AM - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights