Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 01/20/2026 have been fully considered but they are not persuasive.
The Applicant argues that in regard to claims 1 and 12 that the combination of Park and Cho prior art, does not teach the limitation of the “wherein a slope of sidewalls of the first sub-layer and the second sub-layer, which are connected to each other, varies continuously.”
In response to this argument, the Examiner directs the applicant’s attention to the combination of Park and Cho prior art, which clearly teaches that wherein a slope of sidewalls of the first sub-layer (sML2) and the second sub-layer (sML3), which are connected to each other, varies continuously (see Park, Fig.10 as shown below).
In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004).
The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the combination of Park and Cho prior art reference does meet all the limitation in claims 1 and 12.
Allowable Subject Matter
Claims 16-17 and 19-28 are allowed.
The following is an examiner’s statement of reasons for allowance:
The primary reason for the allowance of the claim is the inclusion of the limitation “wherein the forming of the second sub-layer and the forming of the third conductive layer are concurrently performed in a same process” as recited in independent claim 16, in all of the claims which is not found in the prior art references.
Claims 17 and 19-28 are allowed for the same reasons as claim 16, from which they depend.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2022/0310972 A1, hereinafter refer to Park) in view of Cho et al. (U.S. 2021/0249498 A1, hereinafter refer to Cho).
Regarding Claim 1: Park discloses a display device (see Park, Figs.6-7 as shown below and ¶ [0002]) comprising:
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a substrate (100) having a transmission area (TA), a display area (DA) extending around a periphery of the transmission area (TA), and an intermediate area (MA) between the transmission area (TA) and the display area (DA) (see Park, Fig.6 as shown above);
a first active layer (Act) on the substrate (100) and comprising a first active pattern (Act) in the display area (DA) (see Park, Fig.6 as shown above);
a first conductive layer (GE) on the first active layer (Act) and comprising a gate electrode (GE) overlapping the first active pattern (Act) (see Park, Fig.6 as shown above);
a first sub-layer (sML2) in the intermediate area (MA) and on the second conductive layer (CE2), the first sub-layer (sML2) having a first sub-opening (OP-2) (see Park, Figs.6-7 as shown above); and
a second sub-layer (sML3) in the intermediate area (MA) and covering an outer surface of the first sub-layer (sML2), the second sub-layer (sML3) having a second sub-opening (OP-3) connected to the first sub-opening (OP-2) (see Park, Figs.6-7 as shown above).
Park is silent upon explicitly disclosing wherein a first sub-layer on a same layer as the second conductive layer.
However, Park teaches the first sub-layer (sML2) on the second conductive layer (CE2) as shown above. Hence, the Claims to a first sub-layer which read on the prior art except with regard to the position of the first sub-layer with respect to the position of the second conductive layer were held unpatentable because shifting the position of the first sub-layer with respect to the position of the second conductive layer would not have modified the operation of the device.
First embodiment of Park Figs.6 and 7, is silent upon explicitly disclosing wherein a slope of sidewalls of the first sub-layer and the second sub-layer, which are connected to each other, varies continuously.
However, Fig.10 of Park teaches wherein a slope of sidewalls of the first sub-layer (sML2) and the second sub-layer (sML3), which are connected to each other, varies continuously (see Park, Fig.10 as shown below).
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Hence, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to eliminate further etching processing steps of etching the first sub-layer and the second sub-layer, if the function of further etching the first sub-layer and the second sub-layer is not need or required.
Park is silent upon explicitly disclosing wherein a second active layer on the first conductive layer and comprising a second active pattern in the display area;
a second conductive layer between the first conductive layer and the second active layer;
a third conductive layer on the second conductive layer and comprising a bridge electrode electrically connecting the gate electrode and the second active pattern.
Before effective filing date of the claimed invention the disclosed second conductive layer were known to be formed between the first conductive layer and the second active layer and the third conductive layer to be formed on the second conductive layer and comprising a bridge electrode electrically connecting the gate electrode and the second active pattern in order to increase the degree of integration of the display device while reducing the power consumption of the display device.
For support see Cho, which teaches wherein a first active layer (A6) on the substrate (100) and comprising a first active pattern (A6) in the display area (see Cho, Fig.5 as shown below and ¶ [0005]);
a first conductive layer (G6) on the first active layer (A6) and comprising a gate electrode (G6) overlapping the first active pattern (A6) (see Cho, Fig.5 as shown below and ¶ [0005]);
a second active layer (A3) on the first conductive layer (G6) and comprising a second active pattern (A3) in the display area (see Cho, Fig.5 as shown below and ¶ [0005]);
a second conductive layer (G3a) between the first conductive layer (G6) and the second active layer (A3) (see Cho, Fig.5 as shown below and ¶ [0005]);
a third conductive layer (G3b) on the second conductive layer (G3a) and comprising a bridge electrode (173) electrically connecting the gate electrode (G6) and the second active pattern (A3) (see Cho, Fig.5 as shown below and ¶ [0005]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Cho to enable the second conductive layer to be formed between the first conductive layer and the second active layer and the third conductive layer to be formed on the second conductive layer and comprising a bridge electrode electrically connecting the gate electrode and the second active pattern as taught by Cho in order to increase the degree of integration of the display device while reducing the power consumption of the display device.
Regarding Claim 2: Park as modified teaches a display device as set forth in claim 1 as above. The combination of Park and Cho further teaches wherein the first sub-opening (OP1-2) and the second sub-opening (OP1-3) are interconnected to define a metal opening (see Park, Figs.6-7 as shown above), and
wherein the upper insulating layer (208) has an insulating opening (OP2) connected to the metal opening (see Park, Figs.6-7 as shown above).
The combination of Park and Cho is silent upon explicitly disclosing wherein an upper insulating layer on the third conductive layer and the second sub-layer and covering the bridge electrode.
However, practicing the combination of Park and Cho to from an upper insulating layer (Fig.6, 208/Fig.5, 116/118) on the third conductive layer (G3b) and the second sub-layer (Fig.6, sML3) and covering the bridge electrode (Fig.5, 173) necessarily results the claimed limitation of “an upper insulating layer on the third conductive layer and the second sub-layer and covering the bridge electrode” as now specified in claim 2.
Regarding Claim 3: Park as modified teaches a display device as set forth in claim 2 as above. The combination of Park and Cho further teaches wherein the metal opening (OP1-2/OP1-3) and the insulating opening (OP2) are interconnected to define a groove (see Park, Figs.6-7 as shown above), and
wherein an inner surface of the metal opening (OP1-2/OP1-3) is more recessed in a direction away from a center of the groove than an inner surface of the insulating opening (OP2) (see Park, Figs.6-7 as shown above).
Regarding Claim 4: Park as modified teaches a display device as set forth in claim 3 as above. The combination of Park and Cho further teaches wherein a lower insulating layer (207) under the second conductive layer (CE2) and the first sub-layer (sML2) (see Park, Figs.6-7 as shown above and Figs.9-11).
The combination of Park and Cho is silent upon explicitly disclosing wherein the lower insulating layer having a trench connected to the metal opening such that the groove further comprises the trench.
However, the combination of Park and Cho teaches wherein the top surface of lower insulating layer (207) exposed in the metal opening and connected to the metal opening such that the groove (G) further comprises the trench (see Park, Figs.6-7 as shown above and Figs.9-11).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the depth of the groove through routine experimentation and optimization to obtain optimal or desired device performance because the depth of the groove that extend into the lower insulating layer is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 5: Park as modified teaches a display device as set forth in claim 3 as above. The combination of Park and Cho further teaches wherein the groove is axisymmetric with respect to a central axis of the groove (see Park, Figs.6-7 as shown above).
Regarding Claim 6: Park as modified teaches a display device as set forth in claim 3 as above. The combination of Park and Cho further teaches wherein the groove is asymmetrical with respect to a central axis of the groove (see Park, Figs.6-7 as shown above).
Regarding Claim 7: Park as modified teaches a display device as set forth in claim 3 as above. The combination of Park and Cho further teaches wherein a light emitting device in the display area (DA) and comprising an anode electrode (221), a cathode electrode (223), and an intermediate layer (222) between the anode electrode (221) and the cathode electrode (223) (see Park, Figs.6-7 as shown above),
wherein the cathode electrode (223) is disconnected by the groove (see Park, Figs.6-7 as shown above).
Regarding Claim 8: Park as modified teaches a display device as set forth in claim 7 as above. The combination of Park and Cho further teaches wherein the intermediate layer (222) comprises an emission layer (222a/222b/222c), a first functional layer (222a/222b/222c) between the anode electrode (221) and the emission layer (222a/222b/222c), and a second functional layer (222a/222b/222c) between the emission layer (222a/222b/222c) and the cathode electrode (223) (see Park, Figs.6-7 as shown above and ¶ [0108]- ¶ [0112]), and
wherein at least one of the first functional layer (222a/222b/222c) and the second functional layer (222a/222b/222c) is disconnected by the groove (G) (see Park, Figs.6-7 as shown above and ¶ [0138]).
Regarding Claim 9: Park as modified teaches a display device as set forth in claim 1 as above. The combination of Park and Cho further teaches wherein the first active pattern (A6) comprises a silicon semiconductor (see Cho, Fig.5 as shown above and ¶ [0094]), and
wherein the second active pattern (A3) comprises an oxide semiconductor (see Cho, Fig.5 as shown above and ¶ [0094]).
Regarding Claim 10: Park as modified teaches a display device as set forth in claim 1 as above. The combination of Park and Cho further teaches wherein the second conductive layer (CE2) and the first sub-layer (sML2) comprise a same material (see Park, Fig.6 as shown above, ¶ [101], and ¶ [0137]), and
wherein the third conductive layer (G3b) (see Cho, Fig.5 as shown above and ¶ [0133]) and the second sub-layer (sML3) comprise a same material (See Park, Fig.6 as shown above and ¶ [0137]).
Regarding Claim 11: Park as modified teaches a display device as set forth in claim 1 as above. The combination of Park and Cho further teaches wherein a fourth conductive layer (179) on the third conductive layer (G3b) and comprising a first connection electrode (179) contacting the first active pattern (A6) and a second connection electrode (33) contacting the second active pattern (A3) (see Cho, Fig.5 as shown above); and
a fifth conductive layer (185) on the fourth conductive layer (179) and comprising a third connection electrode (185) contacting the first connection electrode (179) (see Cho, Fig.5 as shown above).
Regarding Claim 12: Park discloses a display device (see Park, Figs.6-7 as shown above and ¶ [0002]) comprising:
a substrate (100) having a transmission area (TA), a display area (DA) extending around a periphery of the transmission area (TA), and an intermediate area (MA) between the transmission area (TA) and the display area (DA) (See Park, Fig.6 as shown above);
a first active layer (Act) on the substrate (100) and comprising a first active pattern (Act) in the display area (DA) (See Park, Fig.6 as shown above);
a first conductive layer (GE) on the first active layer (Act) and comprising a gate electrode (GE) overlapping the first active pattern (Act) (See Park, Fig.6 as shown above);
a first sub-layer (sML2) in the intermediate area (MA) and on the first conductive layer (GE), the first sub-layer (sML2) having a first sub-opening (OP1-2) (See Park, Figs.6-7 as shown above); and
a second sub-layer (sML3) in the intermediate area (MA) and covering an outer surface of the first sub-layer (sML2), the second sub-layer (sML3) having a second sub-opening (OP1-3) connected to the first sub-opening (OP1-2) (See Park, Figs.6-7 as shown above).
Park is silent upon explicitly disclosing wherein a first sub-layer on a same layer as the first conductive layer.
However, Park teaches the first sub-layer (sML2) on the first conductive layer (GE) as shown above. Hence, the Claims to a first sub-layer which read on the prior art except with regard to the position of the first sub-layer with respect to the position of the first conductive layer were held unpatentable because shifting the position of the first sub-layer with respect to the position of the first conductive layer would not have modified the operation of the device.
First embodiment of Park Figs.6 and 7, is silent upon explicitly disclosing wherein a slope of sidewalls of the first sub-layer and the second sub-layer, which are connected to each other, varies continuously.
However, Fig.10 of Park teaches wherein a slope of sidewalls of the first sub-layer (sML2) and the second sub-layer (sML3), which are connected to each other, varies continuously (see Park, Fig.10 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to eliminate further etching processing steps of etching the first sub-layer and the second sub-layer, if the function of further etching the first sub-layer and the second sub-layer is not need or required.
Park is silent upon explicitly disclosing wherein a second active layer on the first conductive layer and comprising a second active pattern in the display area;
a second conductive layer between the first conductive layer and the second active layer;
a third conductive layer on the second conductive layer and comprising a bridge electrode electrically connecting the gate electrode and the second active pattern.
Before effective filing date of the claimed invention the disclosed second conductive layer were known to be formed between the first conductive layer and the second active layer and the third conductive layer to be formed on the second conductive layer and comprising a bridge electrode electrically connecting the gate electrode and the second active pattern in order to increase the degree of integration of the display device while reducing the power consumption of the display device.
For support see Cho, which teaches wherein a first active layer (A6) on the substrate (100) and comprising a first active pattern (A6) in the display area (see Cho, Fig.5 as shown above);
a first conductive layer (G6) on the first active layer (A6) and comprising a gate electrode (G6) overlapping the first active pattern (A6) (see Cho, Fig.5 as shown above);
a second active layer (A3) on the first conductive layer (G6) and comprising a second active pattern (A3) in the display area (see Cho, Fig.5 as shown above);
a second conductive layer (G3a) between the first conductive layer (G6) and the second active layer (A3) (see Cho, Fig.5 as shown above);
a third conductive layer (G3b) on the second conductive layer (G3a) and comprising a bridge electrode (173) electrically connecting the gate electrode (G6) and the second active pattern (A3) (see Cho, Fig.5 as shown above).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Cho to enable the second conductive layer to be formed between the first conductive layer and the second active layer and the third conductive layer to be formed on the second conductive layer and comprising a bridge electrode electrically connecting the gate electrode and the second active pattern as taught by Cho in order to increase the degree of integration of the display device while reducing the power consumption of the display device.
Regarding Claim 13: Park as modified teaches a display device as set forth in claim 12 as above. The combination of Park and Cho further teaches wherein the first sub-opening (OP1-2) and the second sub-opening (OP1-3) are interconnected to define a metal opening (See Park, Figs.6-7 as shown above), and
wherein the upper insulating layer (208) has an insulating opening (OP2) connected to the metal opening (OP1-2) (See Park, Figs.6-7 as shown above).
The combination of Park and Cho is silent upon explicitly disclosing wherein an upper insulating layer on the third conductive layer and the second sub-layer and covering the bridge electrode.
However, practicing the combination of Park and Cho to from upper insulating layer (Fig.6, 208/Fig.5, 116/118) on the third conductive layer (Fig.5, G3b) and the second sub-layer (Fig.6, sML3) and covering the bridge electrode (Fig.5, 173) necessarily results the claimed limitation of “an upper insulating layer on the third conductive layer and the second sub-layer and covering the bridge electrode” as now specified in claim 13.
Regarding Claim 14: Park as modified teaches a display device as set forth in claim 13 as above. The combination of Park and Cho further teaches wherein the metal opening (OP1-2/OP1-3) and the insulating opening (OP2) are interconnected to define a groove (See Park, Figs.6-7 as shown above), and
wherein an inner surface of the metal opening (OP1-2/OP1-2) is more recessed in a direction away from a center of the groove than an inner surface of the insulating opening (OP2) (See Park, Figs.6-7 as shown above).
Regarding Claim 15: Park as modified teaches a display device as set forth in claim 13 as above. The combination of Park and Cho further teaches wherein the first conductive layer (GE) and the first sub-layer (sML2) comprise a same material (See Park, Figs.6-7 as shown above and ¶ [0137]), and
wherein the third conductive layer (G3b) (see Cho, Fig.5 as shown above and ¶ [0133]) and the second sub-layer (sML3) comprise a same material (See Park, Figs.6-7 as shown above and ¶ [0137]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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