DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species II (claims 1-17, and 21-23) in the reply filed on 4/13/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21 thru 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aizawa et al. US 2005/0233517 A1 in view of Zhu et al. US 2012/0168863 A1. Aizawa discloses (see, for example, FIG. 1) a semiconductor structure 100 comprising: a bulk substrate 101; active structure 109, an antenna diode 104 merged in the bulk substrate 101; and an antenna metal structure 131/133/135/119 comprising a metal layer 131/133/135/119 disposed in a multi-layer interconnect (MLI) structure 131/133/135/119 over the bulk substrate 101, the antenna metal structure 131/133/135/119 being electrically connected to the antenna diode 104/107/109 and configured to dissipate charges generated in the MLI structure 131/133/135/119 to the bulk substrate through the antenna diode 104/107/109. In FIG. 2, Aizawa discloses the charges being discharged through the antennal metal structure 104/107/109 to the diffusion layer 107 in the bulk substrate 101. Aizawa does not disclose the active substrate isolated by an insulating layer and a heavily doped layer. However, Zhu discloses (see, for example, Fig. 2) an SOI layer 1011 being isolated by an insulating layer 1012, and a buried semiconductor layer 1013. In paragraph [0055], Zhu discloses the buried semiconductor layer 1013 may be doped as high as 1018 cm-3-1021 cm-3, which is well known as a heavily doped concentration. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the active substrate isolated by an insulating layer and a heavily doped layer in order to protect the active substrate, and suppress short channel effects.
Regarding claim 22, see, for example, FIG. 2 wherein Aizawa discloses a topmost
metallization layer 119.
Regarding claim 23, see, for example, FIG. 2 wherein Aizawa discloses plurality of metal
layers 133, 119 that are interconnected by vias 131, 135.
Allowable Subject Matter
Claims 1 thru 17 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a semiconductor structure, comprising: a silicon-on-insulator (SOI) substrate merged in the bulk substrate, the SOI substrate further comprising: a heavily doped layer comprising: a bottom portion extending horizontally; and a side portion extending circumferentially from a top end portion to a bottom end portion in a downward direction, wherein the top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom portion; an insulating layer disposed on and surrounded by the heavily doped layer; and an active substrate disposed on and surrounded by the insulating layer, where the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate.
Regarding claims 11-17, the references of record, either singularly or in combination, do not teach or suggest at least a semiconductor structure, comprising: a silicon-on-insulator (SOI) substrate merged in the bulk substrate, the SOI substrate further comprising: a heavily doped layer comprising: a bottom portion extending horizontally; and a side portion extending circumferentially from a top end portion to a bottom end portion in a downward direction, wherein the top end portion is connected to the top surface of the bulk substrate, and the bottom end portion is connected to the bottom portion; an insulating layer disposed on and surrounded by the heavily doped layer; and an active substrate disposed on and surrounded by the insulating layer, where the active substrate is isolated by the insulating layer and the heavily doped layer and has a top surface coplanar with the top surface of the bulk substrate.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Eugene Lee
April 22, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
Prosecution Insights