DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Applicant’s second solder resist openings (Fig. 10B) are spaced apart from the pad.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 12-16,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu).
Regarding claim 1, Yu discloses a semiconductor package, comprising: an interposer; (Fig. 4, 201; ¶74) at least one semiconductor integrated circuit (IC) die (Fig. 4, 205; ¶74) mounted over a first surface (top) of the interposer; a package substrate (Fig. 4, 101; ¶70) comprising an outer coating layer comprising a solder resist layer (Fig. 4, 102/103; ¶70) on a front side surface of the package substrate, the solder resist layer having a plurality of first openings (Fig. 4, 102-1 or 102-2; ¶60) and second openings (Fig. 4, 102-1 or 102-2; ¶60) each extending through the solder resist layer and exposing a bonding pad (Fig. 4,not labeled location of 111 & 112; ¶57) of an array of bonding pads, and a first width (Fig. 4, D1 ¶60) dimension of the first openings (Fig. 4, 102-1; ¶60) through the solder resist layer in a first region of the package substrate is less than a second width (Fig. 4, D2; ¶60) dimension of the second openings (Fig. 4, 102-2; ¶60) through the solder resist layer in a second region of the package substrate; and a plurality of bonding material portions (Fig. 4, 111/112; ¶57) located between respective bonding pads exposed through the first openings and the second openings in the solder resist layer and corresponding bonding structures (Fig. 4, 204; ¶74) located on a second surface (bottom) of the interposer to mechanically and electrically couple the package substrate and the interposer, wherein the second width dimension of the second openings through the solder resist layer is greater than a width dimension of at least one of the bonding pads exposed through a second opening.
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Yu discloses an alternative configuration where the second width dimension of the solder resist opening (Fig. 9, 106-2; ¶90) is greater than a width dimension of at least one of the bonding pads exposed through a second opening. (Fig. 9, 112; ¶90)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to expand the width of the solder resist opening to provide a bump with more surface area. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 2, Yu discloses the semiconductor package of claim 1, wherein the plurality of bonding material (Fig. 4, 111/112; ¶57) portions comprise solder material portions.
Regarding claim 13, Yu discloses a package substrate, comprising: an array of bonding pads (Fig. 4,not labeled location of 111 & 112; ¶57); and an outer coating layer (Fig. 4, 102/103; ¶70) on a first side surface (top) of the package substrate, wherein the outer coating layer comprises a plurality of first openings (Fig. 4, 102-1 or 102-2; ¶60) and second openings (Fig. 4, 102-1 or 102-2; ¶60) through the outer coating layer, each of the plurality of first openings through the outer coating layer having a first width dimension (Fig. 4, D1 ¶60) and exposing at least a portion of a bonding pad of the array of bonding pads, each of the plurality of second openings through the outer coating layer having a second width dimension (Fig. 4, D2 ¶60) and exposing at least a portion of a bonding pad of the array of bonding pads, wherein bonding pads of the array of bonding pads are exposed through the first openings in a first region of the package substrate (Fig. 4, 101; ¶70), the bonding pads exposed through the first openings in the first region having a bonding pad width dimension that is greater than the first width dimension of the openings in the first region and bonding pads (Fig. 4,not labeled location of 111/112; ¶57) of the array of bonding pads are exposed through the second openings in a second region of the package substrate, the bonding pads exposed through the second openings having a bonding pad width dimension that is less than the second width dimension of the second openings in the second region.
Yu discloses an alternative configuration where the second width dimension of the solder resist opening (Fig. 9, 106-2; ¶90) is greater than a width dimension of at least one of the bonding pads exposed through a second opening. (Fig. 9, 112; ¶90)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to expand the width of the solder resist opening to provide a bump with more surface area. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 14, Yu discloses the package substrate of claim 13, wherein the second region (Fig. 4, D2 ¶60) of the package substrate (Fig. 4, 101; ¶70) is located in a central portion of the array of bonding pads. (Fig. 4,not labeled location of 111 & 112; ¶57)
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Regarding claim 15, Yu discloses the package substrate of claim 13, wherein the second region (Fig. 4,not labeled location of 112; ¶57) of the package substrate (Fig. 4, 101; ¶70) is located along a peripheral edge of the array of bonding pads. (Fig. 4,not labeled location of 111 & 112; ¶57)
Applicant’s figures and associated text appear to be choosing points on the pad array and labeling them second regions rather than making structural changes.
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Regarding claim 16, Yu discloses the package substrate of claim 13, wherein the second region (Fig. 4,not labeled location of 112; ¶57) of the package substrate (Fig. 4, 101; ¶70) is located in a central portion of the array of bonding pads, and the package substrate further comprises a pair of additional second regions, (Fig. 4,not labeled location of 112; ¶57) wherein the bonding pad width dimension of the bonding pads is less than the second width dimension of the second openings through the outer coating layer in each of the pair of additional second regions, and respective ones of the pair of additional second regions are located along opposite peripheral edges of the array of bonding pads located (applicant’s hd2 direction) along opposite peripheral edges of the array of bonding pads.
As can be seen from the figures 6 and 8 of Yu (below) the second region pads and associated openings cross a central portion to four opposite peripheral edges of the substrate.
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Yu discloses an alternative configuration where the second width dimension of the solder resist opening (Fig. 9, 106-2; ¶90) is greater than a width dimension of at least one of the bonding pads exposed through a second opening. (Fig. 9, 112; ¶90)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to expand the width of the solder resist opening to provide a bump with more surface area. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
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Regarding claim 19, Yu discloses a method of fabricating a semiconductor package, comprising: aligning an interposer (Fig. 4, 201; ¶74) having at least one semiconductor integrated circuit (IC) die (Fig. 4, 205; ¶74) on a front side surface (TOP) of the interposer over a front side surface (TOP) of a package substrate (Fig. 4, 101; ¶70) , wherein the package substrate comprises an outer coating layer (Fig. 4, 102/103; ¶70) on the front side surface of the package substrate, the outer coating layer comprising a solder resist layer having a plurality of first openings (Fig. 4, 102-1 or 102-2; ¶60) and a plurality of second openings (Fig. 4, 102-1 or 102-2; ¶60) extending through the solder resist layer to expose an array of bonding pads (Fig. 4,not labeled location of 111 & 112; ¶57), where a first width (Fig. 4, D1 ¶60) dimension of the first openings through the solder resist layer in a first region of the package substrate is less than a second width dimension (Fig. 4, D2 ¶60) of the second openings through the solder resist layer in a second region of the package substrate; and bonding a rear side surface of the interposer to the front side surface of the package substrate such that a plurality of bonding material portions (Fig. 4, 111/112; ¶57) are located between the bonding pads exposed through the plurality of first openings and the plurality of second openings in the solder resist layer on the front side surface of the package substrate and corresponding bonding structures (Fig. 4, 204; ¶74) located on the rear side surface of the interposer to mechanically and electrically couple the package substrate and the interposer, wherein the second width dimension of the second openings through the solder resist layer is greater than a width dimension of at least one of the bonding pads exposed through a second opening..
Yu discloses an alternative configuration where the second width dimension of the solder resist opening (Fig. 9, 106-2; ¶90) is greater than a width dimension of at least one of the bonding pads exposed through a second opening. (Fig. 9, 112; ¶90)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to expand the width of the solder resist opening to provide a bump with more surface area. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Claim(s) 3-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu) in view of Wang et al. (US 20220406752 A1; Wang).
Regarding claim 3, Yu discloses the semiconductor package of claim 1, but is silent on wherein the at least one semiconductor IC die comprises a plurality of system-on-chip (SoC) dies located in a central portion of interposer and a plurality of memory dies laterally surrounding the SoC dies.
Yu does not discloses what type of chips 205 are but discloses the technology is compatible with a SOC/memory configuration. (¶4)
Wang discloses forming a package comprising a semiconductor die with a plurality of system-on-chip (SoC) dies (Fig. 12, 100; ¶71,77) located in a central portion of interposer and a plurality of memory dies (Fig. 12, 200; ¶71,77) laterally surrounding the SoC dies.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 4, Yu in view of Wang discloses the semiconductor package of claim 3, wherein the second region (Fig. 4, D2; ¶60) of the package substrate (Fig. 4, 101; ¶70) underlies a central portion of the interposer. (Fig. 4, 201; ¶74) but is silent on and is circumscribed by a circle having a center underlying a geometric center of the interposer and a radius that is less than or equal to 70% of a length or width dimension of the interposer.
Applicant simply draws a circle (Fig. 13B) around the central region that is not actually a part of the structure. The limitation does not further limit the claimed structure.
One of ordinary skill in the art can draw a circle around the package.
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Before the effective filing date of the invention it would have been obvious to one having ordinary skill to make a circle around the package for determining the desired case size of the completed device.
Regarding claim 6, Yu in view of Wang discloses the semiconductor package of claim 4, wherein the package substrate (Fig. 4, 101; ¶70 Yu) comprises a plurality of second regions, including a second region underlying the plurality of SoC dies (Fig. 12, 100; ¶71,77 Wang) located in the central portion of the interposer and at least one second region underlying the plurality of memory dies. (Fig. 12, 200; ¶71,77 Wang)
Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 7, Yu in view of Wang discloses the semiconductor package of claim 3, wherein the package substrate (Fig. 4, 101; ¶70 Yu) comprises at least one second region underlying a memory die. (Fig. 12, 200; ¶71,77 Wang)
Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions underlying the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 8, Yu in view of Wang discloses the semiconductor package of claim 7, wherein the package substrate (Fig. 8, 101; ¶ 70 Yu) comprises second regions (perimeter) extending along opposite peripheral edges of the array of bonding pads (Fig. 8,not labeled location of 111 & 112; ¶57 Yu) and underlying memory dies. (Fig. 12, 200; ¶71,77 Wang)
Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions underlying the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 9, Yu in view of Wang discloses the semiconductor package of claim 8, wherein each of the second regions (perimeter) extending along opposite peripheral edges of the array of bonding pads (Fig. 8,not labeled location of 111 & 112; ¶57 Yu) extend along the entire peripheral edges of the array of bonding pads (clear from drawings).
The substrate has to be present in areas comprising bond pads. Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions underlying the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 10, Yu in view of Wang discloses the semiconductor package of claim 8, wherein the second regions (Fig. 8, perimeter of 101; ¶ 70 Yu) extending along opposite peripheral edges (perimeter) of the array of bonding pads extend over a portion of the peripheral edges of the array of bonding pads and are located in opposite corners of the array of bonding pads.
Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions underlying the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu).
Regarding claim 12, Yu in view of Wang discloses the semiconductor package of claim 1, wherein the interposer (Fig. 4,201; ¶76 epoxy resin) comprises an organic interposer having at least four redistribution layers (RDLs). (Fig. 12,121 one or more; ¶36 Wang)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to provide four redistribution layers to provide more flexibility in wiring patterns and to provide more mechanical support to the package.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu) in view of Wang et al. (US 20220406752 A1; Wang) and further in view of Hong et al. (US 20200060025 a1; Hong).
Regarding claim 11, Yu in view of Wang discloses the semiconductor package of claim 2, but is silent on wherein the bonding pads in the first region of the package substrate comprise solder mask defined (SMD) bonding pads, and the bonding pads in the second region of the package substrate comprise non-solder mask defined (NSMD) bonding pads.
Yu discloses the pads of claim 2 but does not disclose how they are configured. Hong discloses using SMD and NSMD in a package substrate structure. (¶55)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use both SMD and NSMD pad configurations for the benefit of reducing processing complexity, and increases production efficiency of the package structure.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu).
Regarding claim 20, Yu discloses the method of claim 19, wherein bonding the rear side surface of the interposer (Fig. 4, 201; ¶74) to the front side surface of the package substrate (Fig. 4, 101; ¶70) comprises performing a reflow (¶74) process but is silent on at a temperature greater than 150°C.
However, it is known in the art that solder reflow takes place at or above 180 °C . The preheating face typically has a temperature up to 150°C .
Therefore, before the effective filing date it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the reflow temperature above 150 °C through routine experimentation and optimization to obtain optimal or desired solder bonding because the reflow temperature is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Allowable Subject Matter
Claim 17,18, 21 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 17, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein each of the pair of addition second region extend along the entire peripheral edges of the array of bonding pads.”, as recited in Claim 17, with the remaining features.
Regarding claim 18, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " the pair of additional second regions extend over a portion of the peripheral edges of the array of bonding pads and are located in opposite corners of the array of bonding pads..”, as recited in Claim 18, with the remaining features.
Regarding claim 21, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein a bonding material portion of the plurality of bonding material portions located in a second opening contacts a side surface of a bonding pad exposed through the second opening.”, as recited in Claim 21, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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