DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16-18 are objected to because of the following informalities: claim 16 recites, “a second region of the package substrate is located in a central portion of the array of bonding pads, and a pair of second regions of the package substrate are located along opposite peripheral edges of the array of bonding pads.” Is applicant claiming the second region has second regions, or a new second region? A new region should be a “third region” Which second regions are being referred to in claims 17-18? The claim language is unclear. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 ,2, 13-19 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yu et al. (US-20140091463-A1; Yu).
Regarding claim 1, Yu discloses a semiconductor package, comprising: an interposer; (Fig. 4, 201; ¶74) at least one semiconductor integrated circuit (IC) die (Fig. 4, 205; ¶74) mounted over a first surface (top) of the interposer; a package substrate (Fig. 4, 101; ¶70) comprising an outer coating layer (Fig. 4, 102/103; ¶70) on a front side surface of the package substrate, the outer coating layer having a plurality of first openings (Fig. 4, 102-1 or 102-2; ¶60) and second openings (Fig. 4, 102-1 or 102-2; ¶60) each exposing a bonding pad (Fig. 4,not labeled location of 111 & 112; ¶57) of an array of bonding pads, and a first width (Fig. 4, D1 ¶60) dimension of the first openings (Fig. 4, 102-1; ¶60) through the outer coating layer in a first region of the package substrate is less than a second width (Fig. 4, D2; ¶60) dimension of the second openings (Fig. 4, 102-2; ¶60) through the outer coating layer in a second region of the package substrate; and a plurality of bonding material portions (Fig. 4, 111/112; ¶57) located between respective bonding pads exposed through the first openings and the second openings in the outer coating layer and corresponding bonding structures (Fig. 4, 204; ¶74) located on a second surface (bottom) of the interposer.
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Regarding claim 2, Yu discloses the semiconductor package of claim 1, wherein the outer coating layer (Fig. 4, 102/103; ¶70) comprises a solder resist layer, and the plurality of bonding material (Fig. 4, 111/112; ¶57) portions comprise solder material portions.
Regarding claim 13, Yu discloses a semiconductor package, comprising: an array of bonding pads (Fig. 4,not labeled location of 111 & 112; ¶57), each of the bonding pads having a bonding pad width dimension; and an outer coating layer (Fig. 4, 102/103; ¶70) on a first side surface (top) of the semiconductor package, wherein the outer coating layer comprises a plurality of first openings (Fig. 4, 102-1 or 102-2; ¶60) and second openings (Fig. 4, 102-1 or 102-2; ¶60) through the outer coating layer, each of the plurality of first openings through the outer coating layer having a first width dimension (Fig. 4, D1 ¶60) and exposing at least a portion of a bonding pad of the array of bonding pads, each of the plurality of second openings through the outer coating layer having a second width dimension (Fig. 4, D2 ¶60) and exposing at least a portion of a bonding pad of the array of bonding pads, wherein the bonding pad width (Fig. 4, D2 ¶60) dimension of the bonding pads (Fig. 4,not labeled location of 112; ¶57) is greater than the first width dimension (Fig. 4, D1 ¶60) of the first openings (Fig. 4, 102-1; ¶60) through the outer coating layer in a first region of the package substrate (Fig. 4, 101; ¶70), and the bonding pad width (Fig. 4, D1 ¶60) dimension of the bonding pads (Fig. 4,not labeled location of 111/112; ¶57) is less than the second width dimension (Fig. 4, D2 ¶60) of the second openings (Fig. 4, 102-2; ¶60) through the outer coating layer in a second region of the package substrate.
Regarding claim 14, Yu discloses the package substrate of claim 13, wherein the second region (Fig. 4, D2 ¶60) of the package substrate (Fig. 4, 101; ¶70) is located in a central portion of the array of bonding pads. (Fig. 4,not labeled location of 111 & 112; ¶57)
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Regarding claim 15, Yu discloses the package substrate of claim 13, wherein the second region (Fig. 4,not labeled location of 112; ¶57) of the package substrate (Fig. 4, 101; ¶70) is located along a peripheral edge of the array of bonding pads. (Fig. 4,not labeled location of 111 & 112; ¶57)
Applicant’s figures and associated text appear to be choosing points on the pad array and labeling them second regions rather than making structural changes.
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Regarding claim 16, Yu discloses the package substrate of claim 13, wherein the package substrate (Fig. 4, 101; ¶70) comprises a plurality of second regions, wherein the width dimension of the bonding pads (Fig. 4,not labeled location of 111/112; ¶57) is less than the width dimension (taper of 103 larger than pad width) of the openings through the outer coating layer (Fig. 4, 102/103; ¶70) in each of the second regions of the package substrate, a second region (applicants hd1 direction) of the package substrate is located in a central portion of the array of bonding pads, and a pair of second regions (Perimeter) of the package substrate are located (applicant’s hd2 direction) along opposite peripheral edges of the array of bonding pads.
Applicant’s figures and associated text appear to be choosing points on the pad array and labeling them second regions rather than making structural changes.
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Regarding claim 17, Yu discloses the package substrate of claim 16, wherein each of the second regions (applicant’s hd2 direction) extending along opposite peripheral (perimeter) edges of the array of bonding pads (Fig. 4,not labeled location of 111/112; ¶57) extend along the entire peripheral edges (applicants hd1 direction) of the array of bonding pads.
Applicant’s figures and associated text appear to be choosing points on the pad array and labeling them second regions rather than making structural changes.
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Regarding claim 18, Yu discloses the package substrate of claim 16, wherein each of the second regions extending along opposite peripheral edges of the array of bonding pads (Fig. 4,not labeled location of 111/112; ¶57) extend over a portion of the peripheral edges of the array of bonding pads and are located in opposite corners of the array of bonding pads.
Applicant’s figures and associated text appear to be choosing points on the pad array and labeling them second regions rather than making structural changes.
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Regarding claim 19, Yu discloses a method of fabricating a semiconductor package, comprising: aligning an interposer (Fig. 4, 201; ¶74) having at least one semiconductor integrated circuit (IC) die (Fig. 4, 205; ¶74) on a front side surface (TOP) of the interposer over a front side surface (TOP) of a package substrate (Fig. 4, 101; ¶70) , wherein the package substrate comprises an outer coating layer (Fig. 4, 102/103; ¶70) on the front side surface of the package substrate and having a plurality of first openings (Fig. 4, 102-1 or 102-2; ¶60) and a plurality of second openings (Fig. 4, 102-1 or 102-2; ¶60) extending therethrough to expose an array of bonding pads (Fig. 4,not labeled location of 111 & 112; ¶57), where a first width (Fig. 4, D1 ¶60) dimension of the first openings through the outer coating layer in a first region of the package substrate is less than a second width dimension (Fig. 4, D2 ¶60) of the second openings through the outer coating layer in a second region of the package substrate; and bonding a rear side surface of the interposer to the front side surface of the package substrate such that a plurality of bonding material portions (Fig. 4, 111/112; ¶57) are located between the bonding pads exposed through the plurality of first openings and the plurality of second in the outer coating layer on the front side surface of the package substrate and corresponding bonding structures (Fig. 4, 204; ¶74) located on the rear side surface of the interposer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu) in view of Wang et al. (US 20220406752 A1; Wang).
Regarding claim 3, Yu discloses the semiconductor package of claim 1, but is silent on wherein the at least one semiconductor IC die comprises a plurality of system-on-chip (SoC) dies located in a central portion of interposer and a plurality of memory dies laterally surrounding the SoC dies.
Yu does not discloses what type of chips 205 are but discloses the technology is compatible with a SOC/memory configuration. (¶4)
Wang discloses forming a package comprising a semiconductor die with a plurality of system-on-chip (SoC) dies (Fig. 12, 100; ¶71,77) located in a central portion of interposer and a plurality of memory dies (Fig. 12, 200; ¶71,77) laterally surrounding the SoC dies.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 4, Yu in view of Wang discloses the semiconductor package of claim 3, wherein the second region (Fig. 4, D2; ¶60) of the package substrate (Fig. 4, 101; ¶70) underlies a central portion of the interposer. (Fig. 4, 201; ¶74)
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Regarding claim 5, Yu in view of Wang discloses the semiconductor package of claim 4, wherein the second region of the package substrate is circumscribed by a circle having a center underlying a geometric center of the interposer and a radius that is ≤70% of a length or width dimension of the interposer.
One of ordinary skill in the art can draw a circle around the package.
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Before the effective filing date of the invention it would have been obvious to one having ordinary skill to make a circle around the package for determining the desired case size of the completed device.
Regarding claim 6, Yu in view of Wang discloses the semiconductor package of claim 4, wherein the package substrate (Fig. 4, 101; ¶70 Yu) comprises a plurality of second regions, including a second region underlying the plurality of SoC dies (Fig. 12, 100; ¶71,77 Wang) located in a central portion of the interposer and at least one second region underlying the plurality of memory dies. (Fig. 12, 200; ¶71,77 Wang)
Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 7, Yu in view of Wang discloses the semiconductor package of claim 3, wherein the package substrate (Fig. 4, 101; ¶70 Yu) comprises at least one second region underlying a memory die. (Fig. 12, 200; ¶71,77 Wang)
Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions underlying the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 8, Yu in view of Wang discloses the semiconductor package of claim 7, wherein the package substrate (Fig. 8, 101; ¶ 70 Yu) comprises second regions (perimeter) extending along opposite peripheral edges of the array of bonding pads (Fig. 8,not labeled location of 111 & 112; ¶57 Yu) and underlying memory dies. (Fig. 12, 200; ¶71,77 Wang)
Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions underlying the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 9, Yu in view of Wang discloses the semiconductor package of claim 8, wherein each of the second regions (perimeter) extending along opposite peripheral edges of the array of bonding pads (Fig. 8,not labeled location of 111 & 112; ¶57 Yu) extend along the entire peripheral edges of the array of bonding pads (clear from drawings).
The substrate has to be present in areas comprising bond pads. Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions underlying the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Regarding claim 10, Yu in view of Wang discloses the semiconductor package of claim 8, wherein the second regions (Fig. 8, perimeter of 101; ¶ 70 Yu) extending along opposite peripheral edges (perimeter) of the array of bonding pads extend over a portion of the peripheral edges of the array of bonding pads and are located in opposite corners of the array of bonding pads.
Yu’s substrate is the same length as the interposer. Therefore it comprises the claimed second regions underlying the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to form the die comprising the claimed SOC an HBM configuration for making a high density AI device.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu).
Regarding claim 12, Yu in view of Wang discloses the semiconductor package of claim 1, wherein the interposer (Fig. 4,201; ¶76 epoxy resin) comprises an organic interposer having at least four redistribution layers (RDLs). (Fig. 12,121 one or more; ¶36 Wang)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to provide four redistribution layers to provide more flexibility in wiring patterns and to provide more mechanical support to the package.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu) in view of Wang et al. (US 20220406752 A1; Wang) and further in view of Hong et al. (US 20200060025 a1; Hong).
Regarding claim 11, Yu in view of Wang discloses the semiconductor package of claim 2, but is silent on wherein the bonding pads in the first region of the package substrate comprise solder mask defined (SMD) bonding pads, and the bonding pads in the second region of the package substrate comprise non-solder mask defined (NSMD) bonding pads.
Yu discloses the pads of claim 2 but does not disclose how they are configured. Hong discloses using SMD and NSMD in a package substrate structure. (¶55)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use both SMD and NSMD pad configurations for the benefit of reducing processing complexity, and increases production efficiency of the package structure.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US-20140091463-A1; Yu).
Regarding claim 20, Yu discloses the method of claim 19, wherein bonding the rear side surface of the interposer (Fig. 4, 201; ¶74) to the front side surface of the package substrate (Fig. 4, 101; ¶70) comprises performing a reflow (¶74) process but is silent on at a temperature greater than 150°C.
However, it is known in the art that solder reflow takes place at or above 180 °C . The preheating face typically has a temperature up to 150°C .
Therefore, before the effective filing date it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the reflow temperature above 150 °C through routine experimentation and optimization to obtain optimal or desired solder bonding because the reflow temperature is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899