DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention I and Species (a), (claims 1-5, 9 and 21), in the
reply filed on 03/02/2026 by phone with attorney Joshua L. Pritchett, Reg. No. 69,004 is acknowledged. Claim 20 is canceled. Claim 21 is new. Claims 1-19 and 21 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as
being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, it recites the limitation “…a through-silicon via structure, wherein the first array of vertical assemblies is on a first side of the via structure”. The limitation has an antecedent issue of “the via structure”.
In addition, the limitation “a through-silicon via structure, wherein the first array of vertical assemblies is on a first side of the via structure”. It is not clear how the element “through-silicon via structure” is a through-silicon via. Therefore, it is indefinite. For the examination purpose and according Fig. 13D and paragraph [0035,00146-147], the limitation “…a through-silicon via structure, wherein the first array of vertical assemblies is on a first side of the via structure” is interpreted as “a via structure, wherein the first array of vertical assemblies is on a first side of the via structure”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim(s) 9 is/are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Frougier et al.
(US 20230178620 A1, hereinafter Frougier).
Re: Independent Claim 9, Frougier discloses a semiconductor device comprising:
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Frougier’s Figure 30-Annotated.
a first array of upper channel structures (130-Up-1-channel a plurality in [0063], Figs. 2,30);
a first conductive pattern (1910 contacts for the upper FETs in [0099], Figs. 19,30) over and electrically connected to at least one upper channel structure (130-Up-1-channel Figs. 2,30) of the first array of upper channel structures (130-Up-1-channel a plurality Figs. 2,30);
a first array of intermediate structures (120-inter-1 a plurality in [0063], Figs. 2,30) below the first array of upper channel structures (130-Up-1-channel a plurality Figs. 2,30);
a first array of lower channel structures (130-low-1-channel a plurality in [0063], Figs. 2,30) below the first array of first intermediate structures (120-inter-1 a plurality in [0063], Figs. 2,30);
a second conductive pattern (2920 gate contacts in [0099], Figs. 29,30) under and electrically connected to at least one lower channel structure (130-low-1-channel, Figs. 2,30) of the first array of lower channel structures (130-low-1-channel a plurality, Figs. 2,30);
wherein the first array of upper channel structures (130-Up-1-channel a plurality Figs. 2,30), the first array of intermediate structures (120-inter-1 a plurality in [0063], Figs. 2,30), and the first array of lower channel structures (130-low-1-channel a plurality in [0063], Figs. 2,30) are arranged to form a first array of vertical assemblies (first vertical, a plurality of vertical assemblies in [0003], Fig. 30-Annotated) and
a first vertical assembly (first vertical, [0003], Fig. 30-Annotated) of the first array of vertical assemblies (first vertical, a plurality of vertical assemblies, Fig. 30-Annotated) is configured to electrically connect (Fig. 30-Annotated) the first conductive pattern (1910) and the second conductive pattern (2920); and
a via structure (via-1910 one of 1910 contacts connected to the upper FETs in [0099], Figs. 19,30-Annotated, Frougier), wherein the first array of vertical assemblies (first vertical, a plurality of vertical assemblies, Fig. 30-Annotated) is on (Fig. 30-Annotated) a first side of the via structure (via-1910).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 21 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Frougier et al. (US 20230178620 A1, hereinafter Frougier) in view of Yim et al. (US 20220375935 A1, hereinafter Yim).
Re: Independent Claim 1, Frougier discloses a semiconductor device (Fig. 30) comprising:
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Frougier’s Figure 30-Annotated.
a substrate (substrate stacks of alternating nanosheet layers of differing semiconductor materials are epitaxially grown upon an underlying substrate, Fig. 30-Annotated) having a top surface (top surface of an underlying substrate, Fig. 30-Annotated) and a bottom surface (bottom surface of an underlying substrate, Fig. 30-Annotated);
a frontside conductive pattern (1910 contacts for the upper FETs in [0099], Figs. 19,30) on the top surface (top surface, Fig. 30-Annotated);
a backside conductive pattern (2920 gate contacts in [0099], Figs. 29,30) on the bottom surface (bottom surface, Fig. 30-Annotated);
a first upper channel structure (130-Up-1-channel in [0063], Figs. 2,30) in the substrate (Fig. 30-Annotated);
a first intermediate structure (120-inter-1 in [0063], Figs. 2,30) in the substrate (Fig. 30-Annotated) below the first upper channel structure (130-Up-1-channel in [0063], Figs. 2,30), and
a first lower channel structure (130-low-1-channel in [0063], Figs. 2,30) in the substrate (Fig. 30-Annotated) below the first intermediate structure (120-inter-1),
wherein the first upper channel structure (130-Up-1-channel, Figs. 2,30), the first intermediate structure (120-inter-1, Figs. 2,30), and the first lower channel structure (130-low-1-channel, Figs. 2,30) comprise a first vertical assembly (first vertical, [0003], Fig. 30-Annotated) and establish an electrical connection (Fig. 30-Annotated) between the frontside conductive pattern (1910) and the backside conductive pattern (2920).
Frougier does not expressly disclose wherein the first intermediate structure comprises a conductive material.
However, in the same semiconductor device field of endeavor, Yim discloses wherein the first intermediate structure (52 etch barrier layer provided between the lower transistor and the upper transistor in [0043], Fig.3) comprises a conductive material (etch barrier layer 52 may be an electrical conductor in [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yim’s feature wherein the first intermediate structure comprises a conductive material to Frougier’s device to protect the lower transistors from etchants that are used while the upper transistors are formed ([0043], Yim).
Re: Claim 2, Frougier modified by Yim discloses the semiconductor device according to claim 1, wherein: the first upper channel structure (130-Up-1-channel, Figs. 2,30, Frougier) comprises an N-type material (nFET in [0003], Frougier); and the first lower channel structure (130-Up-1-channel, Figs. 2,30, Frougier) comprises a low resistance material (130 made of silicon in [0056], Frougier).
Re: Claim 3, Frougier modified by Yim discloses the semiconductor device according to claim 2, further comprising: a second upper channel structure (130-Up-2-channel in [0063], Figs. 2,30-Annotated, Frougier) in the substrate (Figs. 30-Annotated, Frougier); a second intermediate structure (120-inter-2 in [0063], Figs. 2,30-Annotated, Frougier) in the substrate (Figs. 30-Annotated, Frougier) below the second upper channel structure (130-Up-2-channel, Frougier); a second lower channel structure (130-low-2-channel in [0063], Figs. 2,30-Annotated, Frougier) in the substrate (Figs. 30-Annotated, Frougier) below the second intermediate structure (120-inter-2, Frougier) ; a signal source (signal-1910 one of 1910 contacts connected to the upper FETs in [0099], Figs. 19,30-Annotated, Frougier) connected to the second upper channel structure (130-Up-2-channel, Frougier); wherein the second upper channel structure (130-Up-2-channel, Frougier) comprises a first transistor (in [0053], Fig. 30-Annotated, Frougier) and the second lower channel structure (130-low-2-channel, Frougier) comprises a second transistor (in [0053], Fig. 30-Annotated, Frougier) and the second upper channel structure (130-Up-2-channel, Frougier), the second intermediate structure (120-inter-2, Frougier), and the second lower channel structure (130-low-2-channel, Frougier) comprises a second vertical assembly (second vertical, [0003], Fig. 30-Annotated, Frougier); and a gate electrode (1610-gate in [0085], Figs. 15,30-Annotated, Frougier) between the first vertical assembly (first vertical, Frougier) and the second vertical assembly (second vertical, Frougier).
Re: Claim 4, Frougier modified by Yim discloses the semiconductor device according to claim 3, wherein: the second upper channel structure (130-Up-2-channel, Frougier) comprises an N-type material (130-Up-2-channel made of N type material in [0003], Frougier); the second intermediate structure (120-inter-2, Frougier) comprises an insulating material (in [0053], Frougier); and the second lower channel structure (130-low-2-channel, Frougier) comprises a P-type material (in [0003], Frougier).
Re: Claim 5, Frougier modified by Yim discloses the semiconductor device according to claim 3, wherein: the second lower channel structure (130-low-2-channel, Frougier) comprises a low resistance material (made of silicon in [0056], Frougier).
Frougier modified by Yim does not expressly disclose wherein: the second upper channel structure (130-Up-2-channel, Frougier) comprises an N-type material; the second intermediate structure comprises conductive material.
However, one of ordinary skill in the art looking to form a complementary FET, would have been able to obvious to try to choose one of two possible options, the first one is forming a FET transistor comprising P-type material, or the second one is forming a FET transistor comprising N-type material, this last option may be selected according to the electrical properties required by the device (see MPEP 2143.1 (e)).
Frougier modified by Yim does not expressly disclose wherein: the second intermediate structure comprises conductive material.
However, in the same semiconductor device field of endeavor, Yim discloses wherein the first intermediate structure (52 etch barrier layer provided between the lower transistor and the upper transistor in [0043], Fig.3) comprises a conductive material (etch barrier layer 52 may be an electrical conductor in [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yim’s feature wherein the second intermediate structure comprises conductive material to Frougier’s device to protect the lower transistors from etchants that are used while the upper transistors are formed ([0043], Yim).
Re: Independent Claim 21, Frougier discloses a semiconductor device (Fig. 30) comprising:
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Frougier’s Figure 30-Annotated.
a substrate (substrate stacks of alternating nanosheet layers of differing semiconductor materials are epitaxially grown upon an underlying substrate, Fig. 30-Annotated) having a first surface (top surface of an underlying substrate, Fig. 30-Annotated) and a second surface (bottom surface of an underlying substrate, Fig. 30-Annotated) opposite the first surface (top surface, Fig. 30-Annotated);
a first conductive pattern (1910 contacts for the upper FETs in [0099], Figs. 19,30) on the first surface (top surface, Fig. 30-Annotated);
a second conductive pattern (2920 gate contacts in [0099], Figs. 29,30) on the second surface (bottom surface, Fig. 30-Annotated), wherein the second surface (bottom surface, Fig. 30-Annotated) is between the first surface (top surface, Fig. 30-Annotated) and the second conductive pattern (2920) in a first direction (Y direction);
a first channel structure (130-Up-1-channel in [0063], Figs. 2,30) in the substrate (Fig. 30-Annotated), wherein the first channel structure (130-Up-1-channel) is electrically connected (Fig. 30-Annotated) to the first conductive pattern (1910);
a second channel structure (130-low-1-channel in [0063], Figs. 2,30) in the substrate (Fig. 30-Annotated), wherein the second channel structure (130-low-1-channel) is electrically connected (Fig. 30-Annotated) to the second conductive pattern (2920);
an intermediate structure (intermediate comprising dielectric layers and portions 1220 (showed as 1120 in Fig. 12) between upper and lower channels in [0021,0053,0063,0082], Figs. 2,30) in the substrate (Fig. 30-Annotated) between the first channel structure (130-Up-1-channel) and the second channel structure (130-low-1-channel), wherein the first intermediate structure (intermediate) comprises and an isolation structure (in [0021,0053,0063,0082], Figs. 12,30); and
a first gate structure (1610-gate-1 in [0085], Figs. 15,30-Annotated, Frougier) over the first channel structure (130-Up-1-channel); a second gate structure (1610-gate-2 in [0085], Figs. 15,30-Annotated, Frougier) over the second channel structure (130-low-1-channel), wherein the isolation structure (1220 in [0021,0053,0063,0082], Figs. 12,30) is between the first gate structure (1610-gate-1) and the second gate structure (1610-gate-2) in the first direction (Y direction).
Frougier does not expressly disclose wherein the intermediate structure comprises a conductive material.
However, in the same semiconductor device field of endeavor, Yim discloses wherein the intermediate structure (52 etch barrier layer provided between the lower transistor and the upper transistor in [0043], Fig.3) comprises a conductive material (etch barrier layer 52 may be an electrical conductor in [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yim’s feature wherein the intermediate structure comprises a conductive material to Frougier’s device to protect the lower transistors from etchants that are used while the upper transistors are formed ([0043], Yim).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Motoyama et al. (US 20240186325 A1) teaches “STACKED TRANSISTORS HAVING BOTTOM CONTACT WITH LARGER SILICIDE”. This document is related to a stacked transistor structure including a top source drain region above a bottom source drain region, where a width of the bottom source drain region is greater than a width of the top source drain region, a bottom contact structure directly above and in electrical contact with the bottom source drain region, a metal silicide between the bottom source drain region and the bottom contact structure, the metal silicide having a width larger than a width of the bottom contact structure; a replacement spacer surrounding the bottom contact structure; and a top gate spacer separating the replacement spacer from a gate conductor.
Xie et al. (US 20240203990 A1) teaches “STACKED CMOS DEVICES WITH TWO DIELECTRIC MATERIALS IN A GATE CUT”. This document is related to a complementary field effect transistor (CFET) device is formed on a semiconductor substrate. The CFET device has a first transistor that is under a second transistor. A filled gate cut is directly adjacent to the sidewall of the gate of the CFET device. The first dielectric material in the gate cut is adjacent to the first transistor. The second dielectric material in the gate cut is adjacent to the second transistor. The two dielectric materials in the gate cut are selected to improve the electrical performance of each of the NFET and the PFET in the CFET device. The first dielectric material can apply a compressive stress to the channels of the first transistor when the first transistor is a PFET to improve the electrical performance of the PFET. When the second transistor is an NFET, the second dielectric material applies a tensile stress to NFET to improve NFET performance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898