DETAILED ACTION
Claims 1-10, 12-15, 17-20, 22 and 24 are pending. Claims 11, 16, 21, 23, and 25-42 have been canceled.
Election/Restrictions
Applicant’s election without traverse of Species I (FIG. 4B), encompassing claims 1-10, 12-15, 17-20, 22 and 24, in the reply filed on 3/26/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6, 8-9, 13-15, 17, and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 5, 6 and 22 reciting “smallest instantaneous angle” render the claims indefinite. It is unclear what constitutes an “instantaneous angle” and how it is defined. Furthermore, the term “smallest” is a relative term which renders the claim indefinite. The term “smallest” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear relative to what is “smallest” in comparison to.
Claim 8 reciting “the portion of the semiconductor layer” renders the claim indefinite due to lack of antecedent basis. It is unclear what is referred to by “the portion of the semiconductor layer”.
Claim 13 reciting “the upper surface of the semiconductor layer structure” renders the claim indefinite due to lack of antecedent basis. It is unclear what is referred to by “the upper surface of the semiconductor layer structure”.
Claim 14 reciting “the upper surface of the gate electrode” renders the claim indefinite due to unclear antecedent basis. It is unclear if “the upper surface” here is intended to refer to “upper surface of the first portion of the gate electrode” recited previously or is intended to refer to a different “upper surface” of the gate electrode.
Claim 15 reciting “the rounded upper corner of the gate trench” renders the claim indefinite. It is unclear which if the “first rounded upper corner” or “second rounded upper corner” is intended by the recited “the rounded upper corner of the gate trench”.
Claim 17 reciting “the upper surface of the semiconductor layer structure” renders the claim indefinite due to lack of antecedent basis. It is unclear what is referred to by “the upper surface of the semiconductor layer structure”.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10, 12-15, 17-20, 22, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Utsumi et al. US 2018/0097069 A1 (Utsumi).
PNG
media_image1.png
854
630
media_image1.png
Greyscale
In re claim 1, Utsumi discloses (e.g. FIGs. 1-2) a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 10 (¶ 51) that comprises an active region (¶ 50);
a gate trench 9 in an upper portion of the semiconductor layer structure 10, the gate trench 9 (¶ 60) having a first rounded lower corner 9a (left) and a second rounded lower corner 9a (right); and
a gate electrode 12 in the gate trench 9,
wherein, within the active region, an upper surface 12a of the gate electrode 12 is below or coplanar with an upper surface of the semiconductor layer structure 10 (upper surface 12a … may be positioned deeper within gate trench 9 than the front surface of the silicon carbide substrate 10 as long as gate electrode 12 is still filled … up to a height position facing the n+ source region 7; ¶ 62),
wherein the gate trench 9 (¶ 61) has a first rounded upper corner 9b (left) and a second rounded upper corner 9b (right).
In re claim 2, Utsumi disclose (e.g. FIG. 2A) wherein a radius of curvature of the first rounded lower corner 9a exceeds a radius of curvature of the first rounded upper corner 9b.
In re claim 3, Utsumi discloses (e.g. FIG. 1) wherein the upper surface 12a of the gate electrode12 is below the upper surface of the semiconductor layer structure 10 (upper surface 12a … may be positioned deeper within gate trench 9 than the front surface of the silicon carbide substrate 10 as long as gate electrode 12 is still filled … up to a height position facing the n+ source region 7; ¶ 62).
In re claim 4, Utsumi discloses (e.g. FIGs. 1 & 2A) wherein the upper surface 12a of the gate electrode 12 is below a midpoint of an arc defined by the first rounded upper corner 9b. Curved upper corners as shown in FIG. 2A remains at top portion of source region 7, while the upper surface 12a of the gate electrode can be filled up to a height of the source region 7; “upper surface 12a … may be positioned deeper within gate trench 9 than the front surface of the silicon carbide substrate 10 as long as gate electrode 12 is still filled … up to a height position facing the n+ source region 7”; ¶ 62).
In re claim 5, as best understood, Utsumi discloses (e.g. FIGs. 1 & 2A) wherein the upper surface 12a of the gate electrode 12 is below a location where the first rounded upper corner 9b has “a smallest instantaneous angle”. The location being at the front surface of substrate 10 where the rounded upper corner ends. The upper surface 12a of the gate electrode can be filled up to a height of the source region 7 (¶ 62), which is below the location at the front surface of the substrate 10.
In re claim 6, as best understood, Utsumi discloses (e.g. FIGs. 1 & 2A) wherein the upper surface 12a of the gate electrode is at least 0.1 microns below the location where the first rounded upper corner has “the smallest instantaneous angle”. The location being at the front surface of substrate 10 where the rounded upper corner ends. The upper surface 12a of the gate electrode can be filled up to a height of the source region 7 (¶ 62), which is a distance of t2 below the location at the front surface of the substrate 10. Utsumi discloses t2 is 0.5 µm (¶ 118). Thus, the upper surface 12a of the gate electrode filled to a height of the source region 7 is 0.5 µm below the location at the front surface of the substrate 10.
In re claim 7, Utsumi discloses (e.g. FIG. 2A) wherein a radius of curvature of the first rounded lower corner 9a is at least twice a radius of curvature of the first rounded upper corner 9b. See annotated FIG. 2A below showing different radii of curvature.
PNG
media_image2.png
854
630
media_image2.png
Greyscale
In re claim 8, as best understood, Utsumi discloses (e.g. FIGs. 1-2A) wherein the semiconductor layer structure 10 further comprises a termination region that surrounds the active region (not shown, ¶ 49-50), and “the portion of the semiconductor layer” 10 in the active region (FIG. 1) comprises:
a drift region 2 having a first conductivity (n) type;
a plurality of well regions 6 having a second conductivity (p) type that is different from the first conductivity (n) type on the drift region 2; and
a plurality of source regions 7 having the first conductivity (n) type, each source region 7 in an upper portion of respective one of the well regions 6.
In re claim 9, Utsumi disclose (e.g. FIG. 1) further comprising:
a plurality of additional gate trenches 9 (associated with plural unit cells, ¶ 49) in the upper surface of the semiconductor layer structure;
a plurality of additional gate electrodes 12 in the respective plurality of additional gate trenches 9, where an upper surface 12a of a portion of each additional gate electrode 12 that is within the active region is below the upper surface of the semiconductor layer structure 10 (upper surface 12a … may be positioned deeper within gate trench 9 than the front surface of the silicon carbide substrate 10 as long as gate electrode 12 is still filled … up to a height position facing the n+ source region 7; ¶ 62);
a gate dielectric layer 11 in the gate trench 9 between the gate electrode 12 and the semiconductor layer structure 10; and
a plurality of additional gate dielectric layers 11 in the respective additional gate trenches 9 between the respective additional gate electrodes 12 and the semiconductor layer structure 10.
In re claim 10, Utsumi discloses (e.g. FIG. 1) further comprising a gate dielectric layer 11 in the gate trench 9 between the gate electrode 12 and the semiconductor layer structure 10,
wherein the semiconductor device is configured so that during on-state operation a peak electric field value in the gate dielectric layer 11 will be located in a portion of the gate dielectric layer 11 that is below the upper surface of the semiconductor layer structure 10 (¶ 60-61,117).
No specific “on-state operation” has been claimed. Furthermore, a limitation directed to an operation state of the device does not render the device claimed structurally distinguishable over the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
In re claim 12, Utsumi discloses (e.g. FIGs. 1-2) a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 10 (¶ 51) that comprises an active region (¶ 50);
a gate trench 9 in an upper portion of the semiconductor layer structure 10, the gate trench 9 (¶ 60) having a first rounded lower corner 9a (left), a second rounded lower corner 9a (right), a first rounded upper corner 9b (left) and a second rounded upper corner 9b (left); and
a gate electrode 12 in the gate trench 9,
wherein a respective radius of curvature of the first rounded lower corner 9a exceeds a respective radius of curvature of the first rounded upper corner 9b. See annotated FIG. 2A above showing different radii of curvature.
In re claim 13, as best understood, Utsumi discloses edge termination region surrounding active region (not shown, ¶ 49-50). The gate electrodes 12 at the boundary of the termination region are considered to be “outside the active region”. Thus, Utsumi teaches wherein a first portion of the gate electrode 12 is within the active region (e.g. gate electrode 12 located at the center of the active region) and a second portion of the gate electrode (e.g. gate electrode 12 located at the boundary near the termination region) is outside the active region, and wherein an upper surface 12a of the first portion of the gate electrode 12 (located at the center of active region) is below or coplanar with “the upper surface of the semiconductor layer structure” 10 (upper surface 12a … may be positioned deeper within gate trench 9 than the front surface of the silicon carbide substrate 10 as long as gate electrode 12 is still filled … up to a height position facing the n+ source region 7; ¶ 62),
In re claim 14, Utsumi discloses wherein the upper surface 12a of the gate electrode 12 is below the upper surface of the semiconductor layer structure 10 (upper surface 12a … may be positioned deeper within gate trench 9 than the front surface of the silicon carbide substrate 10 as long as gate electrode 12 is still filled … up to a height position facing the n+ source region 7; ¶ 62),
In re claim 15, as best understood, Utsumi discloses (e.g. FIGs. 1 & 2A) wherein the upper surface 12a of the gate electrode is below a midpoint of an arc defined by “the rounded upper corner 9b of the gate trench”. The upper surface 12a of the gate electrode can be filled up to a height of the source region 7 (¶ 62), which is below the rounded upper corner 9b.
In re claim 17, as best understood, Utsumi discloses (e.g. FIGs. 1 & 2A) further comprising a gate dielectric layer 11 in the gate trench 9 between the gate electrode 12 and the semiconductor layer structure 10,
wherein the semiconductor device is configured so that during on-state operation a peak electric field value in the gate dielectric layer 11 will be located in a portion of the gate dielectric layer 11 that is below “the upper surface of the semiconductor layer structure” 10 (¶ 60-61,117).
No specific “on-state operation” has been claimed. Furthermore, a limitation directed to an operation state of the device does not render the device claimed structurally distinguishable over the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
In re claim 18, Utsumi discloses (e.g. FIGs. 1-2) a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 10 (¶ 51) that comprises an active region (¶ 50);
a gate trench 9 in an upper portion of the semiconductor layer structure 10, the gate trench 9 (¶ 60) having a first rounded lower corner 9a (left) and a second rounded lower corner 9a (right); and
a gate electrode 12 in the gate trench 9; and
a gate dielectric layer 11 in the gate trench 9 between the gate electrode 12 and the semiconductor layer structure 10,
wherein the semiconductor device is configured so that a peak electric field in the gate dielectric layer 11 during on-state operation is below an upper surface of the semiconductor layer structure 10 (¶ 60-61,117).
No specific “on-state operation” has been claimed. Furthermore, a limitation directed to an operation state of the device does not render the device claimed structurally distinguishable over the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
In re claim 19, Utsumi discloses wherein an upper surface 12a of the gate electrode 12 is below the upper surface of the semiconductor layer structure 10 (upper surface 12a … may be positioned deeper within gate trench 9 than the front surface of the silicon carbide substrate 10 as long as gate electrode 12 is still filled … up to a height position facing the n+ source region 7; ¶ 62),
In re claim 20, Utsumi discloses (e.g. FIG. 2A) wherein the gate trench 9 further has a first rounded upper corner 9b (left) and a second rounded upper corner 9b (right), and wherein a radius of curvature of the first rounded lower corner 9a exceeds a radius of curvature of the second rounded upper corner 9b. See annotated FIG. 2A above showing different radii of curvature.
In re claim 22, as best understood, Utsumi discloses (e.g. FIGs. 1 & 2A) wherein the gate trench 9 further has a first rounded upper corner 9b, and wherein an upper surface 12a of the gate electrode 12 is below a location where the first rounded upper corner has “a smallest instantaneous angle”. The location being at the front surface of substrate 10 where the rounded upper corner ends. The upper surface 12a of the gate electrode can be filled up to a height of the source region 7 (¶ 62), which is below the location at the front surface of the substrate 10.
In re claim 24, Utsumi discloses (e.g. FIG. 2A) wherein the gate trench 9 further has a first rounded upper corner 9b, and wherein a radius of curvature of the first rounded lower corner 9a is at least twice a radius of curvature of the first rounded upper corner 9b. See annotated FIG. 2A above showing different radii of curvature.
Claims 12-15, 17-18, 20, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lichtenwalner et al. US 2022/0130995 A1 (Lichtenwalner).
PNG
media_image3.png
870
1605
media_image3.png
Greyscale
In re claim 12, Lichtenwalner discloses (e.g. FIGs. 3, 3A & 3B) a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 240 (¶ 98) that comprises an active region;
a gate trench 222 (or trench defined above 232) in an upper portion of the semiconductor layer structure 240, the gate trench having a first rounded lower corner (e.g. bottom left corner of trench 222 or bottom left corner of trench above 232), a second rounded lower corner (e.g. bottom right corner of trench 222 or bottom right corner of trench above 232), a first rounded upper corner (upper left corner between 260 and 250) and a second rounded upper corner (upper right corner between 260 and 250); and
a gate electrode 270 in the gate trench,
wherein a respective radius of curvature of the first rounded lower corner (lower corner at bottom of trench 222 or lower corner of trench above 232) exceeds a respective radius of curvature of the first rounded upper corner (upper corner between 260 and 250). See annotated FIG. 3B above showing different radii of curvature.
In re claim 13, as best understood, Lichtenwalner discloses (e.g. FIG. 3, see annotated below) wherein a first portion of the gate electrode (lower portion of 270 below 250) is within the active region (no specific “active region” claimed to distinguish over region of 230 between 220 and 250 wherein channel 231 is formed) and a second portion of the gate electrode (upper portion of 270 above channel 231) is outside the active region, and wherein an upper surface of the first portion of the gate electrode (lower portion of 270 below 250) is below or coplanar with “the upper surface of the semiconductor layer structure” (top of 240).
PNG
media_image4.png
415
777
media_image4.png
Greyscale
In re claim 14, as best understood, Lichtenwalner discloses (e.g. FIG. 3) wherein “the upper surface of the gate electrode” (as best understood, top of the lower portion of 270 below 250) is below “the upper surface of the semiconductor layer structure” (top of 240).
In re claim 15, Lichtenwalner discloses (e.g. FIG. 3) wherein the upper surface of the first portion of the gate electrode (top of the lower portion of 270 below 250) is below a midpoint of an arc defined by “the rounded upper corner of the gate trench” (the lower portion of 270 below 250 is below rounded upper corners of the gate trench).
In re claim 17, as best understood, Lichtenwalner discloses (e.g. FIG. 3) further comprising a gate dielectric layer 260 in the gate trench between the gate electrode 270 and the semiconductor layer structure 240,
wherein the semiconductor device is configured so that during on-state operation a peak electric field value in the gate dielectric layer 260 will be located in a portion of the gate dielectric layer 260 that is below “the upper surface of the semiconductor layer structure” 240 (¶ 97,102).
No specific “on-state operation” has been claimed. Furthermore, a limitation directed to an operation state of the device does not render the device claimed structurally distinguishable over the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
In re claim 18, Lichtenwalner discloses (e.g. FIGs. 3, 3A & 3B) a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 240 (¶ 98) that comprises an active region;
a gate trench 222 (or trench defined above 232) in an upper portion of the semiconductor layer structure 240, the gate trench having a first rounded lower corner (e.g. bottom left corner of trench 222 or bottom left corner of trench above 232) and a second rounded lower corner (e.g. bottom right corner of trench 222 or bottom right corner of trench above 232);
a gate electrode 270 in the gate trench,
a gate dielectric layer 260 in the gate trench between the gate electrode 270 and the semiconductor layer structure 240,
wherein the semiconductor device is configured so that a peak electric field in the gate dielectric layer 260 during on-state operation is below an upper surface of the semiconductor layer structure 240 (¶ 97,102).
No specific “on-state operation” has been claimed. Furthermore, a limitation directed to an operation state of the device does not render the device claimed structurally distinguishable over the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
In re claim 20, Lichtenwalner discloses (e.g. FIG. 3) wherein the gate trench further has a first rounded upper corner (upper left corner between 260 and 250) and a second rounded upper corner (upper right corner between 260 and 250), and wherein a radius of curvature of the first rounded lower corner (lower corner at bottom of trench 222 or lower corner of trench above 232) exceeds a radius of curvature of the second rounded upper corner (upper corner between 260 and 250). See annotated FIG. 3B above showing different radii of curvature.
PNG
media_image5.png
740
547
media_image5.png
Greyscale
In re claim 24, Lichtenwalner discloses (e.g. FIG. 3B) wherein the gate trench further has a first rounded upper corner (upper corner between 260 and 250), and wherein a radius of curvature of the first rounded lower corner (lower corner of trench above 232) is at least twice a radius of curvature of the first rounded upper corner. See FIG. 3B annotated above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights