Prosecution Insights
Last updated: August 18, 2026
Application No. 18/453,688

INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME

Final Rejection §102
Filed
Aug 22, 2023
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
568 granted / 667 resolved
+17.2% vs TC avg
Moderate +14% lift
Without
With
+14.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
702
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
42.3%
+2.3% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
27.3%
-12.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 667 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Amendment filed 6/15/2026. Claims 16-35 are pending. Claims 1-15 are cancelled. Claims 21 and 30 are currently amended. Claims 16, 21 and 30 are independent. Response to Arguments Applicants’ arguments and amendments, filed 6/15/2026, with respect to Drawings Objections and 112 Rejections, as indicated in line numbers 2-4 of the office action mailed 3/19/2026, have been fully considered and are persuasive. The objections and rejections have been withdrawn. Applicants' arguments and amendments, filed 6/15/2026, with respect to independent claim 21, although substantive and pertinent to expediting the prosecution of the current application, are considered moot and not persuasive, respectfully, in light of new grounds of rejections made using the prior art of Lin as noted below in the rejection of independent claim 21. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2021/0126113 A1, hereinafter “Lin”). Regarding independent claim 21, Lin discloses a method, comprising: forming a first nanostructure 207 (“layers”- ¶0025, specifically the lowermost 207) spaced apart from a semiconductor substrate 201 (“semiconductor substrate”- ¶0024) by a first spacing (i.e., the vertical distance between 201 and the lowermost 207) (see Figs. 2A-2B); forming a second nanostructure 207 (“layers”- ¶0025, specifically the middle 207) above and spaced apart from the first nanostructure 207 by a second spacing (i.e., the vertical distance between the lowermost 207 and the middle 207), the second spacing being less than the first spacing (see Figs. 2A-2B); forming a dielectric isolation layer 501 (“spacers… dielectric material”- ¶0060) over the semiconductor substrate 201 (see Figs. 5A-5C); forming a first source/drain epitaxial structure 503 (“source/drain regions… epitaxial process”- ¶0064) adjacent to both the first nanostructure 207 and the second nanostructure 207, wherein the dielectric isolation layer 503 is between the first source/drain epitaxial structure 203 and the semiconductor substrate 201, wherein a top surface of the dielectric isolation layer 503 is higher than a top surface of the semiconductor substrate 201 and lower than a bottom surface of the first nanostructure 207 (see Figs. 5A-5C); and forming a first gate structure 107 (“gate electrodes”- ¶0021) surrounding the first nanostructure 207 and the second nanostructure 207 (see Figs. 8A-8B). Regarding claim 22, Lin discloses wherein a vertical distance between the top surface of the dielectric isolation layer 501 and the bottom surface of the first nanostructure 207 is less than the second spacing. Regarding claim 23, Lin discloses wherein a bottom surface of the first source/drain epitaxial structure 503 is in contact with the top surface of the dielectric isolation layer 501. Allowable Subject Matter Claims 24-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 24 (which claim 25 depends from), the prior art of record including Lin, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein a bottom surface of the first source/drain epitaxial structure is spaced apart from the top surface of the dielectric isolation layer by an air gap”. Regarding claim 26, the prior art of record including Lin, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] method… further comprising: forming an intrinsic epitaxial feature over the semiconductor substrate prior to forming the dielectric isolation layer, wherein the intrinsic epitaxial feature is between the dielectric isolation layer and the semiconductor substrate”. Regarding claim 27 (which claims 28-29 depend from), the prior art of record including Lin, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “[the] method… further comprising: forming a third nanostructure spaced apart from the semiconductor substrate by a third spacing; forming a fourth nanostructure above and spaced apart from the third nanostructure by a fourth spacing, the fourth spacing being less than the third spacing; forming a second gate structure surrounding the third nanostructure and the fourth nanostructure; and forming a second source/drain epitaxial structure adjacent to both the third nanostructure and the fourth nanostructure, wherein a bottom surface of the second source/drain epitaxial structure is lower than a bottom surface of the first source/drain epitaxial structure”. Claims 16-20 and 30-35 are allowed. Regarding independent claim 16, the claim is allowed for reasons as previously indicated in line number 5 of the office action mailed on 3/19/2026. Claims 17-20 are allowed as being dependent on allowed claim 16. Regarding independent claim 30, Lin discloses a method, comprising: forming a first nanostructure 207 (“layers”- ¶0025, specifically the lowermost 207) above a substrate 201 (“semiconductor substrate”- ¶0024) (see Figs. 2A-2B); forming a second nanostructure 207 (“layers”- ¶0025, specifically the middle 207) above the first nanostructure 207 (see Figs. 2A-2B); forming a gate spacer 309 (“spacers”- ¶0044) over the second nanostructure 207 (see Figs. 3A-3B); forming a first inner spacer 403 (“inner spacers”- ¶0047, specifically the lowermost 403) below the first nanostructure 207, and a second inner spacer 403 (“inner spacers”- ¶0047, specifically the middle 403) between the first and second nanostructures 207 (see Figs. 4A-4B); forming a gate structure 301 (“dummy gate stacks”- ¶0024) surrounding the first and second nanostructures 207 (see Figs. 3A-3B); forming a source/drain epitaxial structure 503 (“source/drain regions… epitaxial process”- ¶0064) adjacent to the first and second nanostructures 207 wherein the source/drain epitaxial structure 503 is spaced apart from the gate structure 301 by the first inner spacer 403 and the second inner spacer 403 (see Figs. 5A-5C); and forming a source/drain contact 1401 (“source/drain contacts”- ¶0101) over the source/drain epitaxial structure 503 (see Figs. 14A-14B). Lin does not expressly disclose wherein the first inner spacer has a width less than a width of the gate spacer and a height greater than a height of the second inner spacer and wherein the source/drain contact is spaced apart from the gate structure by the gate spacer. Thus, regarding independent claim 30, the claim is allowed, because the prior art of record including Lin, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “wherein the first inner spacer has a width less than a width of the gate spacer and a height greater than a height of the second inner spacer” and “wherein the source/drain contact is spaced apart from the gate structure by the gate spacer”. Claims 31-35 are allowed as being dependent on allowed claim 30. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Aug 22, 2023
Application Filed
Mar 19, 2026
Non-Final Rejection mailed — §102
Jun 15, 2026
Response Filed
Jul 14, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+14.0%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 667 resolved cases by this examiner. Grant probability derived from career allowance rate.

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