DETAILED ACTION
This Office action responds to Applicant’s election filed on 12/01/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The Applicant’s response on 12/01/2025 in reply to the restriction mailed on 10/01/2025 has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-10.
Election/Restriction
The Applicant’s response on 12/01/2025 in reply to the restriction/election requirements mailed on 10/01/2025 has been entered. Applicant’s election without traverse of Species 1 corresponding to fig. 3, drawn to claims 1-10, is acknowledged. Examiner agrees.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 2, 9, and 10 are rejected under 35 U.S.C. 112(b) as being indefinite.
The claims are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint regard as the invention.
Claim 1 recites the limitation “the device adhering area”. Due to the antecedent basis, the limitation should be “a device adhering area”.
Claims 2 and 9 recite the limitation of "photo-imagable”. This limitation should be corrected with “photo-imageable”.
Claim 10 recites the limitation of “a semiconductor, comprising at least one embedded substrate”. The claim does not define what the semiconductor is. It is not clear from this claim if the semiconductor is equivalent to the embedded device or the semiconductor package. Also, it is not clear if the embedded substrate is in the semiconductor (or embedded device) or in the semiconductor package. For the purposes of examination to apply prior art, the semiconductor was treated as the embedded device, and the embedded substrate as the first semi-finished substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2021/0183783) in view of Sinha (US 2024/0145337).
Regarding claim 1, Park shows (see, e.g., Park: fig. 8) most aspects of the instant invention including a substrate manufacturing method, comprising:
Manufacturing a first semi-finished substrate 111b/112c/112b, wherein the first semi-finished substrate 111b/112c/112b comprises a plurality of first circuit layers 112c/112b electrically connected with each other and at least one first dielectric layer 111b (see, e.g., Park: par. [0028])
The first circuit layers 112c/112b and the first dielectric layer 111b are arranged in a staggered and laminated manner (see, e.g., Park: par. [0051])
A number a of the first circuit layers 112c/112b and a number b of the first dielectric layer 111b satisfy a = b + 1, a ≥ 2 (see, e.g., Park: fig. 8, where b = 1, and a = 2)
Arranging a viscous material layer 125 on the first circuit layer 112b to form a device adhering area (see, e.g., Park: par. [0052])
Adhering an embedded device 120 on the device adhering area, wherein a pin face of the embedded device 120 faces away from the viscous material layer 125
Laminating a second dielectric layer 111a/130 on the first circuit layer 112b (see, e.g., Park: par. [0052]), wherein the second dielectric layer 130 covers the viscous material layer 125 and the embedded device 120
Manufacturing a first conductive pillar 113a/112a/133, a second conductive pillar 133 (see, e.g., Park: fig. 8, it is actually the element equivalent to the element 133, but on top of the element 120) and a second circuit layer 132, wherein the first conductive pillar 113a/112a/133 extends through the second dielectric layer 111a/130 and is configured for connecting the second circuit layer 132 with the first circuit layer 112b, the second conductive pillar 133 is configured for connecting the embedded device 120 with the second circuit layer 132
However, Park fails (see, e.g., Park: fig. 8) to show that a projection area of the viscous material layer 125 in a direction perpendicular to the substrate 111b/112c/112b is smaller than a projection area of a device 120 in the direction perpendicular to the substrate 111b/112c/112b. Sinha, in a similar method to Park, shows (see, e.g., Sinha: fig. 4) that a projection area of the viscous material layer 410 (see, e.g., Sinha: par. [0036]) in a direction perpendicular to the substrate 404 is smaller than a projection area of a device 408 in the direction perpendicular to the substrate 404. Sinha also shows (see, e.g., Sinha: fig. 4) that the projection area of the viscous material layer 410 in a direction perpendicular to the substrate 404 is smaller than the projection area of a device 408 in the direction perpendicular to the substrate 404 in order to enable openings and accommodating connecting wiring bonds 416 between the semiconductor device 408 and substrate 404 (see, e.g., Sinha: par. [0071]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a projection area of the viscous material layer of Sinha, smaller than a projection area of a device a direction perpendicular to the substrate, in the method of Park, in order to in order to enable openings and accommodating connecting wiring bonds between the semiconductor device and substrate.
However, the differences in the projection areas of viscous material layer will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned the projection areas of viscous material layer, and Sinha has identified such projection areas as result-effective variables subject to optimization (see, e.g., Sinha: par. [0071]), it would have been obvious to one of ordinary skill in the art to use these projection area values in the device of Park.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed projection area values or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 2, Park in view of Sinha shows (see, e.g., Park: fig. 8) that arranging the viscos material layer 125 on the first circuit layer 112b (see, e.g., Park: par. [0052]) to form the device adhering area comprises the step of arranging a photo-imageable dielectric (PID) material layer on the first circuit layer 112b or arranging a Die Attach Film (DAF) material layer 125 on the first circuit layer 112b to form the device adhering area.
Regarding claim 7, Park in view of Sinha shows (see, e.g., Park: fig. 8) most aspects of the instant invention including a substrate manufacturing method (see paragraph 15), comprising:
A first semi-finished substrate 111b/112c/112b, wherein the first semi-finished substrate 111b/112c/112b comprises a plurality of first circuit layers 112c/112b electrically connected with each other and at least one first dielectric layer 111b (see, e.g., Park: par. [0028])
The first circuit layers 112c/112b and the first dielectric layer 111b are arranged in a staggered and laminated manner (see, e.g., Park: par. [0051])
A number a of the first circuit layers 112c/112b and a number b of the first dielectric layer 111b satisfy a = b + 1, a ≥ 2 (see, e.g., Park: fig. 8, where b = 1, and a = 2)
Arranging a viscous material layer 125 on the first circuit layer 112b to form a device adhering area (see, e.g., Park: par. [0052])
Adhering an embedded device 120 on the device adhering area, wherein a pin face of the embedded device 120 faces away from the viscous material layer 125
A viscous material layer 125 arranged between embedded device 120 and the semi-finished substrate 111b/112c/112b (see, e.g., Park: par. [0052])
Adhering an embedded device 120 on the device adhering area, wherein a pin face of the embedded device 120 faces away from the viscous material layer 125
The embedded device 120, wherein the pin face of the embedded device 120 is arranged to face away from the first circuit layer 112b of the semi-finished substrate 111b/112c/112b
The second circuit layer 132 connected with the embedded device 120 and the first circuit layer 112b of the semi-finished substrate 111b/112c/112b
The second dielectric layer 111a/130 arranged between the semi-finished substrate 111b/112c/112b and the second circuit layer 132, and covering the embedded device 120
Regarding claim 8, Park in view of Sinha shows (see, e.g., Park: fig. 8) that the embedded device 120 comprises an active device or a passive device (see, e.g., Park: par. [0040]).
Regarding claim 9, Park in view of Sinha shows (see, e.g., Park: fig. 8) that the viscous material layer 125 comprises a photo-imageable dielectric (PID) material layer or a Die Attach Film (DAF) material layer (see, e.g., Park: par. [0052]).
Regarding claim 10, Park in view of Sinha shows (see, e.g., Park: fig. 8) that the semiconductor 120 comprising at least one embedded substrate 111b/112c/112b.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Sinha in further view of Akram (US 2003/0011059).
Regarding claim 3, Park in view of Sinha shows (see, e.g., Park: fig. 8) most of the aspects of the instant application (see paragraph 15), including a viscos material layer 125 that is made of a die attach film (DAF).
Park in view of Sinha shows (see, e.g., Park: fig. 8) that arranging the viscous material 125 on the first layer 112b comprises:
Arranging the viscos material layer 125 on the first circuit layer 112b, wherein the viscos material layer 125 covers the first circuit layer 112b
However, Park in view of Sinha fails (see, e.g., Park: fig. 8) to show that the viscous material layer 125 is a photo-imageable dielectric (PID) material layer. Park in view of Sinha shows (see, e.g., Park: fig. 8) that the viscos material layer 125 is a die attach film (DAF) (see, e.g., Park: par. [0052]). Akram, in a similar method to Park in view of Sinha, shows (see, e.g., Akram: figs. 5-8) that the viscos material layer 66 is a photo-imageable dielectric (PID) material layer (see, e.g., Akram: par. [0039]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the PID viscous material of Akram or the DAF viscous material of Park in view of Sinha because these were recognized in the semiconductor art for their use as adhesive viscous materials in methods of manufacturing semiconductor device packages, as taught by Akram and by Park in view of Sinha, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Park in view of Sinha in view of Akram shows (see, e.g., Akram: figs. 5-8) the method step of performing a photoetching process on the PID material layer 66 to form the device adhering area (see, e.g., Akram: par. [0039]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Sinha in view of Robert (US 2012/0243192) in further view of Chuang (US 2023/0369263).
Regarding claim 4, Park in view of Sinha shows (see, e.g., Park: fig. 8) that manufacturing the first conductor pillar 113a/112a/133, the second conductor pilar 133, and the second circuit layer 132 comprises:
Forming a first through hole 113a/112a/133 and a second through hole 133 in the dielectric layer 111a/130, so that the first circuit layer 112b is exposed and a pin 120P of the embedded device 120 is exposed
Performing hole filling and electroplating in the first through hole 113a/112a/133 (see, e.g., Park: par. [0038], and [0044]) and the second through hole 133 (see, e.g., Park: par. [0044]) to obtain the first conductive pillar 113a/112a/133, and the second conductive pillar 133
However, Park in view of Sinha fails (see, e.g., Park: fig. 8) to show the method step of drilling the second dielectric layer 111a/130 to form through holes. Park in view of Sinha is actually silent about the method of making through holes in the second dielectric layer 111a/130. Robert, in a similar method to Park in view of Sinha, shows (see, e.g., Robert: fig. 6) the method step of drilling though holes 111/115/117 in a dielectric layer 112 (see, e.g., Robert: par. [0030]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the method step of drilling through holes of Robert or the method step of making through holes of Park in view of Sinha because these were recognized in the semiconductor art for their use as method steps of making though holes in semiconductor device substrates, as taught by Robert and by Park in view of Sinha, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
However, Park in view of Sinha in view of Robert fails (see, e.g., Park: fig. 8) to show a method step of forming a second seed layer on the second dielectric layer 112. Chuang, in a similar method to Park in view of Sinha in view of Robert, shows (see, e.g., Chuang: fig. 7) a method step of forming a seed layer on the dielectric layer 132 (see, e.g., Chuang: par. [0031]). Chuang also shows (see, e.g., Chuang: fig. 7) that the method step of forming a seed layer on the dielectric layer 132 is to form a basic seed layer that that be manufactured in a wiring layer 138 after subsequent method steps (see, e.g., Chen: fig.7 and par. [0031]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of forming a seed layer of Chuang in the method of Park in view of Sinha in view of Robert, in order to form a basic seed layer that can be manufactured in a wiring layer after subsequent method steps.
Park in view of Sinha in view of Robert in view of Chuang shows the method step of performing a photoetching process on the second seed layer 138 to obtain the second circuit layer 138 (see, e.g., Chuang: par. [0031]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Sinha in further view of Morita (US 2022/0310547).
Regarding claim 5, Park in view of Sinha shows (see, e.g., Park: fig. 8) most aspects of the instant invention (see paragraph 15), including the viscos material layer 125 on the first circuit layer 112b (see, e.g., Park: par. [0052]), which is a DAF material. Park in view of Sinha shows (see, e.g., Park: figs. 5 and 8) that the viscos material layer 125 is formed at a preset position of the first circuit layer 112b.
However, Park in view of Sinha fails (see, e.g., Park: fig. 8) to show that arranging the PID material layer on the first circuit layer or arranging the DAF material layer on the first circuit layer comprises laminating the PID material layer on the first circuit layer or coating the DAF material. Thus, Park in view of Sinha fails (see, e.g., Park: fig. 8) to show the method of forming the DAF material. Park in view of Sinha is actually (see, e.g., Park: fig. 8) silent about the method of forming the DAF material. Morita, in a similar method to Park in view of Sinha, shows (see, e.g., Morita: figs. 1-6) that the method of forming the DAF material is coating (see, e.g., Morita: par. [0169]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the method step of coating the DAF material of Morita or the method step of forming the DAF material of Park in view of Sinha because these were recognized in the semiconductor art for their use as method steps of making DAF materials in semiconductor device substrates, as taught by Morita and by Park in view of Sinha, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Sinha in further view of Chuang (US 2023/0369263).
Regarding claim 6, Park in view of Sinha shows (see, e.g., Park: fig. 8) most of the aspects of the instant application (see paragraph 15), including the first semi-finished substrate 111b/112c/112b, comprising:
An Nth dielectric layer 111b on a surface of an Nth metal layer 112c, and arranging an N+1th metal layer 112b on the Nth dielectric layer 111b, wherein N ≥ 1 (this is the case for N = 1)
However, Park in view of Sinha fails (see, e.g., Park: fig. 8) to show the method step of laminating the Nth dielectric layer 111b on a surface of an Nth metal layer 112c. Park in view of Sinha is actually (see, e.g., Park: fig. 8) silent about the method step of forming the Nth dielectric layer 111b on a surface of an Nth metal layer 112c. Chuang, in a similar method to Park in view of Sinha, shows (see, e.g., Chuang: fig. 7) that the method step of forming the Nth dielectric layer 148 on a surface of an Nth metal layer 146 is lamination (see, e.g., Chuang: par. [0030]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the method step of Chuang of laminating the Nth dielectric layer on a surface of an Nth metal layer or the method step of Park in view of Sinha of forming the Nth dielectric layer on a surface of an Nth metal layer because these were recognized in the semiconductor art for their use as method steps of making dielectric/metal stacks of layers in semiconductor device substrates, as taught by Chuang and by Park in view of Sinha, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Park in view of Sinha in view of Chuang shows (see, e.g., Chuang: fig. 7) the methos step of performing a photoetching process on the N+1th metal layer 146 to form N+1 first circuit layers 138/146, wherein the N+1 first circuit layers 138/146 are electrically connected with each other through conductive pillars, wherein N ≥ 1 (this is the case for N = 1) (see, e.g., Chuang: par. [0031]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814