DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, claims 1-17 and 21-23 in the reply filed on 4/20/2026 is acknowledged.
Claim Objections
Claim 15 is objected to because of the following informalities: “the passivation layer” should be --the first passivation layer--. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23; line 2 recited the phrase “each sidewall of the first conducive connectors”, however “each sidewall” is not clearly define in the claim or specification, whereas according to drawing Fig. 1D, conductive post 192 is circular. Therefore, the scope of the limitation “each sidewall” is unclear and indefinite. In the interest of prosecution “each sidewall” will be interpreted as side wall of the circular conductive post 192.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8, 10-11, 16 and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HSU, US 2023/0023380.
Regarding claim 1, HSU discloses; an integrated circuit, comprising: a semiconductor substrate (Fig. 11A-16 and [0066]; insulating layers 242); an interconnection structure disposed on the semiconductor substrate (Fig. 11A- 16 and [0066]; wiring interconnects 244 disposed on insulating layers 242); a first dielectric layer disposed on the interconnection structure (Fig. 11A-16 and [0065]; core substrate 210 disposed on wiring interconnects 244); conductive pads disposed on the first dielectric layer (Fig. 11A,16 and [0067]; bonding pads 268 disposed on core substrate 210), wherein the conductive pads are electrically connected to the interconnection structure (Fig. 11A,16 and [0067]; bonding pads 268 connected through wiring interconnects 264 with interconnects 244); a second dielectric layer disposed on the first dielectric layer to laterally surround the conductive pads (Fig. 11A,16 and [0066]; insulating layers 262 disposed on core substrate 210 and surround the bonding pads 268); conductive connectors disposed on and electrically connected to the conductive pads (Fig. 13,16 and [0074]; solder material portions 290 disposed on bonding pads 268); and an anti-stress layer disposed over the conductive pads (Fig. 12A,16 and [0069]; cushioning film 270 that absorbs mechanical stress, disposed on bonding pads 268), wherein the anti-stress layer laterally surrounds some of the conductive connectors (Fig. 13-16 and [0069]; cushioning film 270 surrounds solder material portions 290).
Regarding claim 2, HSU discloses; the anti-stress layer comprises anti-stress patterns, and the anti-stress patterns are located at four corners of the integrated circuit (Fig. 15B-15C and [0083]; rectangular and L-shaped cushioning films 270 located at outside corner regions).
Regarding claim 3, HSU discloses; each of the anti-stress patterns exhibits a square, a rectangle, a triangle, a quadrant, or an L-shape from a top view (Fig. 15B-15C and [0083]; rectangular and L-shaped cushioning films 270 located at outside corner regions).
Regarding claim 6, HSU discloses; the anti-stress layer exhibits a ring-shape from a top view (Fig. 14B-15A and [0083]; rectangular frame-shaped cushioning film 270 exhibits a continuous ring-shape from top view).
Regarding claim 7, HSU discloses; the anti-stress layer laterally surrounds all of the conductive connectors (Fig. 14B-15A and [0083]; rectangular frame-shaped cushioning film 270 surrounds all solder material portions 290).
Regarding claim 8, HSU discloses; the anti-stress layer is in physical contact with sidewalls of the some of the conductive connectors (Fig. 15C and [0083]; rectangular cushioning films 270 located at corner regions are in physical contact with solder material portions 290).
Regarding claim 10, HSU discloses; a semiconductor device, comprising: a substrate (Fig. 16 and [0074]; a PCB substrate 110); and a package structure disposed on the substrate (Fig. 13-16 and [0091]; fan-out package 900 disposed on PCB substrate 110), comprising: an interposer (Fig. 13-16 and [0065]; interposer 200); and an integrated circuit disposed on the interposer, comprising: a semiconductor substrate (Fig. 11A-16 and [0066]; insulating layers 242); an interconnection structure disposed on the semiconductor substrate (Fig. 11A- 16 and [0066]; wiring interconnects 244 disposed on insulating layers 242); a first dielectric layer disposed on the interconnection structure (Fig. 11A-16 and [0065]; core substrate 210 disposed on wiring interconnects 244); conductive pads disposed on the first dielectric layer (Fig. 11A-16 and [0067]; bonding pads 268 disposed on core substrate 210); a second dielectric layer disposed on the first dielectric layer to laterally surround the conductive pads (Fig. 11A,16 and [0066]; insulating layers 262 disposed on core substrate 210 and surround the bonding pads 268); a first passivation layer disposed over the second dielectric layer and the conductive pads (Fig. 14A,16 and [0075]; underfill material portion 292 disposed over insulating layers 262 and the bonding pads 268); conductive connectors disposed on the first passivation layer and the conductive pads (Fig. 13-16 and [0074]; solder material portions 290 disposed on underfill material portion 292 and bonding pads 268); and an anti-stress layer disposed (Fig. 13-16 and [0069]; cushioning film 270 disposed on underfill material portion 292) on the first passivation layer to at least partially cover the first passivation layer (Fig. 13-16; cushioning film 270 partially cover sideways the underfill material portion 292 at the inner-peripheral region).
Regarding claim 11, HSU discloses; the anti-stress layer comprises anti-stress patterns, and the anti-stress patterns are located at four corners of the integrated circuit (Fig. 15B-15C and [0083]; rectangular and L-shaped cushioning films 270 located at outside corner regions).
Regarding claim 16, HSU discloses; the anti-stress layer is in physical contact with sidewalls of the conductive connectors (Fig. 15C and [0083]; rectangular cushioning films 270 located at corner regions are in physical contact with solder material portions 290).
Regarding claim 21, HSU discloses; a semiconductor device, comprising: a substrate (Fig. 16 and [0074]; a PCB substrate 110); and a package structure disposed on the substrate (Fig. 13-16 and [0091]; fan-out package 900 disposed on PCB substrate 110), comprising: an interposer (Fig. 13-16 and [0065]; interposer 200); and an integrated circuit disposed on the interposer, comprising: a semiconductor substrate (Fig. 11A-16 and [0066]; insulating layers 242); an interconnection structure disposed on the semiconductor substrate (Fig. 11A- 16 and [0066]; wiring interconnects 244 disposed on insulating layers 242); a first dielectric layer disposed on the interconnection structure (Fig. 11A-16 and [0065]; core substrate 210 disposed on wiring interconnects 244); conductive pads disposed on the first dielectric layer (Fig. 11A-16 and [0067]; bonding pads 268 disposed on core substrate 210); a second dielectric layer disposed on the first dielectric layer to laterally surround the conductive pads (Fig. 11A,16 and [0066]; insulating layers 262 disposed on core substrate 210 and surround the bonding pads 268); first conductive connectors and second conductive connectors disposed on the conductive pads (Fig. 13-16 and [0074]; solder material portions 290 disposed on bonding pads 268), wherein the first conductive connectors are located at four corners of the integrated circuit (Fig. 13-16 and [0074]; solder material portions 290 disposed at the four corners of the interposer 200); and an anti-stress layer disposed aside the first conductive connectors to laterally surround the first conductive connectors (Fig. 14B-15A and [0083]; rectangular frame-shaped cushioning film 270 surrounds the solder material portions 290 at the four corners of the interposer 200).
Regarding claim 22, HSU discloses; the first conductive connectors protrude from a top surface of the anti-stress layer (Fig. 13-16 and [0099]; cushioning film 270 has a uniform thickness, the uniform thickness is less than a maximum height of the solder material portions 290).
Regarding claim 23, HSU discloses; the anti-stress layer partially covers each sidewall of the first conducive connectors (Fig. 15C and [0083]; rectangular cushioning films 270 located at corner regions are partially covers sidewall of the solder material portions 290).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5, 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over HSU, US 2023/0023380 as applied to claims 1-3, 6-8, 10-11, 16 and 21-23 above, and in view of Park, US 2015/0200186.
Regarding claims 4-5 and 12, HSU discloses; the integrated circuit has a first side and a second side connected to the first side, the first side extends along a first direction, the second side extends along a second direction perpendicular to the first direction, a diameter of each of the conductive connectors is d (Fig. 14B-15B; W1, W2 is first side and L1, L2 is second side and solder material portions 290 has diameter). HSU substantially discloses the invention with rectangular cushioning films 270 located about corner regions in physical contact with solder material portions 290, but is silent about a minimum distance between the conductive connectors and the second side is d1, a width of the integrated circuit along the first direction is W1, a width of each anti-stress pattern along the first direction is W2, and d1+d ≤ W2 ≤ W1 in claim 4, a minimum distance between the conductive connectors and the first side is d2, a length of the integrated circuit along the second direction is L1, a length of each anti-stress pattern along the second direction is L2, and d2+d ≤ L2 ≤ L1 in claim 5 and a minimum distance between the conductive connectors and the second side is dl, a width of the integrated circuit along the first direction is W1, a width of each anti-stress pattern along the first direction is W2, d1+d ≤ W2 ≤ W1, a minimum distance between the conductive connectors and the first side is d2, a length of the integrated circuit along the second direction is L1, a length of each anti-stress pattern along the second direction is L2, and d2+d ≤ L2 ≤L1 in claim 12. However, Park shows that for a stress buffer layer 400c and connection member 600, a minimum distance between the conductive connectors and the second side is d1, a width of the integrated circuit along the first direction is W1, a width of each anti-stress pattern along the first direction is W2, and d1+d ≤ W2 ≤ W1 in claim 4 (Attached Fig.2D), a minimum distance between the conductive connectors and the first side is d2, a length of the integrated circuit along the second direction is L1, a length of each anti-stress pattern along the second direction is L2, and d2+d ≤ L2 ≤ L1 in claim 5 (Attached Fig.2D) and a minimum distance between the conductive connectors and the second side is dl, a width of the integrated circuit along the first direction is W1, a width of each anti-stress pattern along the first direction is W2, d1+d ≤ W2 ≤ W1, a minimum distance between the conductive connectors and the first side is d2, a length of the integrated circuit along the second direction is L1, a length of each anti-stress pattern along the second direction is L2, and d2+d ≤ L2 ≤L1 in claim 12 (Attached Fig.2D). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify HSU by providing a minimum distance between the conductive connectors and the second side is d1, a width of the integrated circuit along the first direction is W1, a width of each anti-stress pattern along the first direction is W2, and d1+d ≤ W2 ≤ W1 in claim 4, a minimum distance between the conductive connectors and the first side is d2, a length of the integrated circuit along the second direction is L1, a length of each anti-stress pattern along the second direction is L2, and d2+d ≤ L2 ≤ L1 in claim 5 and a minimum distance between the conductive connectors and the second side is dl, a width of the integrated circuit along the first direction is W1, a width of each anti-stress pattern along the first direction is W2, d1+d ≤ W2 ≤ W1, a minimum distance between the conductive connectors and the first side is d2, a length of the integrated circuit along the second direction is L1, a length of each anti-stress pattern along the second direction is L2, and d2+d ≤ L2 ≤L1 in claim 12 so that the first and second buffer structures are part of a stress buffer layer, and the stress buffer layer has a modulus that reduces a stress or strain influence from the capping layer when the package substrate contracts or expands ([0018]).
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Regarding claim 9, HSU discloses; a Young's modulus of the anti-stress layer is about 1 GPa to about 100 GPa ([0071]; cushioning film 270 may comprise, a material having a Young's modulus less than 4.0 GPa, and/or less than 2.0 GPa). HSU substantially discloses the invention with rectangular cushioning films 270 with coefficient of thermal expansion at room temperature is higher than the coefficient of thermal expansion at room temperature the second underfill material but is silent about a coefficient of thermal expansion (CTE) of the anti-stress layer is about 2.6 ppm/°C to about 50 ppm/°C. However, Park teaches that the stress buffer layer 400 have a low modulus of, for example, about 0.1 MPa to about 500 MPa ([0086]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify HSU by providing a coefficient of thermal expansion (CTE) of the anti-stress layer is about 2.6 ppm/°C to about 50 ppm/°C so that the substrate expanded and/or contracted with little influence of the sealing member ([0086]).
Claim(s) 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over HSU, US 2023/0023380 as applied to claims 1-3, 6-8, 10-11, 16 and 21-23 above, and in view of YEN, US 2021/0125860.
Regarding claims 13 and 15, HSU substantially discloses the invention with cushioning film 270 partially cover sideways the underfill material portion 292 at the inner-peripheral region, but is silent about the integrated circuit further comprises a second passivation layer sandwiched between the second dielectric layer and the first passivation layer in claim 13 and the anti-stress layer completely covers the passivation layer in claim 15. However, YEN teaches that second passivation layer 140 is over contact pads 130 and first passivation layer 120 and soft film 150 functioning as a stress buffer completely covers the passivation layer 140 (Fig. 1 and [0015-0016]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify HSU by providing the integrated circuit further comprises a second passivation layer sandwiched between the second dielectric layer and the first passivation layer in claim 13 and the anti-stress layer completely covers the passivation layer in claim 15, so as to protect contact pads from damage ([0015]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over HSU, US 2023/0023380 as applied to claims 1-3, 6-8, 10-11, 16 and 21-23 above, and in view of Hung, US 9,287,194.
Regarding claim 14, HSU substantially discloses the invention of with fan-out package and packaging substrate, but is silent about a reinforcement structure disposed on the substrate to laterally surround the package structure. However, Hung teaches that SIS 120 results in structural reinforcement along diagonal and peripheral portions of the packaging substrate 102 (Fig. 1-10 and Col. 10; Ln. 34-36). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify HSU by providing a reinforcement structure disposed on the substrate to laterally surround the package structure, as a result the bending stress (σ) and mechanical warpage induced to the entire package structure is minimized, thus reducing the risk of structural failure of the semiconductor devices (Col. 10; Ln. 40-43).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over HSU, US 2023/0023380 as applied to claims 1-3, 6-8, 10-11, 16 and 21-23 above, and in view of ZENG, CN 111244111.
Regarding claim 17, HSU discloses; the interposer comprises: an interposer substrate having a first surface and a second surface opposite to the first surface (Fig. 13-16 and [0065]; interposer 200 has first surface and second surface), wherein the integrated circuit is disposed on the first surface (Fig. 11A- 16 and [0066]; wiring interconnects 244 disposed on insulating layers 242). HSU substantially discloses the invention with rectangular cushioning films 270 located about corner regions in physical contact with solder material portions 290, but is silent about an auxiliary anti-stress layer disposed on the second surface. However, ZENG teaches that array substrate has first stress absorbing layer 206 and further comprises a second stress absorbing layer 404 (Fig. 8). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify HSU by providing an auxiliary anti-stress layer disposed on the second surface, so that the second stress absorbing layer can absorb when relieving bending suffered by the second inorganic encapsulating layer, the condition to relieve the encapsulation membrane is broken during the bending process; ensure the bending quality and improve the display effect (Page 9; ¶ 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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