DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 7-26 without traverse in the reply filed on 01/09/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22, line 7-8, the limitation “planarizing the etch stop layer” renders the claim indefinite since there is nowhere in the specification and the drawing described this limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-8, 10-13, 15-17, 19, 21, 23 and 25-26 are rejected under 35 U.S.C. 102(a)(1) [0061] as being anticipated by Chen et al [US 2020/0105772].
► With respect to claim 7, Chen et al (figs 1A-13, text [0001]-[0061]) disclose a method for manufacturing a semiconductor device, comprising:
forming an etch stop layer (124, fig 5, text [0036]) with an opening (502, text [0037]);
forming a barrier layer (602, fig 6, text [0038]) on the etch stop layer to fill the opening, the barrier layer including a layer portion disposed on the etch stop layer and an insert portion protruding from the layer portion so as to be inserted into the opening of the etch stop layer;
forming a bottom electrode layer (604, 802, fig 8, text [0038]-[0040]) on the layer portion of the barrier layer opposite to the etch stop layer;
forming a ferroelectric layer (804, fig 8, text [0040]) on the bottom electrode layer opposite to the barrier layer; and
forming a top electrode layer (806, fig 8, text [0040]) on the ferroelectric layer opposite to the bottom electrode layer.
► With respect to claim 8, Chen et al disclose further comprising, before formation of the ferroelectric layer (804, text [0040]), planarizing the bottom electrode layer(604/802, text [0038]-[0039]) so as to permit the bottom electrode layer to be formed with an upper flat surface.
► With respect to claim 10, Chen et al disclose further comprising forming a mask layer (808, fig 8, text [0040]) on the top electrode layer (806, text [0040]).
► With respect to claim 11, Chen et al disclose further comprising patterning the mask layer (808, text [0040]) and the top electrode layer (806, text [0040]) so as to form the mask layer (116,fig 9, text [0042]) and the top electrode layer (114, text [0042]) into a mask and a top electrode, respectively, the mask cooperating with the top electrode to form a stack.
► With respect to claim 12, Chen et al disclose further comprising forming a spacer layer (1002, text [0044]) to cover the ferroelectric layer (804, text [0040]) and the stack.
► With respect to claim 13, Chen et al disclose further comprising etching the spacer layer (1002, fig 10, text [0044]) so as to form the spacer layer (118, text [0045]) into a pair of spacers disposed on the ferroelectric layer to cover two lateral sides of the stack.
► With respect to claim 15, Chen et al (figs 1A-13, text [0001]-[0061]) disclose a method for manufacturing a semiconductor device, comprising:
forming an interconnect structure on a semiconductor substrate (308, fig 2, text [0027]), the interconnect structure including a dielectric layer (122, fig 1A & 3, text [0030]) and a conductive interconnect (106be, text [0025]) disposed in the dielectric layer;
forming a first etch stop layer (124, fig 4, text [0036]) on the interconnect structure;
forming on the first etch stop layer, a barrier layer (602, fig 6, text [0038]) which includes a layer portion disposed on the first etch stop layer and an insert portion protruding from the layer portion and penetrating the first etch stop layer so as to be connected to the conductive interconnect;
forming a bottom electrode layer (604, 802, figs 6-8, text [0038]-[0040]) on the layer portion of the barrier layer opposite to the first etch stop layer;
planarizing the bottom electrode layer (604, 802, text [0038]-[0040]);
forming a ferroelectric layer (804, fig 8, text [0040]) on the bottom electrode layer opposite to the barrier layer; and
forming a top electrode layer (806, fig 8, text [0040]) on the ferroelectric layer opposite to the bottom electrode layer.
► With respect to claim 16, Chen et al (fig 3-13, cols 3-6) disclose further comprising, after formation of the first etch stop layer (124, text [0036]) and before formation of the barrier layer (602, text [0038]), patterning the first etch stop layer so as to form an opening (502, text [0037]) penetrating from an upper surface of the first etch stop layer to a lower surface of the first etch stop layer, the upper surface of the first etch stop layer being in contact with the layer portion of the barrier layer.
► With respect to claim 17, Chen et al (fig 3-13, cols 3-6) disclose wherein in formation of the barrier layer (602, text [0038]), the insert portion of the barrier layer is formed to fill the opening (502, text [0037]).
► With respect to claim 19, Chen et al (fig 3-13, cols 3-6) disclose wherein after planarization of the bottom electrode layer (604, text [0038]), the bottom electrode layer is formed with an upper flat surface on which the ferroelectric layer (804, text [0040]) is formed.
► With respect to claim 21, Chen et al (fig 3-13, cols 3-6) disclose a method for manufacturing a semiconductor device, comprising:
forming an interconnect structure on a semiconductor substrate (308, text [0027]), the interconnect structure including a dielectric layer (122, text [0030]) and a conductive interconnect (106be, text [0025]) disposed in the dielectric layer;
depositing a barrier layer (602, text [0038]) on the interconnect structure opposite to the semiconductor substrate, the barrier layer including a layer portion disposed on the interconnect structure and an insert portion protruding from the layer portion to interface the conductive interconnect;
depositing a bottom electrode layer (604, 802, figs 6-8) on the barrier layer opposite to the interconnect structure;
planarizing the bottom electrode layer (604, 802, figs 6-8, text [0038]) so as to permit the bottom electrode layer to be formed with an upper flat surface;
depositing a ferroelectric layer (804, fig 8, text [0040]) on the upper flat surface of the bottom electrode layer opposite to the barrier layer; and
depositing a top electrode layer (806, , fig 8, text [0040]) on the ferroelectric layer opposite to the bottom electrode layer.
► With respect to claim 23, Chen et al disclose wherein an upper surface of the barrier layer (602, text [0038]) is formed with a notch, and the bottom electrode layer (604, text [0038]) is formed to fill the notch.
► With respect to claim 25, Chen et al disclose wherein each of the barrier layer (602, text [0038]) and the bottom electrode layer (604, text [0038]) includes titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, alloys thereof, or combinations thereof.
► With respect to claim 26, Chen et al (fig 3-13, cols 3-6) disclose wherein the barrier layer (602, text [0038]) and the bottom electrode layer (604, text [0038]) include different materials.
Claims 7-8, 10-11, 15-17, 19, 21, and 23-26 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Choi et al [US 2006/0183250].
► With respect to claim 7, Choi et al (figs 4A-6C, text [0001]-[0074]) disclose a method for manufacturing a semiconductor device, comprising:
forming an etch stop layer (413, fig 4B, text [0044]) with an opening (415, text [0044]);
forming a barrier layer (625,fig 6A, text [0065]) on the etch stop layer to fill the opening, the barrier layer including a layer portion disposed on the etch stop layer and an insert portion protruding from the layer portion so as to be inserted into the opening of the etch stop layer;
forming a bottom electrode layer (635, fig 6A, text [0065]]) on the layer portion of the barrier layer opposite to the etch stop layer;
forming a ferroelectric layer (640,fig 6B, text [0068]) on the bottom electrode layer opposite to the barrier layer; and
forming a top electrode layer (645,fig 6B, text [0069]) on the ferroelectric layer opposite to the bottom electrode layer.
► With respect to claim 8, Choi et al (figs 6A-6B) disclose further comprising, before formation of the ferroelectric layer (640, text [0068]), planarizing the bottom electrode layer (635, text [0067]) so as to permit the bottom electrode layer to be formed with an upper flat surface.
► With respect to claim 10, Choi et al disclose further comprising forming a mask layer (text [0070]) on the top electrode layer (645, text [0069]).
► With respect to claim 11, Choi et al disclose further comprising patterning the mask layer (text [0070]) and the top electrode layer (645, text [0069]) so as to form the mask layer and the top electrode layer (645a, text [0070]) into a mask and a top electrode, respectively, the mask cooperating with the top electrode to form a stack.
► With respect to claim 15, Choi et al (figs 4A-6C, text [0001]-[0074]) disclose a method for manufacturing a semiconductor device, comprising:
forming an interconnect structure on a semiconductor substrate (401, fig 4B, text [0041]), the interconnect structure including a dielectric layer (410, text [0043]) and a conductive interconnect (408a, text [0043]) disposed in the dielectric layer;
forming a first etch stop layer (413, fig 4B, text [0044]) on the interconnect structure;
forming on the first etch stop layer, a barrier layer (625, fig 6A, text [0065]) which includes a layer portion disposed on the first etch stop layer and an insert portion protruding from the layer portion and penetrating the first etch stop layer so as to be connected to the conductive interconnect;
forming a bottom electrode layer (635, fig 6A, text [0065]]) on the layer portion of the barrier layer opposite to the first etch stop layer;
planarizing the bottom electrode layer (635, fig 6B, text [0067]]);
forming a ferroelectric layer (640, fig 6B, text [0068]) on the bottom electrode layer opposite to the barrier layer; and
forming a top electrode layer (645, fig 6B, text [0069]) on the ferroelectric layer opposite to the bottom electrode layer.
► With respect to claim 16, Choi et al disclose further comprising, after formation of the first etch stop layer (413, text [0044]) and before formation of the barrier layer (625, text [0065]), patterning the first etch stop layer so as to form an opening (415, fig 4B, text [0044]) penetrating from an upper surface of the first etch stop layer to a lower surface of the first etch stop layer, the upper surface of the first etch stop layer being in contact with the layer portion of the barrier layer.
► With respect to claim 17, Choi et al disclose wherein in formation of the barrier layer (625, text [0065]), the insert portion of the barrier layer is formed to fill the opening (415, text [0044]).
► With respect to claim 19, Choi et al disclose wherein after planarization of the bottom electrode layer 635, text [0067]]), the bottom electrode layer is formed with an upper flat surface on which the ferroelectric layer (640, text [0068]) is formed.
► With respect to claim 21, Choi et al (figs 4A-6C, text [0001]-[0074]) disclose a method for manufacturing a semiconductor device, comprising:
forming an interconnect structure on a semiconductor substrate (401, fig 4B, zatext [0041]), the interconnect structure including a dielectric layer (410, text [0043]) and a conductive interconnect (408a, text [0043]) disposed in the dielectric layer;
depositing a barrier layer (420, 625, 630, fig 6A, text [0046],[0065]-[0066]) on the interconnect structure opposite to the semiconductor substrate, the barrier layer including a layer portion disposed on the interconnect structure and an insert portion protruding from the layer portion to interface the conductive interconnect;
depositing a bottom electrode layer (635, fig 6A, text [0065]]) on the barrier layer opposite to the interconnect structure;
planarizing the bottom electrode layer (635, fig 6B, text [0067]]) so as to permit the bottom electrode layer to be formed with an upper flat surface;
depositing a ferroelectric layer (640, fig 6B, text [0068]) on the upper flat surface of the bottom electrode layer opposite to the barrier layer; and
depositing a top electrode layer (645, fig 6B, text [0069]) on the ferroelectric layer opposite to the bottom electrode layer.
► With respect to claim 23, Choi et al disclose wherein an upper surface of the barrier layer (625, text [0065]) is formed with a notch, and the bottom electrode layer (604, text [0038]) is formed to fill the notch.
► With respect to claim 24, Choi et al disclose wherein the barrier layer (420, text [0046]) is formed with a void (S1, text [0046]) in the barrier layer.
► With respect to claim 25, Choi et al disclose wherein each of the barrier layer (420, 625, 630, text [0046],[0065]-[0066]) and the bottom electrode layer (635, text [0067]]) includes titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, alloys thereof, or combinations thereof.
► With respect to claim 26, Choi et al (fig 4 and 6, cols 4-7) disclose wherein the barrier layer (420, 625, 630, text [0046],[0065]-[0066]) and the bottom electrode layer (635, text [0067]]) include different materials.
Claims 7, and 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al [US 2022/0328508].
► With respect to claim 7, Lin et al (figs 1-20, text [0001]-[0135]) disclose the claimed method for manufacturing a semiconductor device, comprising:
forming an etch stop layer (316, fig 10, text [0091]) with an opening (1002, text [0091]);
forming a barrier layer (112, fig 11, text [0093]) on the etch stop layer to fill the opening, the barrier layer including a layer portion disposed on the etch stop layer and an insert portion protruding from the layer portion so as to be inserted into the opening of the etch stop layer;
forming a bottom electrode layer (1102, 1202, figs 11-12, text [0093], [0102]) on the layer portion of the barrier layer opposite to the etch stop layer;
forming a ferroelectric layer (108, fig 13, text [0108]) on the bottom electrode layer opposite to the barrier layer; and
forming a top electrode layer (1402,fig 14, text [0114]) on the ferroelectric layer opposite to the bottom electrode layer.
► With respect to claim 9, Lin et al disclose wherein the etch stop layer (316, text [0091]) has an upper surface in contact with the layer portion of the barrier layer (112, text [0093]) and a lower surface opposite to the upper surface; and the insert portion of the barrier layer is formed with a tapered configuration which is tapered in a direction from the upper surface of the etch stop layer to the lower surface of the etch stop layer.
► With respect to claim 10, Lin et al disclose further comprising forming a mask layer (308, fig 14, text [0115]) on the top electrode layer (1402, text [0114]).
► With respect to claim 11, Lin et al disclose further comprising patterning the mask layer (308, text [0115]) and the top electrode layer (1402, text [0114]) so as to form the mask layer and the top electrode layer into a mask and a top electrode, respectively, the mask cooperating with the top electrode to form a stack.
► With respect to claim 12, Lin et al disclose further comprising forming a spacer layer (312, fig 16, text [0117]) to cover the ferroelectric layer (108, text [0108]) and the stack.
► With respect to claim 13, Lin et al disclose further comprising etching the spacer layer (312, text [0117]) so as to form the spacer layer (312]) into a pair of spacers disposed on the ferroelectric layer to cover two lateral sides of the stack.
► With respect to claim 14, Lin et al disclose further comprising, after formation of the spacers, etching the ferroelectric layer (108, fig 17, text [0108]), the bottom electrode layer (1102, 1202, text [0093], [0102]), and the barrier layer (112, text [0093]) so as to form the ferroelectric layer, the bottom electrode layer, and the barrier layer into a ferroelectric element, a bottom electrode, and a barrier, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al [US 2020/0105772] in view of Gong et al [US 2024/0074207].
► With respect to claims 9 and 18, Chen et al substantially disclose the claimed method wherein the etch stop layer (124, text [0036]) has an upper surface in contact with the layer portion of the barrier layer (602, text [0038]) and a lower surface opposite to the upper surface; and the insert portion of the barrier layer is formed in an opening (502, text [0037]) in a direction from the upper surface of the etch stop layer to the lower surface of the etch stop layer. Chen et al do not disclose wherein the opening has a dimension decreasing gradually in a direction from the upper surface of the first etch stop layer to the lower surface of the first etch stop layer, such that the insert portion of the barrier layer is formed with a tapered configuration.
However, Gong et al (fig 3) discloses the opening (108, pp [0033]) having a dimension decreasing gradually in a direction from the upper surface to a bottom surface and formed with a tapered configuration.
Therefore, it would have been obvious to the skilled in the art to have the tapered configuration as taught by Gong et al into the method of Chen et al in order to provide the known purpose of filling the barrier layer in the opening easily.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/THANHHA S PHAM/Primary Examiner, Art Unit 2812
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